JP2811776B2 - Control signal generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control signal generation circuit for a fractionally spaced transversal filter used in an automatic interference canceling device in a digital microwave radio communication system.

[Conventional technology]

In recent years, digital microwave communication systems have shifted from interleaved transmission to channel transmission for efficient use of frequency, and from 4PSK (Phase Shift Keying).
Multi-value is progressing to 16QAM (Quadrature Amplitude Moduration). As the frequency utilization efficiency is increased in this way, problems such as cross-polarization interference and interference from a conventional analog microwave communication system become severe. Therefore, in order to remove these interferences, various automatic interference removal devices using a fractionally-spaced transversal filter that operates at a period that is a fraction of the code transmission period have been proposed.

As an example (first example) of such an automatic interference removal device,
An automatic interference canceling apparatus using a fractionally spaced transversal filter in the IF band will be described. The block diagram is shown in FIG.

Terminal 1 is an input terminal for a desired signal that has received interference, and terminal 2 is an input terminal for a signal that is an interference source. 31,32 is delay time T / 2
(T is the clock cycle of the transmission code)
46 is a weighting circuit, 51 and 52 are synthesis circuits, 6 is an orthogonal synthesis circuit, and 7 is an adder. Reference numerals 8 and 8a denote quadrature synchronous detection circuits (MIX); 81, a multiplier; and 82, a 90-degree transfer device. Also,
9 is a flip-flop circuit (F / F), 10 is a doubler circuit, 11 is a voltage-controlled carrier wave signal oscillator, 12 is a voltage-controlled clock oscillator, and 13 and 13a are analog / digital conversion circuits (A / D). is there. 100a is a control signal generation circuit (CONI).

Signal as interference source input from terminal 2 (interference signal)
Is divided into four, one is a delay line 31, and two are weighting circuits.
Signals proportional to the weighted control signals R-1, I-1 which are outputs of the control signal generation circuit 100a input to 41, 46 are output. Similarly, the output signals of the delay lines 31 and 32 are
2, 43, 45, 44, respectively, and weighted control signals R0, R
A signal proportional to 1, I0, I1 is output. The remaining one signal is input to the quadrature synchronous detection circuit 8a, which performs synchronous detection at the output (CARR) of the voltage-controlled carrier signal oscillator 11, and outputs in-phase and quadrature synchronous detection signals. This synchronous detection signal is input to the F / F 9 and a clock signal CL having a frequency twice as high as the output frequency of the voltage controlled clock oscillator 12 is output.
It discriminates and determines by K (T / 2), performs binary conversion, and outputs quadrant determination signals (D _P , D _Q ) to the control signal generation circuit 100a.

The outputs of the weighting circuits 41 to 43 and the outputs of 44 to 46 are input to synthesis circuits 51 and 52, respectively, to output a synthesized signal, and input to the orthogonal synthesis circuit 6. The orthogonal combining circuit 6 combines the output signal of the combining circuit 52 with the output of the combining circuit 51 by delaying the phase by π / 2, and outputs the combined signal. The output of the quadrature synthesis circuit 6 and the desired signal input from the terminal 1 are added by the adder 7 and input to the quadrature synchronous detection circuit 8. In the quadrature synchronous detection circuit 8,
The input from the adder 7 is synchronously detected by the output (CARR) of the voltage-controlled carrier signal oscillator 11, and the in-phase and quadrature synchronous detection signals are input to the A / Ds 13 and 13a. _P, and E _Q are identified playback. Regenerating the data signal to the outside, also, the error signal E _P, E _Q are output to the control signal generating circuit 100a. Here, the error signals E _P and E _Q are amounts proportional to various interference signals (thermal noise, cross-polarization interference, etc.) included in the desired signal, and represent the least significant bit of the identification reproduction data signal. It can be obtained by taking.

FIG. 6A is a block diagram of a conventional example (first conventional example) of the control signal generation circuit 100a.

101 to 104 are shift register circuits (SR), 105 to 110 are flip-flop circuits (F / F), 111 to 119 are exclusive OR circuits (EX-OR), and 120 to 122 are exclusive OR circuits ( EX-NOR), 123 to 128 indicate adders, and 129 to 134 indicate integration circuits.

The input quadrant determination signals D _P , D _Q and error signals E _P , E _Q are input to shift register circuits 101-104 capable of delaying an arbitrary number of bits, and the quadrant determination signals are output from the shift register circuits 101-104. The delay time difference between D _P and D _Q and the error signals E _P and E _Q is removed. The error signal E _P-1 output from the shift register circuit 103 passes through two cascade-connected F / Fs 107 and 108, and the error signals E _P0 and E have a delay time difference of T / 2 seconds from the F / Fs 107 and 108, respectively. Outputs _P1 . Error signal E _Q-1 error signal E _G0 Similarly for,
E _Q1 is output. Also, the quadrant judgment signals D _P and D _Q are F / F105,1
At 06, D _P0 and D _Q0 are output with a delay of T / 2 seconds. These quadrant judgment signals D _P0 , D _Q0 and error signals E _{P ± 1} , E _P0 , E _{Q ± 1} , E
_Q0 is a correlation signal detection circuit EX-OR111 to 119 or EX
-Input to NORs 120 to 122. The outputs of EX-ORs 111 and 112 are the correlations (D _P0 E _P−1 , D _Q0) between the quadrant determination signal D _P0 and the error signal E _P−1 , and the quadrature determination signal D _Q0 and the error signal E _Q−1 , respectively.
E _Q-1 ; is an exclusive OR operation. EX
-The outputs of OR 111 and 112 are input to adder 123 and D _P0 E
_P-1 + _{DQ0EQ -1} is calculated, averaged over time by the integrator 129, and output as a weighted control signal R- ₁ . In the same manner, the EX-ORs 113 to 119 and EX-NORs 120 to 122 take the correlation between their respective inputs and output a correlation signal. These output signals are input to adders 124 to 128, respectively. (I _-1 ), (R ₀ ), (I ₀ ), (R ₊₁ ),
(I ₊₁ ) is output. These adder output signals are input to the integrators 130 to 134, averaged over time, and output as weighted control signals I- ₁ , _R0 , I0, R _{+ 1} , I _{+ 1} . When the outputs of the weighting circuits 41 to 46 are controlled by the weighting control signals R ₀ , R ± 1, I0, I ± 1 thus obtained, the adder 7
, The error value of the interference component due to the interference source signal input from the terminal 2 is guaranteed to be the minimum in the sense of the square error. That is, the output signal of the adder 7 is input from the terminal 2 and the interference component due to the interference source signal has been removed.

Similarly, even if the fractionally spaced transversal filter is configured in the baseband or all digital, the operating principle is the same.
This is the same as when a fractionally spaced transversal filter is configured in the IF band. Block diagrams of one example (second and third examples) of the automatic interference canceling device in these cases are shown in FIGS. 5 (b) and 5 (c). FIGS. 6 (b) and 6 (b) are block diagrams of conventional examples (second and third conventional examples) of the control signal generation circuits 100b and 100c in FIGS. 5 (b) and 5 (c).
It is shown in (c).

In the automatic interference elimination device shown in FIG. 5B or 5C, there are two in-phase and quadrature systems of the synchronous detection signal or the synchronous detection signal from which the interference component is to be eliminated. It is one. Therefore, in the conventional example shown in FIGS. 6B and 6C, adders 123 to 128 are removed from the conventional example shown in FIG. 6A so as to control two transversal filters.
Output of OR111 ~ 119, EX-NOR120 ~ 122 is directly integrator 137-1
Weighting control signal is input to the 48 or the up-down counter _{149~160 CR P0, CR P ± 1} , CR Q0, CR Q ± 1, CI P0, CI
_{P ± 1} , CI _Q0 and CI _{Q ± 1} are obtained.

[Problems to be solved by the invention]

The above-described conventional control signal generation circuit includes error signals E _P and E _Q
Is the signal identified with the period T, but the period
Since it is operated at T / 2, there is a disadvantage that the operation becomes unstable.

This will be further described with reference to timing charts shown in FIGS. 7A to 7H which are common to the first to third conventional examples.

7, (a) and (b) are timing charts of quadrant determination signals D _P and D _Q output by S.R 101 and 102,
(C), (d) the error signal E _P which S.R103,104 is output, E _Q
3 shows a timing chart. In the numbers following each symbol, 0 indicates the current time, 1 indicates a half bit delay, and -1 indicates a half bit advance. (E) shows a timing chart of D _P (D _Q ) which is an output of the F / F 105 (106), and (f) shows a timing chart of E _P (E _Q ) which is an output of the F / F 107 (109). .
(G) and (h) are EX-OR111 (112) and 114 (11), respectively.
The timing chart of the output of 5) is shown.

Here, the output of the F / F 107 (109) (FIGS. 6A to 6C)
E _P0 (E _Q0)) in each S.R103 (104) output (FIG. 6 _{(a) ~ E P-1} (E Q-1) in (c)) of the clock No. CLK (T / 2) It is a signal that was just punched out with S.R1
T.2 seconds later than the 03 (104) output, but S.R103 (104)
From the output: E _P-2 (E _Q-2 ), E _P0 (E _Q0 ), E _P2 (E _Q2 ) ... From E _P-1 (E _Q-1 ), E _P1 (E _Q1 ) , E _P1 (E _Q1 ), E
_P3 ( _EQ3 ) …… was not necessarily obtained. That is, the synchronous detection signal obtained by synchronously detecting the desired signal is
CLK (T / 2) error signal to be obtained by regenerating with E _P, E _Q
Error signal of the odd-numbered cycle of the clock signal CLK (T / 2) in the time series of E.sub.P _-1 (E _Q-1 ), E _P1 (E _Q1 ), E _P3 (E _Q3 )
... is not actually obtained. Therefore, among the EX-OR or EX-NOR outputs, an error signal of an odd-numbered cycle of the clock signal CLK (T / 2)... EP _-1 ( _EQ-1 ), _EP3 ( _EQ3 ).
The output that should include ... E _P-2 (E _Q-2 ), E _P0 (E _Q0 ), E _P2 (E
_Q2 ) These outputs are not used, and these outputs do not contain effective information for obtaining the weighted control signal. If these invalid outputs are uncorrelated with each other and disappear as a result of integration, there is no real harm.However, since they do not become uncorrelated due to imperfect circuit configuration, etc., the control operation becomes unstable, and this unstable operation is compensated. If so, a complicated compensation circuit is required, and the circuit scale becomes large.

[Means for solving the problem]

According to a first aspect of the present invention, a control signal generating circuit includes: an intermediate frequency band fractionally spaced transversal filter for inputting an intermediate frequency band interference source signal; and an interference source signal quadrature detection device for performing orthogonal synchronous detection of the intermediate frequency band interference source signal. A synchronous detection circuit, and a baseband interference source signal output from the interference source signal quadrature synchronous detection circuit, sampled and identified by operation synchronization of the fractionally spaced transversal filter, and a quadrant of the intermediate frequency interference source signal. A quadrature determination signal generating means for outputting a determination signal, and an adder for inputting a desired signal in the intermediate frequency band which is being interfered by the interference source signal in the intermediate frequency band and a signal output from the fractionally spaced transversal filter. When,
A desired signal quadrature synchronous detection circuit for performing quadrature synchronous detection of the signal output by the adder; and a baseband band desired signal output by the desired signal quadrature synchronous detection circuit. Analog output
A desired signal in the intermediate frequency band is converted into an interference signal in the intermediate frequency band based on the quadrant determination signal and the error signal by using a weighting control signal for the fractionally spaced transversal filter of the intermediate frequency type automatic interference elimination device including a digital conversion circuit. A control signal generating circuit for generating interference received from a source signal so as to be canceled by a signal output from the fractionally spaced transversal filter, wherein a delay time difference between the input quadrant determination signal and the error signal is provided. , A gate circuit for inhibiting the output of the error signal output by the delay time difference compensating means in the latter half cycle of each time slot of the error signal, the error signal output by the gate circuit, The quadrant determination signal output from the delay time difference compensating means is input and the fractional interval type transversal is used. A flip-flop circuit for obtaining a delay time corresponding to a delay time of each tap of the filter; and an exclusive-OR circuit for inputting the error signal and the quadrant determination signal output from each of the flip-flop circuits, or Correlation detection means for detecting a cross-correlation between the error signal and the quadrant determination signal output from each of the flip-flop circuits including an exclusive OR circuit, and outputting a correlation detection signal; and averaging the correlation detection signal. Averaging means for outputting the weighted control signal.

A control signal generating circuit according to a second aspect of the present invention includes an interference source signal quadrature synchronous detection circuit for performing quadrature synchronous detection of an intermediate frequency band interference source signal, and a baseband interference source signal output from the interference source signal quadrature synchronous detection circuit. And a base band band fractional transversal filter having an input, and sampling and identifying the interference source signal of the base band in the operation cycle of the fractional band transversal filter to obtain an interference source signal of the intermediate frequency band. A quadrant determination signal generating means for outputting the signal as a quadrant determination signal; a desired signal quadrature synchronous detection circuit for performing quadrature period detection of a desired signal in an intermediate frequency band which is receiving interference from the interference source signal in the intermediate frequency band; An adder that inputs a desired signal in the baseband band output by the synchronous detection circuit and a signal output by the fractionally spaced transversal filter; Weighting control signal for the fractional interval type transversal filter of the baseband type automatic interference canceller, comprising: an analog-to-digital conversion circuit that identifies and reproduces the signal output by the adder and outputs an identification reproduction desired data signal and an error signal. Is generated based on the quadrant determination signal and the error signal so that the interference of the desired signal in the baseband from the interference source signal in the intermediate frequency band is canceled by the signal output from the fractionally spaced transversal filter. Control signal generating circuit,
Delay time difference compensating means for reducing the delay time difference between the input quadrant determination signal and the error signal to zero, and the output of the latter half cycle of each time slot of the error signal output by the delay time difference compensating means. A gate circuit to be inhibited, and a delay time corresponding to a delay time of each tap of the fractionally spaced transversal filter which receives the error signal output from the gate circuit and the quadrant determination signal output from the delay time difference compensating means as inputs. And an exclusive-OR circuit or an exclusive-OR NOT circuit for inputting the error signal and the quadrant determination signal respectively output from the flip-flop circuits. Detect the cross-correlation of the error signal and the quadrant judgment signal output by A correlation detecting means for outputting a signal output,
Averaging means for averaging the correlation detection signal and outputting the result as the weight control signal.

A control signal generation circuit according to a third aspect of the present invention includes a desired signal quadrature synchronous detection circuit for performing quadrature synchronous detection of a desired signal in an intermediate frequency band which is receiving interference from an interference source signal in the intermediate frequency band, and the desired signal quadrature synchronous detection circuit A first analog-to-digital conversion circuit for recognizing and reproducing a desired signal in the base band, an interference source signal quadrature synchronization detection circuit for performing quadrature synchronization circular waves on the interference source signal in the intermediate frequency band, A second analog / digital conversion circuit for discriminating and reproducing the baseband interference signal output from the synchronous detection circuit at an operation speed that is an integral multiple of the operation speed of the first analog / digital conversion circuit; An all-digital fractionally-spaced transversal filter that receives an interference source data signal output from an analog-to-digital conversion circuit, and a fractionally-spaced transversal filter A digital adder for adding an output data signal of the filter and an output data signal of the first analog-digital conversion circuit and outputting a desired data signal for identification and reproduction and an error signal; The weighted control signal of the interval type transversal filter is converted into an output data signal of the first analog-to-digital conversion circuit based on a quadrant determination signal, which is the most significant bit of the interference source data signal, and the error signal. A control signal generation circuit for generating interference so as to cancel interference received from a source signal by a data signal output from the fractionally spaced transversal filter, wherein a delay between the input quadrant determination signal and the error signal is provided. Delay time difference compensating means for reducing the time difference to zero, and the delay time difference compensating means outputs A gate circuit for inhibiting the output of the error signal in the latter half of each time slot, and the error signal output from the gate circuit and the quadrant determination signal output from the delay time difference compensating means as inputs. A flip-flop circuit for obtaining a delay time corresponding to a delay time of each tap of the interval type transversal filter; and an exclusive input for inputting the error signal and the quadrant determination signal output from each of the flip-flop circuits. Correlation detection means for detecting a cross-correlation between the error signal and the quadrant determination signal output from each of the flip-flop circuits including an OR circuit or an exclusive OR circuit, and outputting a correlation detection signal; and the correlation detection signal. And an averaging means for averaging and outputting the weighted control signal.

According to a fourth aspect of the present invention, there is provided a control signal generating circuit comprising: an intermediate frequency band fractionally spaced transversal filter which receives an intermediate frequency band interference source signal; and an interference source signal which performs quadrature synchronous detection of the intermediate frequency band interference source signal. A quadrature synchronous detection circuit, and a baseband interference signal output by the quadrature synchronous detection circuit is sampled and identified at an operation cycle of the fractionally spaced transversal filter, and an interference source signal of the intermediate frequency band is detected. A quadrant determination signal generating means for outputting as a quadrant determination signal; and an addition for inputting a desired signal in the intermediate frequency band which is being interfered by the interference source signal in the intermediate frequency band and a signal output from the fractionally spaced transversal filter. Signal, a quadrature synchronous detection circuit for quadrature synchronous detection of the signal output from the adder, and a baseband output from the quadrature synchronous detection circuit for desired signal. And an analog-to-digital conversion circuit for identifying and reproducing a desired signal in the band and outputting an identified and reproduced desired data signal and an error signal. Control for generating a desired signal in the intermediate frequency band based on the quadrant determination signal and the error signal so as to cancel an interference received from the interference source signal in the intermediate frequency band by a signal output from the fractionally spaced transversal filter. A signal generation circuit, comprising: a delay time difference compensating unit for setting a delay time difference between the input quadrant determination signal and the error signal to zero; and a quadrature determination signal and the error signal output by the delay time difference compensating unit. Delay time corresponding to the delay time of each tap of the fractionally spaced transversal filter as input A first flip-flop circuit for obtaining, and an exclusive-OR circuit or an exclusive-OR NOT circuit for inputting the quadrant determination signal and the error signal respectively output from the first flip-flop circuits. Correlation detection means for detecting a cross-correlation between the quadrant determination signal and the error signal output from each of the first flip-flop circuits and outputting a correlation detection signal, and converting the correlation detection signal into a code transmission cycle of the desired signal. It includes a second flip-flop circuit for re-sampling, and averaging means for averaging the output of the second flip-flop circuit and outputting the result as the weight control signal.

According to a fifth aspect of the present invention, there is provided a control signal generation circuit comprising: an interference source signal quadrature synchronization detection circuit for performing quadrature synchronization detection of an intermediate frequency band interference source signal; and a baseband interference source signal output by the interference source signal quadrature synchronization detection circuit. And a base band band fractional transversal filter having an input, and sampling and identifying the interference source signal of the base band in the operation cycle of the fractional band transversal filter to obtain an interference source signal of the intermediate frequency band. A quadrant determination signal generating means for outputting as a quadrant determination signal; a desired signal quadrature synchronous detection circuit for performing quadrature synchronous detection of a desired signal in an intermediate frequency band which is receiving interference from the interference source signal in the intermediate frequency band; An adder that inputs a desired signal in the baseband band output by the synchronous detection circuit and a signal output by the fractionally spaced transversal filter; Weighting control signal for the fractional interval type transversal filter of the baseband type automatic interference canceller, comprising: an analog-to-digital conversion circuit that identifies and reproduces the signal output by the adder and outputs an identification reproduction desired data signal and an error signal. Is generated based on the quadrant determination signal and the error signal so that the interference that the desired signal in the baseband receives from the interference signal in the intermediate frequency band is canceled by the signal output from the fractionally spaced transversal filter. A control signal generation circuit, comprising: a delay time difference compensating means for reducing a delay time difference between the input quadrant determination signal and the error signal to zero; and the quadrant determination signal and the error signal output by the delay time difference compensating means. And the delay time of each tap of the fractionally spaced transversal filter. A first flip-flop circuit for obtaining a delay time, and an exclusive-OR circuit or exclusive-OR NOT receiving the quadrant determination signal and the error signal output from each of the first flip-flop circuits. A correlation detection means for detecting a cross-correlation between the quadrant determination signal and the error signal output from each of the first flip-flop circuits and outputting a correlation detection signal; The second flip-flop circuit includes a second flip-flop circuit for re-sampling at a transmission cycle, and averaging means for averaging an output of the second flip-flop circuit and outputting the result as the weight control signal.

A control signal generating circuit according to a sixth aspect of the present invention includes a desired signal quadrature synchronous detection circuit for performing quadrature synchronous detection of a desired signal in an intermediate frequency band which is receiving interference from an interference source signal in the intermediate frequency band, and the desired signal quadrature synchronous detection circuit. A first analog-to-digital conversion circuit for recognizing and reproducing the desired signal in the baseband output from the first and second interferometers; an interference source signal quadrature synchronous detection circuit for performing quadrature synchronous detection of the interference source signal in the intermediate frequency band; A second analog / digital conversion circuit for discriminating and reproducing the baseband interference signal output from the synchronous detection circuit at an operation speed that is an integral multiple of the operation speed of the first analog / digital conversion circuit; An all-digital fractionally-spaced transversal filter that receives the interference source data signal output by the analog-to-digital conversion circuit; A digital adder for adding an output data signal of a monkey filter and an output data signal of the first analog-to-digital conversion circuit to output a desired data signal for identification and reproduction and an error signal; The output data signal of the first analog-to-digital converter is converted to the weighted control signal of the fractionally spaced transversal filter based on the most significant bit of the interference source data signal and the error signal. A control signal circuit for generating interference so as to cancel interference received from an interference source signal by a data signal output from the fractionally spaced transversal filter, wherein a delay between the input quadrant determination signal and the error signal is provided. Delay time difference compensating means for reducing the time difference to zero, and the delay time difference compensating means outputs A first flip-flop circuit for receiving the quadrant determination signal and the error signal as inputs and obtaining a delay time corresponding to a delay time of each tap of the fractionally-spaced transversal filter; and the first flip-flop, respectively. The quadrant determination signal output from each of the first flip-flop circuits including an exclusive OR circuit or an exclusive OR NOT circuit that inputs the quadrant determination signal and the error signal output from each of the circuits; and Correlation detection means for detecting a cross-correlation of the error signal and outputting a correlation detection signal, a second flip-flop circuit for re-sampling the correlation detection signal in a code transmission cycle of the desired signal, and a second flip-flop circuit And an averaging means for averaging the outputs of the above and outputting as the weighted control signal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 (a) is a block diagram of one embodiment of the first invention,
FIG. 2 is a timing chart of signals of various parts of this embodiment.

The embodiment 100aa shown in FIG. 1 (a) is an embodiment used as the control signal generating circuit 100a of the automatic interference canceller shown in FIG. 5 (a) using a fractionally spaced transversal filter in the IF band. 101 to 104 are shift register circuits (SR) which are delay time difference compensating means in claim 1;
110 is a flip-flop circuit (F / F) which is a flip-flop circuit according to claim 1, 111 to 119 and 120 to 122 are exclusive OR circuits (EX-OR) constituting a correlation detecting means according to claim 1; Exclusive OR circuit (EX
−NOR), 123 to 128 are adders, 129 to 134 are integrators which are averaging means in the first aspect, and 135 and 136 are AND circuits which are gate circuits in the first aspect.

Embodiment shown in FIG. 1 (a) as input quadrant decision signals D _P, D _Q and the error signal E _P, the E _Q, the shift register circuit 101 to
At 104, each delay time zone is set to 0. The waveforms of the outputs of the shift register circuits 101 to 104 at this time are shown in FIGS. In the numbers of the symbols, 0 indicates a signal at the present time, +1 indicates a signal delayed by T / 2 seconds, and -1 indicates a signal advanced by T / 2 seconds.

The outputs of the shift register circuits 103 and 104 are AND circuits 135 and 136
Is input to one of the two inputs. Also, AND circuits 135 and 136
The other one of the two inputs is provided with a clock signal CLK having a period T.
(T) is input, and therefore, the AND circuits 135 and 136 inhibit the output of the second half T / 2 seconds of the output of the shift register circuits 103 and 104,
"L" is output (FIG. 2 (e)).

AND circuit 135 (136) output (E _P-1 in FIG. 1 (a))
(EQ _-1 )) are two cascaded F / Fs 107, 108 (109, 11).
0), and the respective time differences are T / 2 seconds E
_P-1 , _EP0 , and _EP1 ( _{PQ -1} , _EQ0 , and _EQ1 ) are created (FIGS. 2 (e) and 2 (g)). Similarly, the quadrant judgment signal D _P (D _Q )
Is also input to the F / F 105 (106), and E _P0 in FIG.
A signal D _P0 (D _Q0 ) at the same time as (E _Q0 ) is created (FIG. 2 (f)). These signals are input to EX-ORs 111 to 119 or EX-NORs 120 to 122, respectively, which are correlation detection circuits.

The EX-ORs 111 to 119 (or EX-NORs 120 to 122) output the error signals E _P0 , E _{P ± 1} , E _Q0 , E _{Q ± 1} among the input signals, which are fixed to “L” for the latter half T / 2 seconds. Therefore, at this timing, the quadrant determination signals D _P0 and D _Q0 are output as they are (FIG. 2 (h),
(I)). The outputs of EX-ORs 111 to 119 (or EX-NORs 120 to 122) are input to adders 123 to 128, respectively.
28 outputs are input to the integrators 129 to 134, and RO, R ± 1, I0, and I ± 1, which are weighting control signals for each tap, are output.

Here, each weight control signal is EX-OR 111 to 119 (or
EX-NOR120-122) The output is an integrated signal, and
Since the components of the quadrant judgment signals D _P0 and D _Q0 are random signals, the quadrature judgment signal is uncorrelated with the error signal after integrating the output signal as it is, so the weighting control signal is the correlation of each tap. The amount is proportional to the detection signal.
Therefore, the operation does not become unstable unlike the control operation of the conventional example shown in FIG. 6 (a).

FIG. 1 (b) is a block diagram of one embodiment of the second invention. Embodiment 100ba shown in FIG. 1 (b) is a fifth embodiment using a fractionally spaced transversal filter in the baseband.
The control signal generation circuit 10 of the automatic interference canceller shown in FIG.
This is an example used as 0b. FIG. 1 (c) shows the third
FIG. 2 is a block diagram of an embodiment of the present invention. Embodiment 100ca shown in FIG. 1 (c) is an embodiment used as a control signal generating circuit 100c of the automatic interference canceller shown in FIG. 5 (c) using an all-digital fractionally spaced transversal filter. The embodiment shown in FIGS. 1 (b) and 1 (c) prevents the generation of an erroneous correlation detection signal by providing the AND circuits 135 and 136 in the embodiment shown in FIG. 1 (a). Is the same as

FIG. 3 (a) is a block diagram of one embodiment of the fourth invention,
FIG. 4 is a timing chart of signals of respective parts of this embodiment.

The embodiment 100ab shown in FIG. 3 (a) is an embodiment used as the control signal generation circuit 100a of the automatic interference canceller shown in FIG. 5 (a) using a fractionally spaced transversal filter in the IF band. 101 to 104 are shift register circuits (S.
R), 105 to 110 are flip-flops (F / F) which are first flip-flop circuits in claim 4, and 161 to 172 are flip-flops (F / F) which are second flip-flop circuits in claim 4. , 111 to 119 are exclusive OR circuits (EX-OR), and 120 to 122 are exclusive OR NOT circuits (EX-NO).
R), 123 to 128 are adders, 173 is a NOT circuit, and 129 to 134 are integrators.

The operation of the embodiment shown in FIG.
D _P , D _Q and error signals E _P , E _Q are input, and the shift register circuits 101 to 104 eliminate the bit delay time difference between the respective signals, and the error signals E _P , E _Q each use two F / Fs. Street E
_{A signal of P (Q) ± 1} , E _{P (Q) 0} is created, and a quadrant judgment signal D _P ,
D _Q goes through one F / F to create D _P0 and D _Q0 signals, respectively.
EX-ORs 111 to 119 which are correlation detection circuits for each tap, respectively.
Alternatively, the operation is the same as that of the conventional example shown in FIG. 6A until the signals are input to the EX-NORs 120 to 122 and the respective correlation signals are generated.

Accordingly, as shown in FIGS. 4 (g) and 4 (h), the correlation signals also show error signals E _{P (Q) −1} , E _{P (Q) 1} ,.
And the correlation signal to be produced by the error signal E _{P (Q) -2} , E _{P (Q) 0} ,. However, when the correlation signals including these erroneous signals are re-sampled by the F / Fs 161 to 172 using the clock CLK (T) having the period T or a clock having the opposite phase (the output of the negation circuit 173), the F / Fs 161 to 172
As shown in FIGS. 4 (i) and 4 (j), the output is such that an erroneous correlation signal is removed when viewed in time series, and a normal correlation signal is obtained. Therefore, the transversal filter can be stably controlled with a relatively simple circuit configuration by adding and integrating these correlation signals.

FIG. 3 (b) is a block diagram of one embodiment of the fifth invention. The embodiment 100bb shown in FIG. 3 (b) is a fifth embodiment using a fractionally spaced transversal filter in the baseband.
The control signal generation circuit 10 of the automatic interference canceller shown in FIG.
This is an example used as 0b. FIG. 3 (c) shows the sixth
FIG. 2 is a block diagram of an embodiment of the present invention. The embodiment 100cb shown in FIG. 3 (c) is an embodiment used as the control signal generating circuit 100c of the automatic interference canceller shown in FIG. 5 (c) using an all-digital fractionally spaced transversal filter. The embodiment shown in FIGS. 3B and 3C is the F / F161.
172 is the same as in the embodiment shown in FIG. 3 (a).

Each of the above-described embodiments is directed to a three-tap fractionally spaced transversal filter. However, even when the number of taps is other than three, any of the first to sixth inventions is applied. The same effect can be obtained.

〔The invention's effect〕

As described above, the first to third inventions allow the latter half bit of the error signal to be inhibited by passing the error signal and the clock signal having the period T through the gate. By re-sampling the correlation signal with a clock signal having a period T, it is possible to obtain a stable transversal filter control signal with a relatively simple circuit configuration.

In the first to sixth inventions, since an erroneous correlation signal can be eliminated by using an IC gate, an LSI can be easily realized,
This has the effect of reducing size and reducing power consumption.

[Brief description of the drawings]

FIG. 2 is a block diagram showing one embodiment of each of the first to third inventions. FIG. 2 is a timing chart of signals of respective parts common to each embodiment shown in FIGS. 1 (a) to 1 (c). (A) ~
(C) is a block diagram showing one embodiment of each of the fourth to sixth inventions, and FIG. 4 is a timing chart of signals of respective parts common to each embodiment shown in FIGS. 3 (a) to (c). 5 (a) to 5 (c) are block diagrams showing first to third examples of an automatic interference canceling device, and FIGS. 6 (a) to (c) are first to third examples of a conventional control signal generating circuit. FIG. 7 is a block diagram showing a third example, and FIG. 7 is a timing chart of signals of respective parts common to the conventional examples shown in FIGS. 6 (a) to 6 (c). 1 ... desired signal input terminal, 2 ... interference source signal input terminal,
6 quadrature synthesis circuit, 7 adder, 8, 8a quadrature synchronous detection circuit, 9 flip-flop circuit, 10 double multiplier circuit, 11 voltage-controlled carrier signal oscillator, 12 … Voltage-controlled clock oscillator, 13,13a to 13c …… Analog
Digital conversion circuit, 14,14a-14c, 15,15a, 18,18a-18c
…… Adder, 17,17a …… Transversal filter, 3
1,31a, 31b, 32,32a, 32b ... delay line, 41-46,41a-41a, 41
b to 41b ... weighting circuits, 51, 51a, 51b, 52, 52a, 52b ...
Combining circuit, 81,174-179 …… Multiplier, 82… 90 degree phase shifter, 91-95… Flip-flop circuit, 100a-100c, 100
aa ~ 100ac, 100ca ~ 100cc ... Control signal generation circuit, 101-1
04 shift register, 105-110, 161-172 flip-flop circuit, 111-119 exclusive OR circuit, 120
... 122 exclusive OR NOT circuit, 123-128 adder, 129-134,137-148 ... integrator, 135,136 ... AND circuit, 149-160 ... up-down counter, 173 ... not circuit.

Claims (6)

(57) [Claims] 1. An intermediate frequency band fractionally spaced transversal filter that receives an intermediate frequency band interference source signal as an input, an interference source signal quadrature synchronous detection circuit that performs quadrature synchronous detection of the intermediate frequency band interference source signal, The baseband interference source signal output by the interference source signal quadrature synchronous detection circuit is sampled and identified by operation synchronization of the fractionally spaced transversal filter, and is output as a quadrant determination signal of the intermediate frequency interference source signal. A quadrant determination signal generating means, an adder for inputting a desired signal in the intermediate frequency band which is receiving interference from the interference source signal in the intermediate frequency band, and a signal output from the fractionally spaced transversal filter; A desired signal quadrature synchronous detection circuit for quadrature synchronous detection of the signal output by
An analog-to-digital conversion circuit that identifies and reproduces a desired signal in the baseband output from the desired signal quadrature synchronous detection circuit and outputs an identification-reproduced desired data signal and an error signal. The fractional interval type transversal filter receives the interference in which the desired signal of the intermediate frequency band is received from the interference source signal of the intermediate frequency band based on the quadrant determination signal and the error signal. A control signal generation circuit generated so as to cancel by the output signal, wherein a delay time difference compensating means for reducing a delay time difference between the input quadrant determination signal and the error signal to zero, and the delay time difference compensating means are A gate circuit for inhibiting output of the output error signal in the latter half cycle of each time slot of the error signal; A flip-flop for receiving the error signal output by the gate circuit and the quadrant determination signal output by the delay time difference compensating means to obtain a delay time corresponding to a delay time of each tap of the fractionally spaced transversal filter. A circuit, and an exclusive OR circuit or an exclusive OR circuit that inputs the error signal and the quadrant determination signal respectively output from the flip-flop circuits. A control comprising: a correlation detection unit that detects a cross-correlation between an error signal and the quadrant determination signal and outputs a correlation detection signal; and an averaging unit that averages the correlation detection signal and outputs the result as the weighted control signal. Signal generation circuit. 2. An interference source signal quadrature synchronous detection circuit for performing quadrature synchronous detection of an intermediate frequency band interference source signal, and a baseband receiving the baseband interference signal output from the interference source signal quadrature synchronous detection circuit. A band fractional interval type transversal filter, and sampling and identifying the baseband band interference source signal at an operation cycle of the fractional interval type transversal filter and outputting the same as an elephant determination signal of the intermediate frequency band interference source signal A quadrature determination signal generating means, a desired signal quadrature synchronous detection circuit for performing quadrature period detection of a desired signal in the intermediate frequency band which is receiving interference from the interference source signal in the intermediate frequency band, and an output of the desired signal quadrature synchronous detection circuit. An adder for inputting the desired signal in the baseband band and the signal output from the fractionally spaced transversal filter, and an output from the adder An analog-to-digital conversion circuit that outputs a desired data signal and an error signal by discriminating and reproducing a signal, the weighting control signal of the fractionally-spaced transversal filter of the baseband type automatic interference canceller, and the quadrant determination signal and A control signal generating circuit for generating, based on the error signal, a desired signal in the baseband band to cancel interference received from the interference source signal in the intermediate frequency band by a signal output from the fractionally spaced transversal filter. A delay time difference compensating means for reducing a delay time difference between the input quadrant determination signal and the error signal to zero; and a second half half cycle of each time slot of the error signal output by the delay time difference compensating means. A gate circuit for inhibiting the output of the error signal, and the error signal and the delay output by the gate circuit. A flip-flop circuit for receiving the quadrant determination signal output by the difference compensating means as an input and obtaining a delay time corresponding to a delay time of each tap of the fractionally spaced transversal filter; and A cross-correlation between the error signal and the quadrant determination signal output from each of the flip-flop circuits including an exclusive OR circuit or an exclusive OR NOT circuit that inputs the output error signal and the quadrant determination signal is provided. A control signal generation circuit, comprising: a correlation detection unit that detects and outputs a correlation detection signal; and an averaging unit that averages the correlation detection signal and outputs the result as the weighted control signal. 3. A quadrature synchronous detection circuit for quadrature synchronous detection of a desired signal in an intermediate frequency band which is receiving interference from an interference source signal in the intermediate frequency band, and a baseband band output from the quadrature synchronous detection circuit in the desired signal. 1 for discriminating and reproducing the desired signal
An analog-to-digital conversion circuit, an interference source signal quadrature synchronous detection circuit that performs quadrature synchronous detection of the intermediate frequency band interference source signal, and a baseband interference source signal output by the interference source signal quadrature synchronous detection circuit. A second analog-to-digital converter for discriminating and reproducing at an operation speed that is an integral multiple of the operation speed of the first analog-to-digital converter, and an interference source data signal output from the second analog-to-digital converter as an input; An all-digital fractionally-spaced transversal filter, an output data signal of the fractionally-spaced transversal filter, and an output data signal of the first analog-to-digital conversion circuit, and a discrimination / reproduction desired data signal and an error signal And a digital adder that outputs the data as a digital signal. An output data signal of the first analog-to-digital conversion circuit is used as an interference source signal in the intermediate frequency band based on a quadrant determination signal, which is the most significant bit of the interference source data signal, and the error signal. A control signal generating circuit for generating interference so as to cancel out the interference received from the data signal output from the fractionally spaced transversal filter, wherein a delay time difference between the input quadrant determination signal and the error signal is calculated. A delay time difference compensating means for setting to zero, a gate circuit for inhibiting the output of the error signal output by the delay time difference compensating means in the latter half cycle of each time slot; the error signal output by the gate circuit; The quadrant judgment signal output from the delay time difference compensating means is input and the fractionally spaced transversal signal is input. A flip-flop circuit for obtaining a delay time corresponding to the delay time of each tap of the filter, and an exclusive-OR circuit for inputting the error signal and the quadrant determination signal output from each of the flip-flop circuits, or Correlation detection means for detecting a cross-correlation between the error signal and the quadrant determination signal output from each of the flip-flop circuits including an exclusive OR circuit, and outputting a correlation detection signal; and averaging the correlation detection signal. Averaging means for outputting the weighted control signal. 4. An intermediate frequency band fractional interval transversal filter that receives an intermediate frequency band interference source signal, an interference source signal quadrature synchronous detection circuit that performs quadrature synchronous detection of the intermediate frequency band interference source signal, A quadrature that samples and identifies the baseband interference source signal output by the interference source signal synchronous detection circuit at the operation cycle of the fractionally spaced transversal filter and outputs it as a quadrant determination signal of the intermediate frequency band interference source signal. A determination signal generation unit, an adder that inputs a desired signal in the intermediate frequency band that is receiving interference from the interference source signal in the intermediate frequency band, and a signal output by the fractionally spaced transversal filter; A desired signal quadrature synchronous detection circuit for performing quadrature synchronous detection on the output signal, and a baseband desired signal output from the desired signal quadrature synchronous detection circuit are identified and re-recognized. And an analog-to-digital conversion circuit that outputs an identification reproduction desired data signal and an error signal, and outputs a weight control signal of the fractionally spaced transversal filter of the intermediate frequency type automatic interference canceller to the quadrant determination signal and the error signal. A control signal generating circuit for generating interference so that a desired signal of the intermediate frequency band is received from an interference source signal of the intermediate frequency band by a signal output by the fractionally spaced transversal filter, Delay time difference compensating means for reducing the delay time difference between the quadrant determination signal and the error signal to zero,
A first flip-flop circuit for receiving the quadrant determination signal and the error signal output from the delay time difference compensating means and obtaining a delay time corresponding to a delay time of each tap of the fractionally spaced transversal filter;
An exclusive-OR circuit or an exclusive-OR NOT circuit for inputting the quadrant determination signal and the error signal output from each of the first flip-flop circuits, and outputting each of the first flip-flop circuits; Correlation detection means for detecting a cross-correlation between the quadrant determination signal and the error signal and outputting a correlation detection signal; a second flip-flop circuit for re-sampling the correlation detection signal at a code transmission cycle of the desired signal; Averaging means for averaging the output of the second flip-flop circuit and outputting the result as the weighted control signal. 5. An interference source signal quadrature synchronous detection circuit for performing quadrature synchronous detection of an intermediate frequency band interference source signal, and a baseband receiving the baseband interference source signal output from the interference source signal quadrature synchronous detection circuit. A band fractional transversal filter and the baseband interference source signal are sampled and identified at the operation cycle of the fractional interval transversal filter and output as a quadrant determination signal of the intermediate frequency band interference source signal. A quadrant determination signal generating means, a desired signal quadrature synchronous detection circuit for performing quadrature synchronous detection of a desired signal in the intermediate frequency band which is receiving interference from the interference source signal in the intermediate frequency band, and the desired signal quadrature synchronous detection circuit output An adder for inputting a desired signal in the baseband band and a signal output from the fractionally spaced transversal filter, and an output from the adder An analog-to-digital conversion circuit that outputs a desired data signal and an error signal by discriminating and reproducing a signal, the weighting control signal of the fractionally-spaced transversal filter of the baseband type automatic interference canceller, and the quadrant determination signal and Based on the error signal, the desired signal in the baseband is changed to an interference signal_
A control signal generation circuit that generates received interference so as to be canceled by a signal output from the fractionally spaced transversal filter, wherein a delay time difference between the input quadrant determination signal and the error signal is calculated. A delay time difference compensating means for setting the delay time difference to zero, and a delay time corresponding to a delay time of each tap of the fractionally spaced transversal filter by inputting the quadrant determination signal and the error signal output by the delay time difference compensating means. A first flip-flop circuit, and an exclusive-OR circuit or an exclusive-OR NOT circuit for inputting the quadrant determination signal and the error signal respectively output by the first flip-flop circuits. And detecting a cross-correlation between the quadrant determination signal and the error signal output from each of the first flip-flop circuits. Correlation detection means for outputting a correlation detection signal, a second flip-flop circuit for re-sampling the correlation detection signal in the code transmission cycle of the desired signal, and averaging the output of the second flip-flop circuit to perform the weighting control. A control signal generation circuit, comprising: an averaging means for outputting the signal as a signal. 6. A desired signal quadrature synchronous detection circuit for performing quadrature synchronous detection of a desired signal in an intermediate frequency band which is receiving interference from an interference source signal in the intermediate frequency band, and a baseband band output by the desired signal quadrature synchronous detection circuit. 1 for discriminating and reproducing the desired signal
An analog-to-digital conversion circuit, an interference source signal quadrature synchronous detection circuit that performs quadrature synchronous detection of the intermediate frequency band interference source signal, and a baseband interference source signal output by the interference source signal quadrature synchronous detection circuit. A second analog-to-digital converter for discriminating and reproducing at an operation speed that is an integral multiple of the operation speed of the first analog-to-digital converter, and an interference source data signal output from the second analog-to-digital converter as an input; An all-digital fractionally-spaced transversal filter, an output data signal of the fractionally-spaced transversal filter, and an output data signal of the first analog-to-digital conversion circuit, and a discrimination / reproduction desired data signal and an error signal And a digital adder that outputs the data as a digital signal. An output data signal of the first analog-to-digital conversion circuit is used as an interference source signal in the intermediate frequency band based on a quadrant determination signal, which is the most significant bit of the interference source data signal, and the error signal. A control signal circuit for canceling the interference received from the data signal output from the fractionally spaced transversal filter, wherein the delay time difference between the input quadrant determination signal and the error signal is reduced to zero. And a delay time difference compensating means for receiving the quadrant determination signal and the error signal output by the delay time difference compensating means and obtaining a delay time corresponding to a delay time of each tap of the fractionally spaced transversal filter. A first flip-flop circuit;
, And an exclusive-OR circuit or an exclusive-OR NOT circuit that inputs the quadrant determination signal and the error signal output from each of the flip-flop circuits. Correlation detection means for detecting a cross-correlation between a signal and the error signal and outputting a correlation detection signal; a second flip-flop circuit for resampling the correlation detection signal at a code transmission cycle of the desired signal; Averaging means for averaging the output of the flip-flop circuit and outputting the result as the weighted control signal.