JP2809168B2 - Timing verification method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a timing verification method, and more particularly, to a timing verification method for verifying a timing constraint of an input signal in a logic circuit.

[0002]

2. Description of the Related Art Conventionally, this kind of timing verification method has
When performing a delay logic simulation of a logic circuit such as a MOS digital circuit by logic simulation means,
It is used to verify timing constraints such as a setup time constraint and a hold time constraint on an input signal of a logic circuit. Therefore, before the delay logic simulation is performed by the logic simulation unit, the timing constraint values of the data signal and the clock signal input to the data input terminal and the clock input terminal of the logic circuit are extracted in advance, and the logic simulation unit delays the logic circuit. When performing logic simulation, a timing constraint violation at the input time of the input data signal and the clock signal is detected with reference to the timing constraint value.
When delay logic simulation is performed by the logic simulation means, generally, there is a case where the input waveform rounding of the input signal to be input to the logic circuit is not considered, and a case where the input waveform rounding of the input signal is considered.

First, a description will be given of a timing verifying method in the case where the input signal rounding is not considered. FIG.
5 is a flowchart showing a timing constraint value extraction processing flow example 1 before delay logic simulation in this timing verification method. Since the input waveform rounding is not taken into account when delay logic simulation is performed on the logic circuit by the logic simulation means, processing including the input waveform rounding assumed on the actual circuit is performed at the time of obtaining the timing constraint value. That is, a circuit simulation is performed by giving an input signal waveform having one assumed rounded input waveform to each of the data terminal and the clock terminal. This is repeated by slightly shifting the time of inputting the data signal and the time of inputting the clock signal.

For example, when the timing constraint value is the setup time constraint value, and when the data signal is input at a time sufficiently later than the clock signal, the output signal does not have the expected value waveform. When the data signal is gradually shifted so as to be input at an earlier time, an output signal having an expected value is obtained at a certain time. The time difference between the input time of the data signal and the input time of the clock signal at this time is the setup time constraint value in the assumed input waveform rounding. In the same manner, a hold time constraint value and the like are also obtained.

After the processing flow of FIG. 6, when delay logic simulation is performed by the logic simulation means, the time when a signal arrives at the data terminal and is inputted and the time when the signal arrives at the clock terminal and is inputted are examined. There is no problem if the time difference is larger than the predetermined timing constraint time, and an alarm is issued if the time difference is smaller than the timing constraint time.

Next, a description will be given of a timing verification method in consideration of the rounding of the input signal. FIG.
5 is a flowchart showing a timing constraint value extraction processing flow example 2 before delay logic simulation in this timing verification method. Although the main processing is to find the timing constraint value assuming a certain rounding of the input waveform and the expected value of the output signal, it is necessary to change the rounding of the input waveform of the input data signal and clock signal by several points and repeat this. is there. That is, the timing constraint value extraction processing in the case where the input waveform rounding of the input signal is not considered is repeated many times while changing the input waveform rounding of the input signal.

[0007] After that, based on the plurality of timing constraint values obtained here, a tallying process for expressing the timing constraint in the form of a function depending on the rounding of the input waveform of the input signal is performed. The form of the function may be a mathematical formula or a tabular form.

After the processing flow of FIG. 7, when delay logic simulation is performed by the logic simulation means, first, the time at which a signal arrives at the data terminal and is input is checked by examining the time at which the signal arrives at the clock terminal and is input.
Calculate the time difference. Thereafter, a timing constraint value corresponding to the current input waveform rounding is obtained from a function for giving a timing constraint value using the input waveform rounding. If the previously obtained time difference is larger than the time of the timing constraint value obtained here, there is no problem, and if it is smaller, an alarm is issued.

[0009]

In the conventional timing verification method, when delay logic simulation is performed by the logic simulation means, if the input waveform rounding is not taken into consideration, the verification is performed on the assumption that the input waveform rounding is constant. . However, in an actual circuit, the rounding of the input waveform differs depending on the case, and thus there is a problem that the accuracy of the timing verification is low.

In addition, when the delay simulation is performed by the logic simulation means, when the input waveform rounding is taken into consideration, the input waveform rounding can be considered, so that the accuracy is good. However, timing constraint values for a plurality of input waveform rounding are obtained in advance. And the execution time of the circuit simulator increases. For example, when a circuit simulation is performed using n types of input waveform roundings of a data signal and a clock signal, a calculation amount of square of n is required when the input waveform roundings of the input signal are not used.

Therefore, the problem to be solved by the present invention is to solve such a situation, and an inexpensive CPU is used.
An object of the present invention is to provide a timing verification method for performing cost verification with high accuracy at high cost.

[0012]

Therefore, the timing verifying method according to the present invention provides a method in which the concept of a setup time or a hold time actually occurs in a logic circuit at an internal node, and the waveform distortion on the data side is also reduced on the clock side. In many cases, the rounding of the waveform is always constant,
The signal delay time of the data signal and the clock signal until the signal input from the external terminal of the logic circuit actually reaches the internal node where the concept of the setup time or the hold time occurs in the logic circuit is stored in each external terminal. It utilizes the characteristic that it depends on the rounding of the input waveform when a signal is input.

That is, the present invention provides a timing verification method for verifying the input timing of a data signal and a clock signal input to a data input terminal and a clock input terminal of a logic circuit when a logic circuit is subjected to delay logic simulation. In the method,
In advance, circuit simulation is performed with the input waveform rounding of the data signal and the clock signal set to zero, the input time of the data signal and the clock signal whose output signal of the logic circuit has an expected value waveform is obtained, and a timing constraint value is extracted. Extracting step, in advance, measuring the data signal delay time from the data input terminal to the internal node of the data holding element in the logic circuit using the input waveform rounding of the data signal as a variable and expressing it as a data delay function,
A functioning step of measuring a clock signal delay time from the clock input terminal to an internal node of the data holding element in the logic circuit by using the input waveform rounding of the clock signal as a variable and expressing the result as a clock delay function; When delay logic simulation is performed on the logic circuit, the input waveform roundings of the data signal and the clock signal are input to variables of the data delay function and the clock delay function, respectively, and the data signal delay time and the clock signal delay time are input. And when the logic simulation means performs delay logic simulation on the logic circuit, based on the timing constraint value, the data signal delay time, and the clock signal delay time. A detection step of detecting a timing constraint violations input time of the preliminary said clock signal comprises a.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 and FIG. 2 are flowcharts showing Embodiment 1 of the timing verification method of the present invention. FIG.
The timing verification process is executed in the order of FIG. FIG. 3 is a conceptual diagram showing an example of a logic circuit to be verified for explaining the timing verification method of the present invention. In the logic circuit 1 to be verified, a circuit portion that generates a timing constraint value is specifically shown, and other circuit portions are omitted. For convenience of explanation, the logic circuit 1 shown in FIG. 3 will be briefly described first. , A data signal and a clock signal are input to a data input terminal 2 and a clock input terminal 3, respectively, arrive at internal nodes 4 to 7 with a delay, and are input to transfer gates 8 and 9 as data holding elements. Internal nodes 5 and 7 are connected to control inputs of transfer gates 8 and 9 and control whether or not signals of internal nodes 4 and 6 connected to data inputs of transfer gates 8 and 9 are transmitted to the next stage. I do. The output of the transfer gate 9 is transmitted to other circuit parts, and arrives at the output terminal 10 of the logic circuit 1 with a delay.

Referring to FIGS. 1, 2 and 3,
The configuration of the timing verification method according to the present embodiment will be described.

The processing steps 21 to 30 in the timing verification method of the present embodiment shown in FIG. 1 are performed in a processing flow called characterization before the logic simulation of the logic circuit 1 by the logic simulation means. is there.

In a processing step 21, a circuit simulation is performed in advance with rounding of the input waveform rounding of the data signal and the clock signal input to the data input terminal 2 and the clock input terminal 3 of the logic circuit 1, and the output signal of the logic circuit 1 is This is an extraction step in which the input times of the data signal and the clock signal having the expected value waveform are obtained, and the timing constraint value is extracted. In the processing steps 22 to 30, the data signal delay time from the data input terminal 2 to the internal nodes 4 and 6 of the data holding elements 8 and 9 in the logic circuit 1 is measured in advance using the rounding of the input waveform of the data signal as a variable. Delay function 1
The function of expressing the clock signal delay time from the clock input terminal 3 to the internal nodes 5 and 7 of the data holding elements 8 and 9 in the logic circuit 1 using the rounding of the input waveform of the clock signal as a variable and expressing it as a delay function 2 Step.

The processing steps 41 to 48 in the timing verification method according to the present embodiment shown in FIG. 2 are performed when the logic simulation means performs the delay logic simulation on the logic circuit 1 by the data input terminal 2 and the clock input terminal 3 of the logic circuit 1. 5 is a processing flow for verifying the input timing of a data signal and a clock signal that have arrived and been input to the device.

The processing steps 41 to 44 are steps for checking each input time and each input waveform rounding of the data signal and the clock signal.
The respective input waveform roundings of the data signal and the clock signal are input to variables of the delay function 1 and the delay function 2, respectively, and the data signal delay time and the clock signal delay time are calculated, respectively. From the delay time and the clock signal delay time, the internal nodes 4 to 9 of the data holding elements 8 and 9 in the logic circuit 1
7 is a calculation step of calculating an arrival time difference between the data signal and the clock signal. The processing step 48 compares the timing constraint value with the arrival time difference,
This is a detection step for detecting a timing constraint violation at the input time of the data signal and the clock signal.

Next, an example in which the timing constraint value of the circuit of FIG. 3 is a constraint value of the setup time will be described in the order of each step of the timing verification method of this embodiment.

First, in step 21 of FIG. 1, the rounding of the input waveform of the data signal input to 2 in FIG.
The input waveform rounding of the clock signal in FIG.
The setup time for the internal nodes 4 and 5 is determined. This method gradually changes the input time of the signal input to the input terminals 2 and 3 in FIG.
To check the input times of the terminals 2 and 3 under the condition that the expected waveform output is obtained, and to measure the time when the signals input to the terminals 2 and 3 reach the internal nodes 4 and 5 Do with. The time difference between the internal nodes 4 and 5 at that time is the setup time constraint value obtained in step 21 of FIG. It is easy to input the data signal to the terminals 2 and 3 in FIG. 3 which is the boundary of the target circuit. However, the measurement can also be performed by directly inputting the data to the internal nodes 4 and 5 in FIG. In addition, although these measurements are performed with a circuit simulator,
A simulator other than a circuit simulator, such as a switch level simulator or a gate level simulator, can be used depending on the circuit scale and the required accuracy.

Next, in step 22 of FIG. 1, a plurality of types of rounded input waveforms to be applied to the terminal 2 of FIG. 3 are obtained. This is done in such a way that the influence of the rounding of the input waveform on the data signal delay time can be understood. Although input waveform rounding can be given manually and empirically, a circuit simulator is automatically executed for a typical small block, and the input waveform rounding and the data signal delay time from input to output of that block are measured. It is also possible to draw a graph of the relationship between the input waveform rounding and the data signal delay time, and to select a plurality of points where the graph is remarkably bent.

In step 23 of FIG. 1, for each of the plurality of rounded input waveforms selected in step 22 of FIG. 1, the data signal delay time from terminal 2 to internal node 4 in FIG. 3 is determined.

After the processing of step 23 is completed for a plurality of rounded input waveforms selected in step 22 of FIG. 1, the results are totaled in step 26 of FIG. That is, from the input waveform rounding, the terminal 2 of FIG.
A delay function 1 for calculating a data signal delay time is generated. Expression (1) indicates that the function has the input waveform rounding as a variable.

[0026]

In Expression (1), InputSlope is the rounding value of the input waveform of the data signal, and Delay is the data signal delay time from terminal 2 to internal node 4 in FIG. Equation (1)
FunctionA may be a mathematical expression or a table.
Expression (2) is an example in which FunctionA of Expression (1) is expressed by a mathematical expression. In the case of equation (2), ParameterA and ParameterB are obtained in the process of step 26 in FIG. Equation (2) is an example of a linear equation, but other methods such as a quadratic equation are also conceivable.

[0028]

FIG. 4 is an explanatory diagram showing an example in which the expression (1) is expressed in a table. In the case of expressing in a table, an interpolation process for obtaining a signal delay time for an arbitrary input round from an element of this table is required.

After step 26 in FIG. 1, the clock signal is subjected to the same processing as the processing from step 21 to step 25 for the data signal. As a result, in step 30, a delay function 2 for obtaining a clock signal delay time from the terminal 3 in FIG. 3 to the internal node 5 is created from the input waveform of the clock terminal, that is, the rounding of the input waveform of the clock signal in step 3 in FIG. At this time, in Expression (1), InputSlope is the value of the rounding of the input waveform of the clock signal, and Delay is from the terminal 3 to the internal node 5 in FIG.
Data signal delay time.

Here, the processing flow on the characterization side before the logic simulation of the logic circuit 1 by the logic simulation means ends, and the logic simulation means of FIG. Move to processing flow.

In step 41 of FIG. 2, the input time of the data signal input to the terminal 2 of FIG. 3 is checked. The rounding of the input waveform of the data signal at that time is checked in step 42 of FIG. Further, in steps 43 and 44 in FIG. 2, the input time of the clock signal input to the terminal 3 in FIG. 3 and the input waveform rounding are checked. Here, the processing order of steps 41 to 44 in FIG. 2 does not matter.

Next, at step 45 in FIG. 2, the time at which the data signal input to the data terminal arrives at the internal node 4 in FIG. 3 is calculated. In this calculation, step 41 in FIG.
Using the arrival time of the data signal checked at step, the input waveform rounding checked at step, and equation (1), the following equation (3) is used.
Is calculated.

[0034]

Here, DataArrivalTime is the time when the data signal arrives at terminal 2 in FIG. 3 and is input. Func
tionA is the delay function obtained in step 25 of FIG. DataTime is the time when the data signal arrives at the internal node 4 in FIG.

Next, at step 46 in FIG. 2, the time at which the clock signal input to the clock terminal arrives at the internal node 4 in FIG. 3 is calculated. In this calculation, the arrival time of the clock signal checked in step 43 of FIG.
The following equation (4) is used to calculate using the input waveform rounding checked in step (1) and equation (1).

[0037]

Here, ClockArrivalTime is the time when the clock signal arrives at terminal 3 in FIG. 3 and is input. Fu
nctionA is the delay function obtained in step 30 of FIG. ClockTime is the time when the signal arrives at the internal node 5 in FIG.

Next, at step 47 in FIG. 2, the difference between the time when the data signal arrives at the internal node 4 in FIG. 3 and the time when the clock signal arrives at the internal node 5 in FIG. 3 is determined. This value is calculated by the following equation (5) when determining the setup time, and is calculated by the following equation (6) when determining the hold time.

[0040]

Note that the setup time and the hold time described above are represented by the term “timing allowance” in FIG.

Finally, at step 48 in FIG. 2, it is determined whether or not the following conditional expressions (7) and (8) are satisfied. If the conditions are not satisfied, a warning is issued.

[0043]

FIG. 5 is a partial flowchart showing Embodiment 2 of the timing verification method of the present invention. 4 shows a processing flow portion on the characterization side before performing a delay logic simulation of the logic circuit 1 by the logic simulation means. The second embodiment is an example in which a part of the processing when performing the delay logic simulation in the first embodiment is performed by the processing flow on the characterization side. The processing added to the processing on the characterization side will be described here.

In the second embodiment, assuming that verification of the setup time is performed, first, a timing constraint value between the internal nodes 5 and 6 in FIG.

Next, in step 52 of FIG. 5, the data signal delay time from the data input terminal to the internal node is obtained for a plurality of rounded input waveforms. That is, terminal 2 in FIG.
From the input signal to the internal node 4 are obtained for a plurality of rounded input waveforms.

Next, in step 53 of FIG. 5, the clock signal delay time from the clock input terminal to the internal node is obtained for a plurality of rounded input waveforms. That is, the clock signal delay time from the terminal 3 to the internal node 7 in FIG.
Find multiple rounded input waveforms.

Next, in step 54 of FIG.
From the values obtained in 1, 52 and 53, a constraint function representing a constraint value of the setup time according to the combination of the input waveform rounding of the data signal and the clock signal is created. This processing is performed using the following equation (9).

[0049]

[0050]

In the equation (9), x is the rounding of the input waveform of the data signal, and y is the rounding of the input waveform of the clock signal. SetupInternal is the setup time constraint value for the internal node, DelayData is the data signal delay time from the data terminal to the internal node, and DelayC
lock is a clock signal delay time from the clock terminal to the internal node. SetupTop is a timing constraint value at the time of input waveform rounding of the setup time of the data terminal and the clock terminal. SetupTop (x, y) may be stored in a table format or as a function. Sought here
The value of SetupTop (x, y) can be used for timing verification by means of a logic simulator in a conventional method.

Next, when delay logic simulation is performed on the logic circuit 1 by the logic simulation means, each input waveform rounding of a data signal and a clock signal is input to a variable of a constraint function, and an input waveform rounding timing constraint value is calculated. The input timing difference between the signal and the clock signal is compared with the timing constraint value at the time of input waveform rounding, and a timing constraint violation at the input time of the data signal and the clock signal is detected.

According to the timing verification methods of the first and second embodiments, the CPU cost of the circuit simulation is significantly reduced at the stage of calculating the timing constraint value.
At the time of timing verification, it is possible to achieve the same high-accuracy verification as that of the conventional method, which considers input waveform rounding.

[0054]

As described above, the timing verification method of the present invention only needs to have one timing constraint value when delay logic simulation is performed on a logic circuit by the logic simulation means. In the conventional timing verification method, it is necessary to have timing constraint values by the number of combinations of the number of types of rounded input waveforms of data signals and the number of types of rounded input waveforms of clock signals. Assuming that the data signal and the clock signal have four types of input waveform rounding, the processing time of this portion is 1/16.

In the timing verification method of the present invention,
It is necessary to determine the data signal delay time from the data terminal to the internal node and the clock signal delay time from the clock terminal to the internal node as a function of each input waveform rounding. The number of executions of the circuit simulation at that time is the same as the number of rounded input waveforms. Assuming that an average of 20 circuit simulations is required to obtain one timing constraint value, the required number of simulations is 20 * 16 = 32 in the conventional timing verification method.
With 0 (the number of times required for one extraction * the number of combinations of input waveform roundings), 320 circuit simulations are required. On the other hand, in the timing verification method of the present invention, the required number of simulations is 20 * 1 + 4 + 4 = 28 (the number required for one extraction * the number of combinations of input waveform roundings + the number of data signal delays + the clock signal delay) ), And only 28 circuit simulations are required, so that the timing constraint value can be extracted with a CPU cost of about 1/11.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a first half flow of a timing verification method according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a second half flow of the timing verification method according to the first embodiment of the present invention.

FIG. 3 is a conceptual diagram showing an example of a logic circuit to be verified for explaining a timing verification method.

FIG. 4 is an explanatory diagram showing an example in which a signal delay time is expressed in a table.

FIG. 5 is a flowchart showing a first half flow of a timing verification method according to a second embodiment of the present invention;

FIG. 6 is a flowchart showing a first half flow of a conventional timing verification method example 1;

FIG. 7 is a flowchart showing a first half flow of a second conventional timing verification method.

[Explanation of symbols]

1 Example of logic circuit to be verified 2 Data input terminal 3 Clock input terminal 4 Data side internal node related to setup time 5 Clock side internal node related to setup time 6 Data side internal node related to hold time 7 Clock side related to hold time Internal node 8 Transfer gate 9 Transfer gate 10 Output terminal 21 to 54 Processing steps

Claims (3)

(57) [Claims] In a timing verification method for verifying the input timing of a data signal and a clock signal input to a data input terminal and a clock input terminal of a logic circuit when performing a delay logic simulation of the logic circuit by the logic simulation means, A circuit simulation in which input waveform rounding of the data signal and the clock signal is set to zero, an input time of the data signal and the clock signal whose output signal of the logic circuit has an expected value waveform is obtained, and a timing constraint value is extracted. Extracting, beforehand, measuring the data signal delay time from the data input terminal to the internal node of the data holding element in the logic circuit using the input waveform rounding of the data signal as a variable, and expressing the measured data signal delay function as a data delay function; The input waveform rounding of A function of measuring a clock signal delay time from the clock input terminal to an internal node of the data holding element in the logic circuit and expressing the result as a clock delay function, using the logic simulation means to perform delay logic simulation of the logic circuit. A calculation step of inputting the input waveform rounding of the data signal and the clock signal to variables of the data delay function and the clock delay function, respectively, and calculating the data signal delay time and the clock signal delay time, respectively; When delay logic simulation is performed on the logic circuit by the logic simulation means, the input timing of the data signal and the clock signal is determined based on the timing constraint value, the data signal delay time, and the clock signal delay time. Timing verification method characterized by comprising the steps of detecting a timing constraint violations, the. 2. The method according to claim 1, wherein the calculating step calculates the data signal at an internal node of the data holding element in the logic circuit from each input time of the data signal and the clock signal, the data signal delay time and the clock signal delay time. Calculating the arrival time difference with the clock signal, wherein the detecting step compares the timing constraint value with the arrival time difference to detect a timing constraint violation at the input time of the data signal and the clock signal. 2. The timing verification method according to claim 1, wherein the method is a step. 3. The method of claim 2, wherein the step of converting the input signal transition timing of the data signal and the clock signal into a timing constraint value based on the delay function and the timing constraint value as a constraint function using the respective input waveform transitions as variables. And calculating the input waveform rounding timing constraint value by inputting each of the input waveform roundings of the data signal and the clock signal to a variable of the constraint function, wherein the detecting step comprises: Is a step of comparing the input time difference between the data signal and the clock signal with the timing constraint value at the time when the input waveform is rounded, and detecting a timing constraint violation at the input time of the data signal and the clock signal. 2. The timing verification method according to 1.