JP2805090B2 - Field interpolation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-field interpolation circuit in a decoder for decoding a television signal transmitted after being subjected to inter-field and inter-frame offset subsampling.

[Related Art] As a method of compressing a transmission signal band of a television signal, a multiplex sub-sample transmission method using offset sub-sampling between fields and between frames is known. As one of the multiple sub-sample transmission systems,
There is a transmission method called MUSE (Multiple Sub-Nyquist Sampling Encoding).

In the decoder of the MUSE transmission method, in the case of a still image, signals of the past three fields that are sequentially transmitted are
Image reproduction is performed by synthesizing the signals transmitted in the current field, that is, by performing frame interpolation processing and field interpolation processing. On the other hand, in the case of moving images, in order to prevent multi-line blur, the current field The image reproduction is performed only by the signal transmitted in step (1), that is, by performing field interpolation processing.

In this case, it is too coarse to switch the operation between the still image and the operation for each screen, so that motion detection is performed for each pixel, and the processing is performed separately in each pixel into a still image area and a moving image area.

 FIG. 6 shows an example of a conventional decoder.

In the figure, an input signal supplied to an input terminal 1 is
A / D converter 2 samples at a frequency of 16.2 MHz and converts it into a digital signal.

The output signal of the A / D converter 2 is supplied to an inter-frame interpolation circuit 3 and inter-frame interpolated. The output signal of the inter-frame interpolation circuit 3 is supplied to a sampling frequency conversion circuit 4 and a sampling frequency of 32.4 MHz to 48.6MHz.

The output signal of the conversion circuit 4 is supplied to a field memory 5 constituting a delay element having a delay time of one field period.

The output signals of the conversion circuit 4 and the field memory 5 are supplied to a two-dimensional low-pass filter 16, and a signal interpolated between fields is output from the two-dimensional low-pass filter 16. That is, the field memory 5, the two-dimensional low-pass filter 16
Therefore, the inter-field interpolation circuit 9 is configured.

FIG. 7 shows a configuration example of the two-dimensional low-pass filter 16. In other words, at the sample point, the signal of the target pixel is multiplied by a coefficient of 3/2, and the signal of four pixels at positions d away from the target pixel in the horizontal direction and h in the vertical direction is multiplied by a coefficient of −1/8. Is added and interpolated. At the non-sample points, signals of two pixels that are d away from the pixel of interest in the horizontal direction and signals of two pixels that are h away from the pixel in the vertical direction are multiplied by a factor of 1/4 and added and interpolated.

The interpolated signal output from the two-dimensional low-pass filter 16 is supplied to the linear mixing circuit 10 as a still image signal. That is, this signal is
Is multiplied by a coefficient 1-k and supplied to the adder 10c.

The output signal of the A / D converter 2 is supplied to a field interpolation circuit 11 for field interpolation, and the output signal of the field interpolation circuit 11 is supplied to a sampling frequency conversion circuit 12 for sampling frequency conversion. From 32.4MHz to 48.
Converted to 6MHz. The output signal of the conversion circuit 12 is supplied to the linear mixing circuit 10 as a moving image signal. In other words, this signal is multiplied by the coefficient k in the coefficient unit 10b, and then added to the adder 10c.
Supplied to

Further, the output signal of the A / D converter 2 is supplied to the motion detection circuit 13, and the motion amount is detected from, for example, an inter-frame difference signal. The motion detection signal Dm is supplied to the linear mixing circuit 10, where the still image signal and the moving image signal are mixed in accordance with the motion detection signal Dm.

In other words, the motion detection signal Dm is
It is supplied as a control signal to 10a and 10b. When the motion detection signal Dm takes a value of, for example, 0 to F (hexadecimal),
The value of the coefficient 1-k of the coefficient unit 10a is set to 1 to 0, and the coefficient unit 10b
Is set to be 0 to 1.

The output signal of this linear mixing circuit 10 and thus the adder 10
The output signal c is converted to an analog signal by the D / A converter 14 and then supplied to the output terminal 15.

[Problems to be Solved by the Invention] By the way, the interpolating circuit 9 in the still image processing system of FIG. 6 multiplies a signal of a neighboring pixel by a predetermined coefficient and adds the signal regardless of the content of the video signal. Then, an interpolation signal is created.

However, a better image can be reproduced by adaptively creating an interpolation signal depending on the content of the video signal.

In view of the above, an object of the present invention is to make it possible to perform appropriate field interpolation in a still image processing system.

Means for Solving the Problems The present invention relates to an inter-field interpolation circuit in a still image processing system of a decoder for decoding a television signal transmitted after being subjected to offset sub-sampling between fields and between frames. Alternatively, an inter-pixel interpolation signal from a neighboring pixel in the horizontal direction and an inter-pixel interpolation signal from a neighboring pixel in the vertical direction due to the field delay signal are mixed according to the amount of motion to obtain an inter-field interpolation signal.

[Operation] In the above-described configuration, the inter-pixel interpolation signal from the neighboring pixels in the horizontal direction and the inter-pixel interpolation from the neighboring pixels in the vertical direction due to the field delay signal according to the edge amount or the motion amount, that is, the content of the video signal. The signals are mixed to form a field interpolation signal, and appropriate field interpolation is performed in the still image processing system.

Embodiment An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.
In this example, an inter-field interpolation signal is adaptively mixed between an inter-pixel interpolation signal from a horizontal neighboring pixel and an inter-pixel interpolation signal from a vertical neighboring pixel due to a field delay signal according to an edge amount detection signal. It is something that you get.

For example, when the horizontal line edge amount is large, the correlation between the pixels in the vertical direction is weak, so that the ratio of the inter-pixel interpolation signal from the neighboring pixels in the horizontal direction is increased. On the other hand, when the vertical line edge amount is large, the correlation between pixels in the horizontal direction is weak.
The ratio of the interpolated signal from the neighboring pixels in the vertical direction due to the field delay signal is increased.

In this example, the output signal of the field memory 5 is
It is supplied to an average value circuit 7 via a line memory 6 which constitutes a delay element having a delay time of one horizontal period (1H) directly. The average value circuit 7 outputs the average value of the scanning line signals of the previous field located before and after the current scanning line signal.

The output signal of the averaging circuit 7, that is, the inter-pixel interpolation signal from the neighboring pixel in the vertical direction due to the field delay signal is supplied to the adder 17 after being multiplied by the coefficient 1-1 by the coefficient unit 16. The output signal of the conversion circuit 4, that is, an inter-pixel interpolation signal from a pixel adjacent in the horizontal direction is supplied to an adder 17 after being multiplied by a coefficient 1 in a coefficient unit 18. And this adder
The output signal of 17 is supplied to the fixed terminal on the a side of the changeover switch 8 as an inter-field interpolation signal.

The conversion circuit 4 is connected to a fixed terminal on the b side of the changeover switch 8.
Are directly supplied. This changeover switch 8
The signal is switched between the a side and the b side at an alternation of 48.6 MHz, and the switch 8 outputs a signal interpolated between fields. The signal interpolated between the fields is used as a still image-based signal by the coefficient unit 10a of the linear mixing circuit 10.
Supplied to

The output signal of the A / D converter 2 is supplied to an edge amount detection circuit 19.
The edge amount is detected from the line difference signal and the pixel difference signal, for example. The edge amount detection signal De is supplied to the coefficient units 16 and 18 as a control signal.

The edge amount detection circuit 19 is constituted by, for example, a horizontal line edge amount detection circuit 191 as shown in FIG. 2A. That is, the output signal of the A / D converter 2 is supplied from a terminal 19a to a horizontal line edge amount detection circuit 191. The horizontal line edge amount detection signal detected from the line difference signal by the horizontal line edge amount detection circuit 191 is supplied to a terminal 19b. Is output.

In addition, the edge amount detection circuit 19 includes, for example, a vertical line edge amount detection circuit 192 as shown in FIG. 2B.
That is, the output signal of the A / D converter 2 is supplied from the terminal 19a to the vertical line edge amount detection circuit 192, and the vertical line edge amount detection signal detected from the pixel difference signal by the vertical line edge amount detection circuit 192 is The signal is output to the terminal 19b via the inverter 193.

The edge amount detection circuit 19 includes, for example, a horizontal line edge amount detection circuit 191 and a vertical line edge amount detection circuit 192 as shown in FIG. 2C. That is, the A / D converter 2
Is supplied from a terminal 19a to a horizontal line edge amount detection circuit 191 and a vertical line edge amount detection circuit 192, and is detected by the horizontal line edge amount detection circuit 191 and the vertical line edge amount detection circuit 192. The detected vertical line edge amount detection signal is supplied to the subtractor 194. And
In the subtracter 194, the vertical line edge amount detection signal is subtracted from the horizontal line edge amount detection signal, and the output signal of the subtractor 194 is output to a terminal 19b.

Here, when each of the horizontal line edge amount detection signal and the vertical line edge amount detection signal takes a value of 0 to F (hexadecimal),
In the example of FIGS. 2A and 2B, corresponding to the edge amount detection signals 0 to F, and in the example of FIG. 2C, corresponding to the edge amount detection signals -F to F, the coefficient 1-1 of the coefficient unit 16 is calculated. The value is set to 1 to 0, and the value of the coefficient 1 of the coefficient unit 18 is set to 0 to 1.

As a result, the inter-field interpolation signal output from the adder 17 increases the ratio of the output signal of the conversion circuit 4, that is, the ratio of the inter-pixel interpolation signal from the neighboring pixel in the horizontal direction to the vertical direction, as the horizontal line edge amount increases. As the line edge amount increases, the ratio of the inter-pixel interpolation signal from the neighboring pixel in the vertical direction due to the field delay signal increases.

 Other configurations are the same as in the example of FIG.

Thus, in this example, the larger the horizontal line edge amount is and the lower the vertical correlation is, the larger the ratio of the inter-pixel interpolation signal from the horizontal neighboring pixels is, and the vertical line edge amount is large and the horizontal correlation is weak. As the ratio of the inter-pixel interpolation signal from the neighboring pixel in the vertical direction increases, the inter-field interpolation signal is formed, so that an appropriate interpolation process suitable for the content of the video signal can be performed.

Next, FIG. 3 shows another embodiment of the present invention. In FIG. 3, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this example, an inter-field interpolation signal is obtained by mixing an inter-pixel interpolation signal from a horizontal neighboring pixel and an inter-pixel interpolation signal from a vertical neighboring pixel due to a field delay signal in accordance with a motion detection signal. Things.

For example, when the motion amount is large, the correlation between the pixels in the field direction is weak, so that the ratio of the inter-pixel interpolation signal from the neighboring pixels in the horizontal direction is increased.

In this example, the motion detection signal from the motion detection circuit 13
Dm is supplied to coefficient units 16 and 18 as a control signal.

Here, when the motion detection signal Dm takes a value of 0 to F (hexadecimal number), the value of the coefficient 1-k of the coefficient unit 16 is set to 1 to 0, and the value of the coefficient k of the coefficient unit 18 is 0 to 1 is set.

As a result, the larger the amount of motion of the interpolated signal output from the adder 17 is, the larger the output signal of the conversion circuit 4, that is, the proportion of the interpolated signal from the neighboring pixels in the horizontal direction is increased.

 Other configurations are the same as those in the example of FIG.

When the changeover switch 8 is connected to the a side to select the interpolated field signal, the output signal of the conversion circuit 4 (interpolated signal between pixels from neighboring pixels in the horizontal direction) SA and the output signal of the average value circuit 7 (field delay) Interpolated signal between pixels in the vertical direction from the neighboring pixels) SB, the output signal SC of the conversion circuit 12,
Relationship between the output signal Y of the linear mixing circuit 10 is represented by Y = k (1-k) SA + (1-k) 2 SB + k SC, On the other hand, the relationship between the time of non-sampling points in the conventional example of FIG. 6 is , Is represented by

FIGS. 4A and 4B show the relationship between the motion detection signal Dm and each coefficient in the conventional example and the present example, respectively.

In the conventional example, as the motion detection signal Dm increases, the coefficient applied to the signals SA and SB decreases proportionally,
It can be seen that the coefficient applied to the signal SC increases proportionally.

On the other hand, in this example, as the motion detection signal Dm increases, it can be seen that some of the coefficients applied to the signal SB are replaced by the coefficients applied to the signal SA.

As described above, in this example, as the amount of motion is larger and the correlation in the field direction is weaker, the ratio of the interpolated signal from the pixel in the horizontal direction to the pixel adjacent to the pixel in the vertical direction due to the field delay signal is increased. Since the ratio of the interpolation signal is reduced to form the inter-field interpolation signal, it is possible to perform an appropriate interpolation process suitable for the content of the video signal. As a result, switching from a still image to a moving image can be performed smoothly.

FIG. 5 shows another embodiment of the present invention. In FIG. 5, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this example, an inter-field interpolation signal is mixed by mixing an inter-pixel interpolation signal from a horizontal neighboring pixel and an inter-pixel interpolation signal from a vertical neighboring pixel by a field delay signal according to the edge amount detection signal and the motion detection signal. Is obtained.

In this example, the motion detection signal from the motion detection circuit 13
Dm and the edge amount detection signal De from the edge amount detection circuit 19
Are supplied to the maximum value circuit 20. And this maximum circuit
The larger signal selected at 20 is supplied to the coefficient units 16 and 18 as a control signal.

Here, the output signal of the maximum value circuit 20 is 0 to F (hexadecimal)
In this case, the value of the coefficient 1-1 of the coefficient unit 16 is set to 1 to 0, and the value of the coefficient 1 of the coefficient unit 18 is set to 0 to 1.

As a result, the interpolated signal output from the adder 17 becomes larger as the motion amount or the edge amount becomes larger.
, Ie, the proportion of the inter-pixel interpolation signal from the horizontal neighboring pixel is increased.

 Other configurations are the same as those in the example of FIG.

Thus, in this example, as the edge amount or the motion amount is larger and the correlation in the vertical direction or the field direction is weaker,
Since the ratio of the inter-pixel interpolation signal from the horizontal neighboring pixels is increased and the ratio of the inter-pixel interpolation signal from the vertical neighboring pixels due to the field delay signal is reduced, the inter-field interpolation signal is formed. As in the embodiment, it is possible to perform an appropriate interpolation process suitable for the content of the video signal.

Note that the maximum value circuit 20 in the example of FIG. 5 may be replaced with an average value circuit.

[Effects of the Invention] As described above, according to the present invention, according to the edge amount or the motion amount, that is, according to the content of the video signal, the vertical interpolation between the inter-pixel interpolation signal from the horizontal neighboring pixel and the field delay signal is performed. Since the interpolated signals between pixels from the direction neighboring pixels are mixed to form interpolated signals between fields, appropriate interpolated fields are performed in the still image processing system, and a more natural image can be reproduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a specific block diagram of an edge amount detection circuit, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. FIG. 5 is a block diagram showing still another embodiment of the present invention, and FIG.
FIG. 1 is a configuration diagram of a conventional example, and FIG. 7 is a configuration diagram of a two-dimensional low-pass filter. DESCRIPTION OF SYMBOLS 1 ... Input terminal 3 ... Frame interpolation circuit 4,12 ... Sampling frequency conversion circuit 5 ... Field memory 6 ... Line memory 7 ... Average value circuit 8 ... Changeover switch 9 ... Field interpolation Circuit 10 Linear mixing circuit 10a, 10b, 16, 18 Coefficient unit 10c, 17 Adder 11 Field interpolation circuit 13 Motion detection circuit 15 Output terminal 19 Edge amount detection Circuit 20: Maximum value circuit

Continuation of the front page (72) Inventor Yuichi Ninomiya 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Research Institute (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 7/015

Claims (1)

(57) [Claims] 1. An inter-field interpolation circuit in a still image processing system of a decoder for decoding a television signal transmitted after being subjected to offset sub-sampling between fields and between frames, wherein a horizontal neighborhood is determined according to an edge amount or a motion amount. An inter-field interpolation circuit characterized by mixing an inter-pixel interpolation signal from a pixel and an inter-pixel interpolation signal from a neighboring pixel in the vertical direction due to a field delay signal to obtain an inter-field interpolation signal.