JP2804325B2 - Multilayer base metal ceramic chip capacitors - Google Patents
Multilayer base metal ceramic chip capacitorsInfo
- Publication number
- JP2804325B2 JP2804325B2 JP32686789A JP32686789A JP2804325B2 JP 2804325 B2 JP2804325 B2 JP 2804325B2 JP 32686789 A JP32686789 A JP 32686789A JP 32686789 A JP32686789 A JP 32686789A JP 2804325 B2 JP2804325 B2 JP 2804325B2
- Authority
- JP
- Japan
- Prior art keywords
- base metal
- ceramic chip
- dielectric layer
- metal ceramic
- nickel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【発明の詳細な説明】 (産業上の利用分野) 本発明は、ニッケルあるいはニッケル合金等の卑金属
を内部電極とした積層型セラミックチップコンデンサに
関する。Description: TECHNICAL FIELD The present invention relates to a multilayer ceramic chip capacitor having a base metal such as nickel or a nickel alloy as an internal electrode.
(従来の技術) 第3図は従来の積層型卑金属セラミックチップコンデ
ンサを示す断面図であり、このコンデンサは、チタン酸
バリウム等の誘電体層1と、ニッケルやその合金等の卑
金属でなる内部電極2とを印刷法等により積層して焼成
し、側面に外部電極3を焼付け等により形成してなるも
のである。(Prior Art) FIG. 3 is a sectional view showing a conventional multilayer base metal ceramic chip capacitor. This capacitor has a dielectric layer 1 such as barium titanate and an internal electrode made of a base metal such as nickel or an alloy thereof. 2 are laminated by a printing method or the like and fired, and the external electrodes 3 are formed on the side surfaces by baking or the like.
(発明が解決すべき課題) 上記従来の積層型卑金属セラミックチップコンデンサ
においては、パラジウム等を内部電極2に用いた積層型
貴金属セラミックチップコンデンサに比べて負荷時の寿
命が短い。(Problems to be Solved by the Invention) In the above-mentioned conventional multilayer base metal ceramic chip capacitor, the life under load is shorter than that of the multilayer noble metal ceramic chip capacitor using palladium or the like for the internal electrode 2.
ところで、この寿命を縮めるチップの破壊の発生箇所
の分布に片寄りがある。この負荷時の破壊箇所の発生の
割合を第3図の右欄にパーセントで表示している。この
破壊箇所の表示から分かるように、チップの積層方向の
中央部に破壊箇所が集中している。つまりチップの積層
方向の中央部ほど寿命が短いことが明らかである。これ
は、内部電極2にニッケルを用いているために、ニッケ
ルが酸化しないように、還元雰囲気で焼成することに起
因すると考えられている。すなわち、チップの焼成後の
アニール処理時の再酸化チップ表面から起こり、チップ
内部の再酸化が内部で不十分であることに起因してい
る。この問題を解決するため、チタン酸バリウム系誘電
体材料の還元防止のために、組成の工夫がいくつかなさ
れているものの、素地の還元を完全に防止することはで
きない。By the way, there is a bias in the distribution of the locations where the chip breakage that shortens the life is generated. The percentage of occurrence of the breakage point under this load is shown in percentage in the right column of FIG. As can be seen from the display of the broken portions, the broken portions are concentrated at the center in the stacking direction of the chips. That is, it is clear that the life is shorter at the center of the chip in the stacking direction. This is considered to be caused by firing in a reducing atmosphere so that nickel is not oxidized because nickel is used for the internal electrode 2. In other words, the reoxidation occurs during the annealing process after the firing of the chip, and the reoxidation inside the chip is insufficient inside. In order to solve this problem, although some compositions have been devised to prevent the reduction of the barium titanate-based dielectric material, the reduction of the substrate cannot be completely prevented.
本発明は、上述のような問題点に鑑み、寿命の長い積
層型卑金属セラミックチップコンデンサを提供すること
を目的とする。The present invention has been made in view of the above-described problems, and has as its object to provide a multilayer base metal ceramic chip capacitor having a long life.
(課題を解決するための手段) この目的を達成するため、本発明は、ニッケルあるい
はニッケル合金等の卑金属を内部電極とした積層型セラ
ミックチップコンデンサにおいて、積層方向の中央部の
誘電体層を他の部分よりも厚く形成したことを特徴とす
る。(Means for Solving the Problems) In order to achieve this object, the present invention relates to a multilayer ceramic chip capacitor having a base metal such as nickel or a nickel alloy as an internal electrode. It is characterized by being formed thicker than the part.
また、積層方向の中央部にポーラスな誘電体層を設け
たことを特徴とする。Further, a porous dielectric layer is provided at the center in the laminating direction.
(作用) 積層方向の中央部の誘電体層を他の部分よりも厚く形
成することにより、中央部の電界強度が他の部分より弱
められる。(Operation) By forming the dielectric layer at the center in the stacking direction thicker than the other parts, the electric field intensity at the center is weaker than the other parts.
また、中央部にポーラスな誘電体を設ければ、アニー
ル処理時に誘電体層の再酸化が促進される。Further, if a porous dielectric is provided at the center, reoxidation of the dielectric layer is promoted during the annealing process.
(実施例) 第1図は本発明による積層型卑金属セラミックチップ
コンデンサの一実施例を示す断面図である。このチップ
コンデンサは、積層方向の中央部の誘電体層1の厚さW1
を、他の部分すなわち、図面上の上下部分の厚さW2〜W4
より大としている。本実施例においては、中央部ほど厚
く、W1>W2>W3>W4としている。(Embodiment) FIG. 1 is a sectional view showing an embodiment of a multilayer base metal ceramic chip capacitor according to the present invention. This chip capacitor has a thickness W 1 of the dielectric layer 1 at the center in the stacking direction.
The thickness of the other parts, ie, the upper and lower parts on the drawing, W 2 to W 4
It's bigger. In the present embodiment, as the central portion thicker, and the W 1> W 2> W 3 > W 4.
第4図は、対向する内部電極間の誘電体厚さを変化さ
せることにより、電界強度を変化させて、印加電圧200
V、200℃で加速試験を行なった場合の寿命を測定した結
果を示すもので、電界強度の増大に伴なって急激に寿命
が短くなることが分かる。FIG. 4 shows that the electric field strength is changed by changing the dielectric thickness between the opposing internal electrodes, and the applied voltage 200
It shows the result of measuring the life when an accelerated test was performed at V and 200 ° C. It can be seen that the life is sharply reduced as the electric field intensity increases.
このように、電界強度と寿命とは大いに関連があるか
ら、第1図に示したように、破壊が起こりやすい中央部
分に誘電体層を大として電界強度を小とすることによ
り、チップコンデンサの寿命を従来の2倍以上に延長す
ることができた。As described above, since the electric field strength is greatly related to the lifetime, as shown in FIG. 1, by increasing the dielectric layer and reducing the electric field strength in the central portion where destruction is likely to occur, the chip capacitor can be reduced. The service life can be extended more than twice as long as the conventional one.
第2図は本発明の他の実施例であり、積層方向の中央
部の誘電体層にポーラスな誘電体層1Aを設けたものであ
る。このようにポーラスな誘電体層1Aは、積層に際して
誘電体ペースト中に炭素粉末あるいは樹脂粉末を分散さ
せたものを積層することにより形成される。FIG. 2 shows another embodiment of the present invention, in which a porous dielectric layer 1A is provided on the dielectric layer at the center in the stacking direction. The porous dielectric layer 1A is formed by laminating carbon paste or resin powder dispersed in a dielectric paste during lamination.
このように、中央部にポーラスな誘電体層1Aを設ける
ことにより、焼成後のアニール処理時に誘電体層1が再
酸化し易くなり、中央部の再酸化が十分となるので、前
記実施例と同様に寿命を2倍以上延長することが可能と
なる。As described above, by providing the porous dielectric layer 1A at the center, the dielectric layer 1 is easily reoxidized at the time of annealing after firing, and the reoxidation at the center is sufficient. Similarly, it is possible to extend the life more than twice.
本発明は、誘電体層1、1Aがチタン酸バリウム系のも
ののみならず、酸化チタン系、ジルコン酸バリウム系、
鉛複合ペロブスカイト系のものである場合にも適用で
き、また、内部電極2として、ニッケルやその合金以外
に、銅やその合金を用いる場合に適用しても延命効果が
得られる。In the present invention, the dielectric layers 1 and 1A are not only made of barium titanate, but also made of titanium oxide, barium zirconate,
The present invention can be applied to the case of a lead composite perovskite-based material, and the life extension effect can be obtained even when the internal electrode 2 is applied to copper or its alloy in addition to nickel or its alloy.
(発明の効果) 請求項1によれば、中央部の誘電体層を厚くしたの
で、破壊を起こしやすい部分の電界強度が弱くなり、コ
ンデンサの寿命の延長が達成される。(Effect of the Invention) According to the first aspect, since the dielectric layer in the central portion is thickened, the electric field intensity in a portion which is likely to be broken is weakened, and the life of the capacitor is extended.
請求項2によれば、中央部にポーラスな誘電体層を設
けたことにより、焼成後のアニール時における誘電体の
再酸化が十分となり、コンデンサの寿命の延長が達成さ
れる。According to the second aspect, since the porous dielectric layer is provided in the central portion, reoxidation of the dielectric during annealing after firing is sufficient, and the life of the capacitor is extended.
第1図は本発明によるの積層型卑金属セラミックチップ
コンデンサの一実施例を示す断面図、第2図は本発明の
他の実施例を示す断面図、第3図は従来の積層型卑金属
セラミックチップコンデンサを破壊箇所分布と共に示す
断面図、第4図はコンデンサの加速試験における電界強
度と寿命との関係図である。 1:誘電体層、1A:ポーラスな誘電体層、2:内部電極、3:
外部電極FIG. 1 is a sectional view showing one embodiment of a multilayer base metal ceramic chip capacitor according to the present invention, FIG. 2 is a sectional view showing another embodiment of the present invention, and FIG. 3 is a conventional multilayer base metal ceramic chip. FIG. 4 is a cross-sectional view showing the capacitor together with the distribution of breakage points, and FIG. 4 is a diagram showing the relationship between the electric field strength and the life in an acceleration test of the capacitor. 1: dielectric layer, 1A: porous dielectric layer, 2: internal electrode, 3:
External electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 池田 雅昭 東京都中央区日本橋1丁目13番1号 テ ィーディーケイ株式会社内 (72)発明者 中野 幸恵 東京都中央区日本橋1丁目13番1号 テ ィーディーケイ株式会社内 (72)発明者 阿部 道郎 東京都中央区日本橋1丁目13番1号 テ ィーディーケイ株式会社内 (58)調査した分野(Int.Cl.6,DB名) H01G 4/12 H01G 4/30────────────────────────────────────────────────── ─── Continuing on the front page (72) Masaaki Ikeda 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDK Corporation (72) Inventor Yukie Nakano 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDK Inside (72) Inventor Michio Abe 1-13-1 Nihonbashi, Chuo-ku, Tokyo Inside TDK Corporation (58) Fields surveyed (Int.Cl. 6 , DB name) H01G 4/12 H01G 4/30
Claims (2)
を内部電極とした積層型セラミックチップコンデンサに
おいて、積層方向の中央部の誘電体層を他の部分よりも
厚く形成したことを特徴とする積層型卑金属セラミック
チップコンデンサ。1. A multilayer ceramic chip capacitor in which a base metal such as nickel or a nickel alloy is used as an internal electrode, wherein a dielectric layer at a central portion in a laminating direction is formed thicker than other portions. Ceramic chip capacitors.
を内部電極とした積層型セラミックチップコンデンサに
おいて、積層方向の中央部にポーラスな誘電体層を設け
たことを特徴とする積層型卑金属セラミックチップコン
デンサ。2. A multi-layer ceramic chip capacitor comprising a base metal such as nickel or a nickel alloy as an internal electrode, wherein a porous dielectric layer is provided at a central portion in a laminating direction.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32686789A JP2804325B2 (en) | 1989-12-15 | 1989-12-15 | Multilayer base metal ceramic chip capacitors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32686789A JP2804325B2 (en) | 1989-12-15 | 1989-12-15 | Multilayer base metal ceramic chip capacitors |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03187209A JPH03187209A (en) | 1991-08-15 |
JP2804325B2 true JP2804325B2 (en) | 1998-09-24 |
Family
ID=18192616
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32686789A Expired - Lifetime JP2804325B2 (en) | 1989-12-15 | 1989-12-15 | Multilayer base metal ceramic chip capacitors |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2804325B2 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06224071A (en) * | 1993-01-28 | 1994-08-12 | Murata Mfg Co Ltd | Multilayer capacitor |
JP4622421B2 (en) * | 2004-09-27 | 2011-02-02 | パナソニック株式会社 | Multilayer capacitor |
JP4654854B2 (en) * | 2005-09-13 | 2011-03-23 | パナソニック株式会社 | Multilayer capacitors and molded capacitors |
JP5303884B2 (en) * | 2007-09-14 | 2013-10-02 | 株式会社村田製作所 | Multilayer ceramic capacitor |
KR101882998B1 (en) * | 2011-11-25 | 2018-07-30 | 삼성전기주식회사 | Laminated ceramic electronic parts |
KR20150005577A (en) * | 2012-06-19 | 2015-01-14 | 다이요 유덴 가부시키가이샤 | Laminated ceramic capacitor |
KR101514509B1 (en) * | 2013-02-26 | 2015-04-22 | 삼성전기주식회사 | Multilayer ceramic device |
JP5652487B2 (en) * | 2013-03-04 | 2015-01-14 | 株式会社村田製作所 | Multilayer ceramic capacitor |
-
1989
- 1989-12-15 JP JP32686789A patent/JP2804325B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH03187209A (en) | 1991-08-15 |
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