JP2796661B2 - Manufacturing method of bonded semiconductor substrate - Google Patents
Manufacturing method of bonded semiconductor substrateInfo
- Publication number
- JP2796661B2 JP2796661B2 JP6033794A JP6033794A JP2796661B2 JP 2796661 B2 JP2796661 B2 JP 2796661B2 JP 6033794 A JP6033794 A JP 6033794A JP 6033794 A JP6033794 A JP 6033794A JP 2796661 B2 JP2796661 B2 JP 2796661B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- manufacturing
- semiconductor substrate
- bonded
- speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Recrystallisation Techniques (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は例えば２枚のシリコンウ
ェーハを直接張り合わせて一体化する張り合わせ半導体
基板の製造方法、特にその張り合わせ速度に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bonded semiconductor substrate in which, for example, two silicon wafers are directly bonded and integrated, and more particularly to a bonding speed.
【０００２】[0002]
【従来の技術】従来より、シリコンウェーハ同士を直接
張り合わせて接合する技術は、例えば特開昭６１−１４
５８３９号公報、特開昭６２−７１２１５号公報等に列
挙されている。このウェーハの張り合わせ接合技術は、
基本的には以下の工程により構成されている。室温で
２枚のウェーハを張り合わせる。９００℃以上の温度
領域でこれをアニールし、結合強度を高める。、の
各工程では張り合わせ界面は一様に結合され、ボイド等
の非結合部分がないこと、また、後工程で剥離しない程
度に結合強度が高いことが要求される。2. Description of the Related Art Conventionally, a technique for directly bonding and bonding silicon wafers to each other is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-14 / 1986.
5839, JP-A-62-71215 and the like. This wafer bonding technology is
Basically, it is constituted by the following steps. Attach two wafers at room temperature. This is annealed in a temperature range of 900 ° C. or more to increase the bonding strength. In each of the steps (1) and (2), it is required that the bonding interface is uniformly bonded, that there is no non-bonding portion such as a void, and that the bonding strength is high enough not to peel off in a subsequent step.
【０００３】そして、張り合わせ技術としては、従来よ
り、例えば特開平２−４６７２２号公報、特開平２−２
４８０３２号公報、特開平３−１９６６１０号公報、特
開平４−４７４０号公報等に示す装置および方法が提案
されているが、いずれの技術についても未だ実用上の難
点が存在している。すなわち、いずれの張り合わせ方法
を採用したとしても、張り合わせ作業において、張り合
わせ不良のウェーハがかなりの率で発生することとな
る。[0003] Conventional laminating techniques are disclosed in, for example, Japanese Patent Application Laid-Open Nos. 2-46722 and 2-2.
Japanese Patent Application Laid-Open No. 48032, Japanese Patent Application Laid-Open No. HEI 3-196610, and Japanese Patent Application Laid-Open No. H4-4740 have proposed devices and methods. However, there are still practical difficulties in any of these technologies. That is, no matter which bonding method is adopted, a defective bonding wafer is generated at a considerable rate in the bonding operation.
【０００４】[0004]
【発明が解決しようとする課題】このように従来の張り
合わせ技術にあってはの熱処理後における接合強度は
必ずしも充分なものではなく、その後のデバイス工程で
剥がれ等の不具合を発生させていたという課題が生じて
いた。As described above, the bonding strength after the heat treatment in the conventional laminating technique is not always sufficient, and a problem such as peeling occurs in a subsequent device process. Had occurred.
【０００５】そこで、本発明は、剥がれ等の不具合の発
生をなくした張り合わせ半導体基板の製造方法を提供す
ることを、その目的としている。SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a bonded semiconductor substrate which eliminates problems such as peeling.
【０００６】[0006]
【課題を解決するための手段】請求項１に記載した発明
は、２枚の半導体基板の主面同士を重ね合わせて１枚の
張り合わせ半導体基板を製造する張り合わせ半導体基板
の製造方法において、上記２枚の半導体基板の各主面の
一点から接合を開始し、それらの全面を接合する場合、
その接合開始から接合終了までの間の接合速度をそれら
の主面の状態に対応して設定した張り合わせ半導体基板
の製造方法である。According to a first aspect of the present invention, there is provided a bonded semiconductor substrate manufacturing method for manufacturing a single bonded semiconductor substrate by superposing main surfaces of two semiconductor substrates. When joining from one point of each main surface of the semiconductor substrates and joining them all,
This is a method for manufacturing a bonded semiconductor substrate in which the bonding speed from the start of bonding to the end of bonding is set in accordance with the state of the main surfaces.
【０００７】また、請求項２に記載した発明は、上記２
枚の半導体基板の各主面を熱酸化による二酸化シリコン
（ＳｉＯ2）膜で形成し、その接合速度を１ｃｍ／秒よ
りも大きくする製法である。また、請求項３に記載の発
明は、各主面をシリコンで、すなわち自然酸化膜で形成
し、接合速度は１ｃｍ／秒よりも大きくしてある。ま
た、請求項４に記載の発明も、主面を熱酸化膜と自然酸
化膜とでそれぞれ構成した場合、その接合速度は１ｃｍ
／秒より大きくする。また、請求項５に記載の発明は、
上記２枚の半導体基板の主面のいずれか一方をポリシリ
コン膜で形成し、その接合速度を０．８ｃｍ／秒よりも
大きくした方法である。さらに、請求項６の発明は、上
記２枚の半導体基板の各主面をポリシリコン膜で形成
し、その接合速度を０．６ｃｍ／秒よりも大きくした製
造方法である。なお、いずれの場合にあっても各主面は
鏡面研磨されている。[0007] The invention described in claim 2 is the above-mentioned 2
This is a manufacturing method in which each main surface of a single semiconductor substrate is formed of a silicon dioxide (SiO2) film by thermal oxidation, and the bonding speed is higher than 1 cm / sec. Further, in the invention according to claim 3, each main surface is formed of silicon, that is, a natural oxide film, and the bonding speed is set to be higher than 1 cm / sec. Also, in the invention according to claim 4, when the main surface is formed of a thermal oxide film and a natural oxide film, the bonding speed is 1 cm.
/ Sec. The invention described in claim 5 is
In this method, one of the main surfaces of the two semiconductor substrates is formed of a polysilicon film, and the bonding speed is set to be higher than 0.8 cm / sec. Further, the invention according to claim 6 is a manufacturing method in which each of the principal surfaces of the two semiconductor substrates is formed of a polysilicon film, and the bonding speed thereof is higher than 0.6 cm / sec. In any case, each main surface is mirror-polished.
【０００８】[0008]
【作用】本発明方法によれば、熱処理後にあっても接合
強度が高く、剥がれが生じることがない張り合わせ半導
体基板を得ることができる。この場合、張り合わせに使
用する半導体基板としては、シリコンウェーハの主面を
鏡面研磨したもの同士であってもよく、または、一方の
重ね合わせ面に酸化膜（ＳｉＯ2膜）、ＣＶＤ膜（ポリ
シリコン膜）、エピタキシャル膜（ポリシリコン膜）等
を被着したものであってもよい。いずれの主面状態にあ
っても設定した接合速度よりも大きい速度で張り合わせ
を行うことにより、その接合強度を高めることができ
る。また、これらの接合速度は１０ｃｍ／秒程度まで高
めてもよい。According to the method of the present invention, it is possible to obtain a bonded semiconductor substrate having high bonding strength even after the heat treatment and without peeling. In this case, the semiconductor substrates used for bonding may be mirror-polished main surfaces of silicon wafers, or an oxide film (SiO2 film), a CVD film (polysilicon film) ), An epitaxial film (polysilicon film) or the like may be applied. In any of the main surface states, the bonding strength can be increased by performing the bonding at a speed higher than the set bonding speed. Further, the bonding speed of these may be increased to about 10 cm / sec.
【０００９】[0009]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。図１は一実施例に係る張り合わせ半導体基板を製
造する際に用いる半導体基板の張り合わせ欠陥検査装置
を示すブロック図である。図２は一実施例に係る張り合
わせ半導体基板の熱処理後のボイド発生率と、その接合
速度との関係を説明するためのグラフである。（Ａ）は
シリコンウェーハ（自然酸化膜）同士の関係、シリコン
ウェーハ（鏡面に自然酸化膜あり）と熱酸化膜付のシリ
コンウェーハとの関係、熱酸化膜付のシリコンウェーハ
同士の関係を示している。また、（Ｂ）はポリシリコン
膜付のウェーハとシリコンウェーハ（鏡面に自然酸化膜
あり）との関係について示している。さらに、（Ｃ）は
ポリシリコン膜付のシリコンウェーハ同士の関係につい
て示している。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a semiconductor substrate bonding defect inspection apparatus used when manufacturing a bonded semiconductor substrate according to one embodiment. FIG. 2 is a graph for explaining the relationship between the void generation rate after heat treatment of the bonded semiconductor substrate according to one embodiment and the bonding speed thereof. (A) shows the relationship between silicon wafers (natural oxide films), the relationship between silicon wafers (natural oxide films on mirror surfaces) and silicon wafers with thermal oxide films, and the relationship between silicon wafers with thermal oxide films. I have. (B) shows the relationship between a wafer with a polysilicon film and a silicon wafer (a natural oxide film is provided on the mirror surface). (C) shows the relationship between silicon wafers with a polysilicon film.
【００１０】図１において示すように、この装置では、
接着治具１１の直上に所定間隔だけ離れてＩＲカメラ１
２がセットしてある。また、接着治具１１に対して斜め
上方から所定角度をなして赤外線ＩＲを照射可能に赤外
光源（半導体レーザ等）１３が配設されている。照射さ
れた赤外線ＩＲは、接着治具１１で反射し、ＩＲカメラ
１２に入射する構成である。ＩＲカメラ１２の出力信号
は画像処理装置１４に送られ、さらに、モニタ１５に表
示される。すなわち、接着治具１１での２枚のウェーハ
Ａ，Ｂの張り合わせ時の重ね合わせ面（主面）の状態
は、光源１３から照射した赤外線ＩＲがこのウェーハ
Ａ，Ｂを透過し、または反射した赤外線ＩＲをＩＲカメ
ラ１２で撮影することにより記録される。この重ね合わ
せ面の状態は、所定の信号処理（光電変換、フィルタリ
ング等）により画像としてモニタ１５に表示される。し
たがって、作業者はモニタ１５を目視してボイド等を容
易に発見、認識することができる。As shown in FIG. 1, in this device,
The IR camera 1 is separated from the bonding jig 11 by a predetermined distance just above the bonding jig 11.
2 is set. Further, an infrared light source (semiconductor laser or the like) 13 is provided so as to be able to irradiate infrared IR at a predetermined angle to the bonding jig 11 from obliquely above. The irradiated infrared IR is reflected by the bonding jig 11 and enters the IR camera 12. The output signal of the IR camera 12 is sent to the image processing device 14 and further displayed on the monitor 15. That is, the state of the superposed surface (main surface) when the two wafers A and B are bonded by the bonding jig 11 is such that the infrared rays IR emitted from the light source 13 have transmitted or reflected the wafers A and B. It is recorded by photographing the infrared IR with the IR camera 12. The state of the superimposed surface is displayed on the monitor 15 as an image by predetermined signal processing (photoelectric conversion, filtering, and the like). Therefore, the worker can easily find and recognize a void or the like by viewing the monitor 15.
【００１１】本実施例における張り合わせウェーハの製
造工程を説明する。まず、主面を鏡面研磨した基盤ウェ
ーハ（シリコンウェーハ）および同じく主面を鏡面研磨
したこれに張り合わせられる活性層ウェーハ（シリコン
ウェーハ）を準備する。これらのウェーハを上記接着治
具１１を使用して一定の条件（接合速度）の下に張り合
わせる。例えば一方のウェーハを略半球状に湾曲させて
その湾曲面（主面）の中心から周縁に向かって所定の速
度で張り合わせる。このとき、赤外線を照射し重ね合わ
せ面の状態を撮影している。図２の（Ａ）、（Ｂ）、
（Ｃ）はこの結果を示している。The manufacturing process of the bonded wafer in this embodiment will be described. First, a base wafer (silicon wafer) whose main surface is mirror-polished and an active layer wafer (silicon wafer) whose main surface is mirror-polished and bonded thereto are prepared. These wafers are bonded under a certain condition (bonding speed) using the bonding jig 11. For example, one of the wafers is bent into a substantially hemispherical shape and bonded at a predetermined speed from the center of the curved surface (main surface) to the periphery. At this time, the state of the superimposed surface is photographed by irradiating infrared rays. 2 (A), (B),
(C) shows this result.
【００１２】そして、張り合わせ不良が生じた場合は、
モニタ１５で確認した後、再生用のウェーハとして処理
する。張り合わせが正常である場合は、張り合わせ後の
ウェーハには例えば１１００℃，２時間，酸素雰囲気で
の熱処理（アニール）が施され、さらに、超音波探傷法
によるボイド等の欠陥検査を行う。良品は次工程で研磨
等が施され、デバイス工程に供される。[0012] Then, when the bonding failure occurs,
After confirmation on the monitor 15, the wafer is processed as a wafer for reproduction. If the bonding is normal, the bonded wafers are subjected to a heat treatment (annealing) in an oxygen atmosphere at, for example, 1100 ° C. for 2 hours, and further inspected for defects such as voids by ultrasonic testing. The non-defective product is polished or the like in the next step and is provided to a device step.
【００１３】[0013]
【発明の効果】本発明によれば、張り合わせでの良品率
を高めることができる。すなわち、ボイドの発生がない
張り合わせウェーハを得ることができる。According to the present invention, the rate of non-defective products in bonding can be increased. That is, a bonded wafer free of voids can be obtained.
【図１】本発明の一実施例に係る製法に使用する張り合
わせ欠陥検査装置を示すブロック図である。FIG. 1 is a block diagram showing a bonding defect inspection apparatus used in a manufacturing method according to an embodiment of the present invention.
【図２】本発明の一実施例に係る張り合わせ半導体基板
の製造方法を説明するためのグラフである。FIG. 2 is a graph illustrating a method for manufacturing a bonded semiconductor substrate according to one embodiment of the present invention.
フロントページの続き (72)発明者 菅原 誠 東京都千代田区岩本町３丁目８番16号 三菱マテリアルシリコン株式会社内 (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/02 H01L 21/20Continuation of the front page (72) Inventor Makoto Sugawara 3-8-16 Iwamotocho, Chiyoda-ku, Tokyo Mitsubishi Materials Silicon Corporation (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/02 H01L 21/20
Claims (6)
せて１枚の張り合わせ半導体基板を製造する張り合わせ
半導体基板の製造方法において、 上記２枚の半導体基板の各主面の一点から接合を開始
し、それらの全面を接合する場合、その接合開始から接
合終了までの間の接合速度をそれらの主面の状態に対応
して設定したことを特徴とする張り合わせ半導体基板の
製造方法。2. A method for manufacturing a bonded semiconductor substrate, comprising manufacturing a single bonded semiconductor substrate by superposing main surfaces of two semiconductor substrates on each other, wherein the bonding is performed from one point of each main surface of the two semiconductor substrates. A method for manufacturing a bonded semiconductor substrate, wherein, when starting and bonding the entire surfaces thereof, the bonding speed from the start of the bonding to the end of the bonding is set in accordance with the state of the main surfaces thereof.
による二酸化シリコン膜で形成し、その接合速度を１ｃ
ｍ／秒よりも大きくした請求項１に記載の張り合わせ半
導体基板の製造方法。2. The method according to claim 1, wherein each of the principal surfaces of the two semiconductor substrates is formed of a silicon dioxide film formed by thermal oxidation, and the bonding speed is 1c.
The method for manufacturing a bonded semiconductor substrate according to claim 1, wherein the speed is higher than m / sec.
ンで形成し、その接合速度を１ｃｍ／秒よりも大きくし
た請求項１に記載の張り合わせ半導体基板の製造方法。3. The method for manufacturing a bonded semiconductor substrate according to claim 1, wherein each of the main surfaces of the two semiconductor substrates is formed of silicon, and a bonding speed thereof is higher than 1 cm / sec.
による二酸化シリコン膜とシリコンとでそれぞれ形成
し、その接合速度を１ｃｍ／秒よりも大きくした請求項
１に記載の張り合わせ半導体基板の製造方法。4. The bonded semiconductor substrate according to claim 1, wherein the main surfaces of the two semiconductor substrates are formed of a silicon dioxide film and silicon by thermal oxidation, respectively, and the bonding speed is higher than 1 cm / sec. Manufacturing method.
一方をポリシリコン膜で形成し、その接合速度を０．８
ｃｍ／秒よりも大きくした請求項１に記載の張り合わせ
半導体基板の製造方法。5. A method according to claim 1, wherein one of the main surfaces of the two semiconductor substrates is formed of a polysilicon film, and the bonding speed is 0.8
The method for manufacturing a bonded semiconductor substrate according to claim 1, wherein the speed is higher than cm / sec.
リコン膜で形成し、その接合速度を０．６ｃｍ／秒より
も大きくした請求項１に記載の張り合わせ半導体基板の
製造方法。6. The method for manufacturing a bonded semiconductor substrate according to claim 1, wherein each of the principal surfaces of the two semiconductor substrates is formed of a polysilicon film, and a bonding speed thereof is higher than 0.6 cm / sec.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6033794A JP2796661B2 (en) | 1994-03-04 | 1994-03-04 | Manufacturing method of bonded semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6033794A JP2796661B2 (en) | 1994-03-04 | 1994-03-04 | Manufacturing method of bonded semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07245250A JPH07245250A (en) | 1995-09-19 |
| JP2796661B2 true JP2796661B2 (en) | 1998-09-10 |
Family
ID=13139259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6033794A Expired - Lifetime JP2796661B2 (en) | 1994-03-04 | 1994-03-04 | Manufacturing method of bonded semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2796661B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7601271B2 (en) * | 2005-11-28 | 2009-10-13 | S.O.I.Tec Silicon On Insulator Technologies | Process and equipment for bonding by molecular adhesion |
-
1994
- 1994-03-04 JP JP6033794A patent/JP2796661B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07245250A (en) | 1995-09-19 |
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