JP2796375B2 - CMOS charge pump circuit - Google Patents

Description

The present invention relates to a CMO provided on an output side of a PLL phase comparator.
The present invention relates to an S charge pump circuit for improving the characteristics of a PLL.

[Prior Art] FIG. 5 shows a conventional C provided at the output side of a PLL phase comparator.
FIG. 2 is a connection diagram of a MOS charge pump circuit. As shown in FIG. 2, a P-channel, a first transistor 2, and an N-channel first transistor 3 are connected in series between a positive power supply 1 and a ground. And a source and a gate of a P-channel third transistor 4 for a constant current source are connected to the positive power supply 1 and a gate of the first transistor 2, respectively.
2, 4 constitute a current mirror, the source of an N-channel fourth transistor 5 for a constant current source is grounded, and the gate is connected to the gate of the second transistor 3; A current mirror is configured by 3,5.

At this time, the channel area represented by the channel length and the channel width of the third transistor 4 is set to α times the first transistor 2, and the channel area represented by the channel length and the channel width of the fourth transistor 5 is: The current I flows between the source and the drain of the first and second transistors 2 and 3, respectively, so that the current of αI flows between the source and the drain of the third transistor 4. Flows, the source of the fourth transistor 5,
A current of βI flows between the drains.

Further, as shown in FIG. 5, a switching P-channel fifth transistor 7 is provided between the drain of the third transistor 4 and the output terminal 6, and between the drain of the fourth transistor 5 and the output terminal 6. N for switching
A sixth transistor 8 for the channel is provided.

Then, a gate control pulse from a control unit (not shown in FIG. 5) is input to the gates of the switching fifth and sixth transistors 7 and 8, and both transistors 7,
8 turns on alternately.

By the way, the third of such a CMOS charge pump circuit is
The formation pattern of the sixth to fourth transistors 4, 5, 7, and 8 is as shown in FIG. 6, where S, G, and D represent the source, gate, and drain, respectively. Each of the transistors 4, 5, 7, 8 has an individual diffusion pattern area P _a , P _b , P _c ,
_Pd is formed respectively.

 Next, the operation will be described.

First and third transistors 2, 4 forming a current mirror
Since the channel area ratio is 1: α, when a constant current I flows through the first transistor 2, a current α · I that is α times as large flows through the third transistor 4, and therefore the first transistor 2
Functions as a constant current source for supplying a current α times the constant current I to the third transistor 4, and the third transistor 4 has +
Is a constant current source.

On the other hand, the second and fourth
Since the ratio of the channel area of the transistors 3 and 5 is 1: β, when the constant current I flows through the second transistor 3, the current β · I flows through the fourth transistor 5 by β times that of the second transistor 3. 3 functions as a constant current supply source for flowing a current β times the constant current I to the fourth transistor 5,
The transistor 5 serves as a negative constant current source.

When the fifth and sixth transistors 7 and 8 are alternately turned on, the output of the + constant current source by the third transistor 4 and the − constant current source by the fourth transistor 5 are switched, and the output terminal is switched. 6 outputs a square-wave current as shown in FIG.

[Problems to be solved by the invention]

In the conventional CMOS charge pump circuit, the third and fifth transistors 4, 7 are formed in separate diffusion pattern regions P _a , P _c ,
The fourth and sixth transistors 5, 8 also have separate diffusion pattern regions P _b ,
Because of the formation of _Pd , the third and fifth parts as shown in FIG.
Due to the effect of charging and discharging of the stray capacitance C _a between the transistors 4 and 7 and the stray capacitance C _b between the fourth and sixth transistors 5 and 8, the output current waveform from the output terminal 6 becomes a square wave as shown in FIG. In fact, a waveform including a spike-like noise component due to stray capacitances C _a and C _b as shown in FIG. 7 is obtained, and the distortion of the output current waveform causes deterioration of PLL characteristics. There was a problem of inviting.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is an object of the present invention to reduce a stray capacitance between a current power supply transistor and a switching transistor, thereby preventing output waveform distortion. With the goal.

[Means for solving the problem]

A CMOS charge pump circuit according to the present invention includes a P-channel first transistor and an N-channel second transistor connected in series between a power supply and a ground, and a current connected to the power supply with the source connected to the power supply. A P-channel third transistor for a current source constituting a mirror, a N-channel fourth transistor for a current source having a grounded source and a current mirror together with the second transistor, and a drain and an output of the third transistor; A switching P-channel fifth transistor provided between the output terminal and a switching P-channel fifth transistor provided between the output terminal and a switching P-channel fifth transistor. Third
And a fifth transistor are formed in one same diffusion pattern region, the fourth and sixth transistors are formed in another same diffusion pattern region, and respective drains of the fifth and sixth transistors are connected to each other. It is characterized in that a surge breakdown withstanding means is included between the drain and the output terminal.

[Action]

In the present invention, the third and fifth transistors are formed in one and the same diffusion pattern region, and the fourth and sixth transistors are formed in the other and the same diffusion pattern region.
The stray capacitance between the fifth transistor and the stray capacitance between the fourth and sixth transistors are reduced as compared with the conventional case, distortion of the output waveform is prevented, and the surge breakdown immunity securing means secures the surge immunity.

〔Example〕

1 and 2 are a pattern diagram and a connection diagram of a part of the CMOS charge pump circuit of the present invention.

Referring to FIG. 2, the basic circuit configuration is substantially the same as FIG. 5, and the difference from FIG.
An on-state transmission gate 11 composed of an N-channel seventh transistor 9 connected to the N-channel and a P-channel eighth transistor 10 whose gate is grounded is connected to a connection point A between the fifth and sixth transistors 7 and 8. This is provided between the output terminal 6.

FIG. 1 shows the third to sixth transistors 4 and 4 of FIG.
FIG. 5 is a diagram showing formation patterns of 5, 7, and 8, where S, G, and D in FIG. 1 represent a source, a gate, and a drain, respectively, and the third and fifth transistors 4, 7 are arranged in one diffusion pattern region _Pe . Formed,
The drain of the third transistor 4 and the source of the fifth transistor 7 are common, and the fourth and sixth transistors 5,
8 is formed on the other of the diffusion pattern region P _f, a drain and a source of the sixth transistor 8 of the fourth transistor 5 is in common.

As described above, the third and fifth transistors 4, 7 are formed in one diffusion pattern region P _e , and the fourth and sixth transistors 5, 8 are formed in the other diffusion pattern region P _f , whereby the third transistor is formed. ,
The stray capacitance between the fifth transistors 4 and 7 and the stray capacitance between the fourth and sixth transistors 5 and 8 can be significantly reduced as compared with the related art.

Accordingly, the waveform of the current output from the output terminal 6 when the fifth and sixth transistors 7, 8 are turned on alternately is:
As shown in FIG. 3, the waveform becomes a square wave, and the characteristic deterioration of the PLL as in the related art can be prevented.

The third, the fifth transistor 4 and 7 formed on one of the diffusion pattern region P _e, 4, to form a sixth transistor 5,8 other diffusion pattern region P _f, first for switching
5, Although the area of the drain regions of the sixth transistors 7 and 8 becomes smaller and weaker against surges, the provision of the transmission gate 11 in the ON state ensures the surge breakdown withstand capability.

As another embodiment, a transmission gate
Instead of 11, as shown in FIG. 4, two protection diodes 12, 13 are provided in series between the positive power supply 1 and the ground, and the connection point A of the fifth and sixth transistors 7, 8 and the output terminal 6 may be connected to the connection point of both diodes 12 and 13 to ensure the surge breakdown withstand capability.

Further, in the above embodiment, the case where the present invention is used for the PLL phase comparator has been described, but it goes without saying that the mode of use is not limited to this.

〔The invention's effect〕

As described above, according to the present invention, the stray capacitance between the third transistor for current source and the fifth transistor for switching, and the stray capacitance between the fourth transistor for current source and the sixth transistor for switching. Since the capacity can be reduced compared to the conventional type, it is possible to prevent the distortion of the output waveform as in the past and to secure the surge breakdown withstand capability.
When used on the output side of the phase comparator, it is possible to prevent the characteristics of the PLL from deteriorating.

[Brief description of the drawings]

FIG. 1 is a diagram showing a formation pattern of an embodiment of a CMOS charge pump circuit of the present invention, FIG. 2 is a connection diagram of FIG. 1, FIG. 3 is an output waveform diagram of FIG. 2, and FIG. FIG. 5 is a connection diagram of a conventional CMOS charge pump circuit, FIG. 6 is a partial formation pattern diagram of FIG. 5, and FIG. 7 is an output waveform of FIG. FIG. In the figure, 1 is a positive power supply, 2 to 5 are first to fourth transistors, 6 is an output terminal, 7, 8 are fifth and sixth transistors, 11
Are transmission gates, 12, 13 are diodes, Pe,
Pf is a diffusion pattern area. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A P-channel first transistor and an N-channel second transistor connected in series between a power supply and a ground, and a current having a source connected to the power supply and forming a current mirror with the first transistor. A third P-channel transistor for a source, a fourth N-channel transistor for a current source having a source grounded and forming a current mirror with the second transistor, and a third transistor, a drain, and an output terminal. A switching P-channel fifth transistor provided; and a switching N-channel sixth transistor provided between the drain of the fourth transistor and the output terminal; A transistor is formed in one and the same diffusion pattern region, and the fourth and sixth transistors are A CMOS charge pump formed in one diffusion pattern region, wherein drains of the fifth and sixth transistors are connected to each other, and a surge breakdown withstanding means is included between the drain and the output terminal. circuit.