JP2796354B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a technology for facilitating device testing and debugging relating to individual signals exchanged between semiconductor integrated circuits and functional modules included in the semiconductor integrated circuits. The present invention relates to a technique which is effective when applied to a microcomputer constituted by a specific method.

2. Description of the Related Art A semiconductor integrated circuit such as a so-called single-chip microcomputer in which a plurality of functional modules are formed on a single semiconductor substrate, as shown in FIG.
A U (Central Processing Unit) 1 and other peripheral circuits such as a DMA (Direct Memory Access) controller 2, a timer 3, and a serial interface controller (not shown) are mounted. These functional modules include a common internal bus 4 including an address bus, a data bus, and a control bus.
And a common signal such as a data signal, an address signal, and a control signal can be exchanged between the functional modules, especially with the CPU.

By the way, the signals necessary for the operation of such functional modules are not only the above-mentioned common signals, but also individual signals which must be individually exchanged between predetermined functional modules. For example, the DMA controller 2 requests the CPU 1 to release the common internal bus 4, a DMA request signal DREQ, a DMA acknowledge signal DACK as a response signal to the DMA request, and the DMA controller 2 and the timer 3 interrupt the CPU 1. Interrupt signals INT ₂ and INT ₃ for instructing. Since such an individual signal is a signal exclusively required for handshake control between predetermined functional modules, the common internal bus 4 can be interfaced with the outside via an input / output circuit 5, It was said that the individual signals were not released to the outside at all, and that there was no need to open them to the outside.

[Problems to be Solved by the Invention] In a device test of a semiconductor integrated circuit such as a single-chip microcomputer for exchanging individual signals between built-in function modules, common signals are externally transmitted via a common internal bus 4. By supplying a desired function module, the function module can be tested while controlling it independently.However, since no individual signal such as an interrupt signal is open to the outside, it can be supplied directly from the outside. Also, the output state cannot be directly confirmed externally. For this reason, in the test on the individual signal, it is necessary to operate both of the plurality of functional modules that exchange predetermined individual signals with each other to perform the test.

The present inventors have examined this point. As a result, in order to confirm the output state of a predetermined individual signal and the operating state of a functional module receiving the signal, the function module that outputs the individual signal requires It is necessary to carry out an operation necessary to obtain the output state of the above, and to operate the function module which receives the output state so that the state of the individual signal can be reflected. As a result, it has been clarified that the test time for the individual signal becomes longer and that it takes time to create the test pattern.

Note that in one semiconductor integrated circuit device having a plurality of built-in logic function blocks, individual signals between the logic function blocks are sent out of the semiconductor integrated circuit device, and the signals are sent from outside the semiconductor integrated circuit device. The supply of the input test signal to a predetermined logic function block is described in U.S. Application Serial No. 119,605, Japanese Patent Application Laid-Open No. 62-38949 on February 2, 1987 and Japanese Patent Application Laid-open No. It was released with Kaikai 61-272668.

However, each of the semiconductor integrated circuits described in the above-mentioned application has a dedicated signal line added for testing. Further, there is no mention of handling of individual signals when one of the logic function blocks is a CPU.

According to the study of the present inventor, in a semiconductor integrated circuit circuit such as an application-specific hook microcomputer corresponding to an individual specification request as a desired peripheral function module can be arbitrarily combined centering on a core CPU, It has been found that the test pattern for an individual signal has to be recreated every time the combination of the peripheral function modules adopted according to the required specifications is different, and it has been found that the above problem becomes more remarkable.

Further, when a signal line for testing is added, the degree of integration of peripheral function modules that can be built in one semiconductor integrated circuit may be reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit circuit which can facilitate a device test for an individual signal exchanged between built-in function modules and increase the product density.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, output gate means for selectively outputting, to the common internal bus, individual signals exchanged between a plurality of functional modules coupled to the common internal bus interfaced with the outside is provided, and the individual signals are supplied to the common bus. Input gate means is provided for selectively supplying signals to predetermined functional modules instead of individual signals.

Also, in place of the output gate means and the input gate means, individual signals exchanged between a plurality of function modules coupled to a common internal bus interfaced with the outside are transferred from a predetermined function module to another predetermined function module. A supply state, a state in which the individual signal output from the predetermined function module is output to the common internal bus, and a signal supplied from the outside to the common internal bus instead of the individual signal, and supply to the other predetermined function module In this case, a signal separating means that can be adopted as an alternative is provided.

[Operation] According to the above-described means, in a device test or the like relating to an individual signal, an individual signal output from a predetermined functional module can be supplied to the common internal bus via the output gate means, thereby enabling the individual signal to be output. The output state can be directly confirmed externally via a common internal bus interfaced with the outside. This makes it possible to easily check the output state of a desired individual signal without making the function module that receives the individual signal reflect the state of the individual signal.

Further, in a device test or the like relating to an individual signal, a signal directly supplied from the outside to the common internal bus can be supplied from the input gate means to a desired functional module instead of the individual signal, so that the individual signal is originally output. The operation state of the function module based on the desired individual signal can be easily confirmed without causing the function module to perform an operation required to obtain a required output state of the individual signal.

The signal separating means selectively unifies the flow of the individual signal output from the predetermined function module to one of a common internal bus or another function module receiving the individual signal, and outputs the signal from the predetermined function module. A conflict between the individual signal to be supplied and a signal supplied from the outside in place of the individual signal is avoided. As a result, when an individual signal that is a trigger for starting a predetermined operation, such as an operation request signal or a response signal to the signal, is used to directly check the output state of the individual signal externally, a functional module that originally receives it Automatically inhibits activation of its own operation by this individual signal, and also checks the operation state of a functional module receiving a predetermined individual signal based on an externally supplied individual signal substitution signal. The first object of the present invention is to suppress the activation of the operation by the inherent individual signal, thereby facilitating the independent test of the desired function module on the individual signal.

Embodiment FIG. 1 shows a single-chip microcomputer according to an embodiment of the present invention. The single-chip microcomputer shown in FIG. 1 is formed on a semiconductor substrate such as a single-crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The single-chip microcomputer 10 shown in FIG. 1 is not particularly limited, but includes a CPU 11, a DMA controller 12, a timer 13, and other peripheral circuits such as a serial interface controller (not shown) in a so-called application-specific manner. ing. These function modules include a common internal bus 14 including an address bus AB, a data bus DB, and a control bus CB.
, So that common signals such as data, address signals, and control signals can be exchanged with each other. The common internal bus 14 can be interfaced with the outside via an input / output circuit 15.

The individual signals exchanged between the functional modules typically shown in FIG. 1 include interrupt signals INT ₁₂ and INT ₁₃
Is shown as an example. These interrupt signals INT ₁₂ and IN
T ₁₃ is can be supplied to the CPU11 via the respective signal separation circuit 16 and 17.

Signal separating circuit 16, and a state for supplying the interrupt signal INT ₁₂ output from the DMA controller 12 to CPU 11, and outputs a predetermined signal line of the data bus DB included the interrupt signal INT ₁₂ internal bus 14 for example to a common The state and the signal supplied from the outside to the common internal bus 14 are determined by the CPU 11 interrupt signal INT.
_The state to be supplied to the ₁₂ input terminals is alternatively selected. Similarly, the signal separation circuit 17, and a state for supplying the interrupt signal INT ₁₃ to CPU11 outputted from the timer 13, a predetermined signal on the data bus DB included the interrupt signal INT ₁₃ internal bus 11 for example to a common Line and the signal supplied from the outside to the common internal bus 14
And a state for supplying the interrupt signal INT ₁₃ input terminal of the one in which alternatively selects.

FIG. 2 shows a detailed example of the signal separation circuit 16.

The signal separation circuit 16, an output gate 20 for providing an interrupt signal INT ₁₂ output from the DMA controller 12 to a predetermined signal line of the data bus DB, in such devices a test in order to replace the interrupt signal INT ₁₂ a flip-flop 21 for latching the test signal tEST ₁₂ supplied from the outside via a predetermined signal line of the data bus DB, the interrupt signal INT ₁₂ outputted from the test signal tEST ₁₂ or DMA controller 12 is outputted from the flip-flop 21 And a flip-flop for latching a switching control signal CONT ₁₂ supplied from the outside via a predetermined signal line of the data bus DB to perform output selection control of the multiplexer 22. And a read gate for reading the latch data of the flip-flop 23 to the data bus DB so that the data can be checked externally. Doo 24
It is constituted by and.

The output gate 20 and the flip-flop 21, and the flip-flop 23 and the read gate 24 can be regarded as registers Ra and Rb, respectively.

An address is assigned to each of the registers Ra and Rb, and more specifically, an output gate 2 constituting the registers Ra and Rb.
0, the flip-flop 21, the flip-flop 23, and the read gate 24 are each assigned a broad address. The address assigned in this way is CP
Although it can be mapped to the same address space as registers included in various functional modules such as U11,
In this embodiment, the mode signal MO supplied from the outside is
All or some bits of the DE are used together and mapped to a unique address space. Note that when a test operation is instructed to the single-chip microcomputer 10 by the mode signal MODE, the input / output circuit 15 can supply an address signal and a control signal to the common internal bus 14 from outside.

Registers Ra and Rb mapped in this way
The selection control is not particularly limited, but is performed by the selection circuit 25 configuring one functional module. This selection circuit 25
It receives an address signal externally supplied via an address bus AB, a read / write signal externally supplied via a control bus CB, and a mode signal MODE.

When a predetermined test operation is instructed by a mode signal MODE supplied from the outside, the selection circuit 25 to which these signals are supplied is supplied with an address signal corresponding to the register Ra from the outside, and a read / write signal. When a read operation is instructed, the selection control signal φar is asserted to control the output gate 20 to be in an on state,
Enabling reading the interrupt signal INT ₁₂ to the outside. At this time, when the write operation is instructed by the read / write signal, the selection control signal φaw given to the control terminal of the flip-flop 21 is asserted to set the test signal TEST.
₁₂ is latched by the flip-flop 21.

On the other hand, when a predetermined test operation is instructed by the externally supplied mode signal MODE, when an address signal corresponding to the register Rb is externally supplied, and a write operation is instructed by the read / write signal, asserts the selection control signal φbw applied to the control terminal of the flip-flop 23 a switching control signal CONT ₁₂ is latched to the flip-flop 23. This switching control signal
When CONT ₁₂ is at a high level, the multiplexer 22 selects the output of the interrupt signal INT _12, and when it is at a low level, selects the output of the latch signal of the flip-flop 21.
At this time, when the read operation is instructed by the read / write signal, the selection control signal φbr is asserted to latch the latch signal of the flip-flop 23 to the read gate.
The output is controlled to the data bus DB via 24.

The flip-flop 23 is initialized in response to the initialization reset of the single-chip microcomputer 10 by taking a low-level state of the latch signal with a reset signal RESET.

 Next, the operation of the above embodiment will be described with reference to FIG.

First, in the case of confirming the output status of the interrupt signal INT ₁₂ in a device testing, controls the output gate 20 to the ON state. By the interrupt signal INT ₁₂ output from the DMA controller 12 which may be supplied to the data bus DB via an output gate 20 in the ON state in this state, the output state of the interrupt signal INT ₁₂ common being externally interfaced It is possible to directly confirm it to the outside via the internal bus 14. This makes it possible to check the output state of the interrupt signal INT ₁₂ CPU 11 to the interrupt signal INT ₁₂ briefly interrupt signal INT ₁₂ without the operation as a state and a possible reflection of undergoing.

In this case, by previously so as not to output the interrupt signal INT ₁₂ is a switching control signal CONT ₁₂ of the high level to the flip-flop 23 latches the multiplexer 22, to confirm directly the interrupt signal INT ₁₂ externally, CPU 11 There can be suppressed to start it specific operation by the interrupt signal INT ₁₂ automatically, DMA that is the origin when state confirmation of the interrupt signal INT ₁₂
The single test of the controller 12 can be facilitated.

Then, in the device testing, in the case of check of the operation of the CPU when an interrupt is indicated by the interrupt signal INT ₁₂ is a high-level switching control signal CONT ₁₂ of the latching multiplexer 22 to the flip-flop 23 flip The output of the latch data of the loop 21 is selected. In this state, when the flip-flop 21 latches the test signal TEST ₁₂ directly supplied from the outside to the data bus DB, the latch data is replaced by the CPU 11 instead of the interrupt signal INT _12.
By being supplied to, the interrupt signal INT to the DNA controller 12 for outputting originally the interrupt signal INT ₁₂
It is possible to easily check the operation state of the CPU when a predetermined interrupt is instructed, without performing the operation required to obtain the _twelve required output states.

At this time, the high-level switching control signal CONT ₁₂ is latched in the flip-flop 23, and the interrupt signal INT ₁₂ is not output from the multiplexer 22, so that an interrupt is actually instructed from the DNA controller 12 during a test. be interrupt signal INT ₁₂ is output for, by the test signal tEST ₁₂ supplied from the outside instead of the interrupt signal INT ₁₂ has a conflict with the interrupt signal INT ₁₂ is avoided, the interruption is instructed in confirming the basis the operating state of the CPU11 to the test signal tEST ₁₂ supplied from the outside when, C due to inherent interrupt signal INT ₁₂
The activation of the interrupt sequence of the PU 11 is suppressed, thereby facilitating the independent test of the interrupt sequence of the CPU 11 from the outside.

Note that a test using the other signal separation circuit 17 can be similarly performed.

FIG. 3 shows the signal separation circuit 16 and the selection circuit shown in FIG.
An example of 25 detailed logic diagrams is shown. In this embodiment, three interrupt signals INT ₁₂₁ , IN
_T122 and INT ₁₂₃ are sent out. Multiplexer 22, an AND gate AG1 receiving the interrupt signal INT _121, INT ₁₂₂ and INT _123, receives the test signal supplied from the data bus DB side through the register Ra ₂ AND gates AG2 and the AND gate AG1 or AG2 It is composed of an OR gate OR for transmitting an output signal to the CPU 11. Above AND Gate AG
The control signal to ₁ is supplied from the data bus DB via the register Rb1. The control signal to the AND gate AG2 is
Supplied from the data bus DB via the register Rb _2. The registers Ra ₁ , INT ₁₂₂ and INT ₁₂₃ , which can be sent directly to the data BUS DB via the interrupt signal INT ₁₂₁ , provide control signals φa to the registers Ra ₁ , Rb ₁ , Rb ₂ and Ra ₂ .
₁ r, φb ₂ w, φa ₂ w, φb ₂ r, and φb ₂ w are formed by the selection circuit 25. The selection circuit 25 includes an AND gate AG3 receiving an address signal on the address bus AB and a NOR gate NOR.
And an AND gate AG4 for receiving a control signal on the control bus CB and an inverted signal of the mode signal MODE. The reason that address signals are used is that
This is because each register is mapped on the address area of this microcomputer. For example, register Ra ₁ is at address 0, register Rb ₁ is at address 1, register Ra ₂
Is mapped to address ₂ and register Rb2 is mapped to address 3.

When the mode signal MODE is 0, the test mode is set, and when the mode signal MODE is 1, the normal operation mode is set. The MODE signal is in the normal operation mode, the flip-flop 234 in register Rb ₂ is to be reset, the AND gate AG2 is controlled to a non-transmission state. Thus, the output of the register Ra ₂ consisting of flip-flops 211, 212, 213 is not transmitted to the CPU. By register Rb ₁ consisting of flip-flops 231, 232, and 233 is to control the AND gate AG1 is in normal operation mode, the interrupt signal INT
It is used to permit or prohibit the transmission of ₁₂₁ , INT ₁₂₂ , and INT _{123 to} the CPU side. Output gate 201, 202 and 203 in the register Ra ₁ is also used in the normal operation mode in order to monitor the state of the interrupt signal. In test mode,
By 1 is written in the flip-flop 234 of the register Rb _2, since the AND gate AG2 is controlled to the transmission state, the output of the register Ra ₂ consisting of flip-flops 211, 212 and 213 is to be inputted to the CPU. At this time, unless writing is performed in the register Rb ₁ composed of the flip-flops 231, 232, 233, the flip-flops 231, 232,
233 is reset and the interrupt signals INT ₁₂₁ , INT ₁₂₂ , I
Not transmitted to NT ₁₂₃ CPU. In the normal operation mode, the register write signal .phi.a ₂ w for Ra _2, the write signal .phi.b ₂ w with respect to the read signal .phi.a ₂ r register Rb ₂ to the register Rb is not a work level, is the address of the register Ra _2, Rb ₂ 2 The addresses 3 and 3 can be used for other purposes in the normal operation mode. According to this embodiment, the interrupt signals INT ₁₂₁ and INT
It is possible to test the operation of the CPU 11 for the combination of the states ₁₂₂ and INT ₁₂₃ . Since the CPU 11 can be tested without operating the DMA controller 12, the test pattern can be shared with the CPU 11 even if the DMA controller 12 is replaced with another functional module.

According to the above embodiment, the following effects can be obtained.

(1) It is not necessary to provide an additional test bus other than the common internal bus 14 in a device test on an individual signal between functional modules. Therefore, the improvement of the degree of integration is not hindered.

(2) In a device test related to an individual signal such as an interrupt signal, an individual signal output from a predetermined functional module can be supplied to the common internal bus 14 via the output gate 20. It can be directly confirmed externally through the common internal bus 14 that is interfaced with the outside, so that it is possible to easily perform the operation without allowing the function module receiving the individual signal to reflect the state of the individual signal. The output state of the desired individual signal can be confirmed.

(3) In a device test related to an individual signal, a test signal TEST ₁₂ directly supplied from the outside to the common internal bus 14
Signals such as flip-flop 21 and multiplexer
The signal can be supplied to the desired functional module via the subroutine 22 in place of the individual signal, thereby preventing the functional module that originally outputs the individual signal from performing an operation necessary to obtain a desired output state of the individual signal. It is possible to easily confirm the operation state of the function module based on the desired individual signal.

(4) The signal separating circuits 16 and 17 selectively unify the flow of the individual signal output from the predetermined functional module to one of the common internal bus or another functional module receiving the individual signal, and Between the individual signal output from the functional module and the signal supplied from the outside in place of the individual signal. This makes it possible to directly check the output state of an individual signal, such as a DMA request signal, an interrupt signal, and a response signal thereto, which is used as a trigger for activating a predetermined operation, when directly checking the output state of the individual signal. Automatically inhibits a functional module that originally receives the individual signal from activating its own operation by this individual signal, and changes the operating state of the functional module that receives a predetermined individual signal to an externally supplied individual signal substitute signal. When confirming based on the individual signal, it is possible to suppress the activation of the operation by the original individual signal, thereby facilitating the independent test of the desired function module on the individual signal.

(5) From the above-described effects (2) to (4), it is possible to shorten the device test time for the individual signal and further facilitate the creation of the test pattern. In particular, for an application-specific hook-type semiconductor integrated circuit, the trouble of recreating a test pattern of an individual signal every time a combination of peripheral function modules employed differs according to the required specifications is largely eliminated.

(6) The signal supplied from the outside in place of the individual signal is temporarily latched by a data latch circuit such as the flip-flop 21 and supplied to a predetermined functional module, so that the individual signal is required in terms of timing. The substitute signal having a required length or waveform can be supplied to a predetermined functional module. Therefore, it is possible to obtain versatility that a signal separating circuit having the same hardware configuration can be commonly used for various individual signals having different waveforms.

(7) When assigning addresses to the registers Ra and Rb included in the signal separation circuits 16 and 17, these are mapped to a unique address space together with an externally supplied mode signal MODE, so that the device test is exclusively performed. The registers used in the first embodiment need not occupy a part of the address space used in the common operation other than the device test, and the use efficiency of the address space can be improved.

(8) A function to release individual signals to the outside if necessary
Utilization for system debugging or software debugging of the target machine can contribute to facilitation of debugging processing.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

For example, in the above embodiment, the output gate 20, the flip-flop 21, the multiplexer 22, the flip-flop 23, and the read gate 24 constitute a signal separation circuit.
The read gate 24 may be omitted, or the test signal may be directly supplied to the multiplexer 22 without passing through the flip-flop 21. The output selection control for the multiplexer 22 may be directly performed by the mode signal.

The addresses assigned to the registers Ra and Rb included in the signal separation circuit are not limited to mapping in the address space using the mode signal together, but may be mapped in the same address space as the registers included in various functional modules. .

The signal separation circuit may be included in a functional module or the like that generates an individual signal. At this time, the various registers included in the signal separation circuit can be arranged in the same address space as the registers included in the function module, and a circuit for selecting these registers in response thereto is also included in the function module. And other circuits for selecting other registers.

In the above embodiment, the signal separation circuit is employed as a means for facilitating the device test relating to the individual signal. However, similarly to the output gate of the above embodiment, an output gate means capable of selectively outputting the individual signal to the common internal bus is provided. With only this, it is possible to easily confirm the output state of a desired individual signal without operating the function module that receives the individual signal so that the state of the individual signal can be reflected.
Further, in this case, it is possible to add input gate means capable of selectively supplying a predetermined functional module instead of an individual signal instead of a signal supplied to the common internal bus. This input gate means may be a simple switch,
A data latch circuit such as the flip-flop 21 of the above embodiment may be used.

The individual signal is not limited to an interrupt signal, a DMA request signal, and a DMA response signal, but broadly means various handshake signals such as a coprocessor enable signal and a memory acknowledge signal.

In the above description, the case where the invention made by the present inventor is mainly applied to an application-specific single-chip microcomputer, which is a field of application as the background, has been described. However, the present invention is not limited to this. It can be widely applied to microcomputer LSI and other semiconductor integrated circuits.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a single-chip microcomputer according to one embodiment of the present invention, FIG. 2 is a block diagram showing a detailed example of a signal separation circuit, and FIG. 3 is another detailed example of a signal separation circuit. FIG. 4 is a schematic block diagram of a conventional single-chip microcomputer. 10: Single-chip microcomputer 11: CPU, 12: DMA controller 13: Timer, 14: Common internal bus 15: I / O circuit 16, 17: Signal separation circuit INT ₁₂ , INT _13: Interrupt Signal 20: Output gate 21: Flip-flop 22: Multiplexer 23: Flip-flop 24: Read gate Ra, Rb: Register TEST _12: Test signal CONT _12: Switching control signal MODE: Mode signal 25 …… Selection circuit φar, φaw, φbr, φbw …… Selection control signal

──────────────────────────────────────────────────続 き Continuing from the front page (72) Haruo Keida, Inventor 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Musashi Plant, Hitachi, Ltd. (72) Kunihiko Nakata 5-chome, Josuihoncho, Kodaira-shi, Tokyo No. 20 in the Musashi Factory of Hitachi, Ltd. (72) Gen Yasuda, Inventor 1-5-1, Marunouchi, Chiyoda-ku, Tokyo In the Semiconductor Division of Hitachi, Ltd. (56) References JP-A-61-272668 (JP, A) JP-A-62-191953 (JP, A) JP-A-63-293646 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 11/22-11/ ²⁶ G06F 15 / 78 510

Claims (5)

(57) [Claims] An input or output means coupled to a CPU, a direct memory access controller, a timer, and an external terminal; and an input or output means coupled to the CPU;
U, a common internal bus to which a direct memory access controller and a timer are coupled; a first signal supplied to the CPU, the direct memory access controller and the common internal bus and output from the direct memory access controller or the common internal bus A first signal separating means for selectively supplying the second signal to the CPU, a third signal output from the timer or the third signal coupled to the CPU, the timer, and a common internal bus; A semiconductor integrated circuit device having a second signal separating means for selectively supplying a fourth signal on a bus to the CPU. 2. The system according to claim 1, wherein said first signal and said third signal are interrupt signals, and said second signal and said fourth signal are test signals. Semiconductor integrated circuit measures as described. 3. The input section is coupled to the common internal bus, and the output section is coupled to the first and second signal separation circuits, and the first and second signal separation circuits are provided on the common bus based on signals. 3. The semiconductor integrated circuit device according to claim 2, further comprising a control circuit for forming a control signal for said signal separation circuit. 4. The common internal bus includes a data bus, an address bus, and a control bus, and supplies the first signal from the first signal separation circuit to the data bus.
Or a first transmission means for supplying the second signal from the data bus to the first signal separation circuit;
And a second transmission unit for supplying the third signal from the signal separation circuit to the data bus or supplying the fourth signal from the data bus to the second signal separation circuit. 4. The semiconductor integrated circuit device according to claim 3, wherein: 5. The control signal is formed based on a mode switching signal supplied through at least one external terminal and the input means, an address signal on the address bus, and a control signal on the control bus. 5. The semiconductor integrated circuit device according to claim 4, wherein: