JP2794599B2 - Signal playback device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio reproducing apparatus capable of switching between a plurality of modes.

[Summary of the Invention]

The present invention relates to a signal reproducing apparatus for reproducing a signal including a mode from a recording medium, demodulating the signal, extracting mode information, and controlling a mute means based on the mode information transmitted via a state setting bus. By muting the output signal for a certain period of time, the occurrence of abnormal sound can be prevented at low cost.

[Conventional technology]

In a digital audio tape recorder system (DAT system) using a rotary head, six modes are standardized, and the sampling frequency, the number of quantization bits, the number of channels, and the like are set differently in each mode.

First, FIG. 4 shows the DAT tape format, in which a magnetic tape 100 has a track 2A recorded by a first rotating magnetic head and a track 2B recorded by a second rotating magnetic head. Magnetic tape 100
Are formed alternately obliquely with respect to the longitudinal direction. The heads are provided on the rotating drum at approximately 180 ° intervals with different azimuth angles. Then, while each head makes one rotation, tracks 2A and 2B are formed respectively.

One track 2A (2B) is called one segment, and
It is divided into six data blocks. The 34 blocks at both ends are auxiliary data areas, and the 128 blocks at the center are PCM areas. The auxiliary data area is further divided into a number of sections. In each section, a predetermined signal such as a subcode or a PLL run-in signal is recorded, and a non-signal section is also provided. In one of the sections, an AFT signal serving as a pilot signal for tracking servo is recorded.

In the PCM area, a signal obtained by converting the audio signal into PCM is recorded together with other predetermined data. This PCM area is composed of 128 data blocks, and the configuration of one block is as shown in FIG.

In FIG. 5, one block is composed of 288 bits, and an 8-bit (1 symbol) block synchronization signal is added to the head, followed by an 8-bit PCM-ID. After this PCM-ID, a block address is added. The two symbols of this PCM-ID and block address (W
₁ , W ₂ ), a simple parity error detection encoding process is performed, and an 8-bit parity is added next to the block address.

Then, as shown in FIG. 6, during the PCM-ID,
ID consisting of 2 bits each with the frame address
Mode information of -1 to ID-8 is included in the block of the even block address. Of these mode information, for example,
ID-2 is the sampling frequency (48kHz, 44.1kHz, 32kHz), ID-
3 is the number of channels (2ch, 4ch), and ID-4 is the quantization rule (1
6bit, 12bit), ID-5 is track pitch (13.591μm, 2
0.41 μm).

In the conventional DAT system, the mode information recorded in the data block of the tape is extracted at the time of reproduction, and the mode information is set using a recognition unit such as a microcomputer. That is, conventionally, a signal related to mode information is output from a signal processing IC that performs demodulation to a microcomputer that controls the system and is taken in, and the mode is switched by control from the microcomputer. .

[Problems to be solved by the invention]

In such a system in which the mode setting is switched using a microcomputer or the like, when the mode is switched during playback, the muting is performed under the control of the microcomputer.

For example, when playing back a tape whose sampling frequency is changed in the middle, or when writing (overwriting) in the middle of the tape, the clock signal used for the sampling frequency is transiently disturbed, or the servo is disabled. Noise or abnormal sound is generated due to disturbance. In particular, servo disturbances are remarkable in a no-tracking servo system that controls a tape speed using a frame address (for example, see Japanese Patent Application Laid-Open No. 63-184948). Therefore, the microcomputer operates the mute circuit based on the mode information extracted from the data, and mutes the output.

However, when the size of the device is reduced, the device is dedicated to reproduction, and cost reduction is considered, it becomes difficult to control muting using a microcomputer or the like, and it is necessary to take measures to prevent abnormal noise.

In view of the technical problems, an object of the present invention is to provide a signal reproducing apparatus that prevents occurrence of abnormal sound and realizes a low-cost system.

[Means for solving the problem]

In order to achieve the above object, a signal reproducing apparatus of the present invention is a signal reproducing apparatus that reproduces a recording medium on which a signal having mode information, an address, and main data is recorded.
Demodulating means for demodulating a reproduction signal reproduced from the recording medium, mode information extracting means for extracting the mode information from the signal demodulated by the demodulating means, and the mode extracted by the mode information extracting means A state setting bus for transmitting information, an address bus for transmitting the address among the signals demodulated by the demodulation means, and a data bus for transmitting the main data among the signals demodulated by the demodulation means; Mute means for muting the main data transmitted via the main bus when the mode information transmitted via the state setting bus changes.

[Action]

The signal recorded on the recording medium is modulated, demodulated by the demodulation means, and separated from data, addresses, and the like by the mode information extraction means, so that mode information is extracted. Then, this mode information is transmitted on a state setting bus provided in the same IC chip, and based on a signal from the state setting bus, the mute means is operated, particularly when the mode information changes. The occurrence of abnormal sound is prevented beforehand.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

This example is an example of a digital audio signal reproducing apparatus for reproducing a digital signal from a rotary head.

1. Structure of reproduction-only IC (Fig. 1)
FIG. 2 is a block diagram showing an internal circuit configuration of FIG. A demodulation unit 2 to which a PF signal is supplied is provided in a chip of the reproduction-only IC 1.
, A data bus 4, an address bus 5, and a state setting bus 3; an error correction circuit 7;
, An internal reference address generation circuit 9, a de-interleave circuit 10, a 12-16 conversion / interpolation circuit 11, a mute circuit 6, and a gate circuit 12 for operating each circuit. A RAM control circuit 14 for controlling a clock generation circuit 13 and a RAM (random access memory) 15 is also provided.

In the read-only IC 1, the signals from the two magnetic heads of the rotary head are amplified and switched by an amplifier and combined to form one RF signal, which is combined with a waveform equalizer and a limiter. Supplied via The RF signal from this magnetic tape is output to the PLL circuit 23 of the read-only IC1.
Is supplied to the demodulation unit 2 via The PLL circuit 2 generates a read clock based on the RF signal. In the reproduction-only IC 1 of the present embodiment, the demodulation unit 2 includes a demodulation circuit 21 and a mode information detection circuit 22, detects a synchronization pattern, converts 10-bit data into 8 bits, and further converts Perform the extraction. Reproduction data and a reproduction address are extracted from the demodulation circuit 21. The reproduced data is sent to the data bus 4. The reproduction address is sent to the address bus 5. These reproduction data and reproduction address are taken into the external RAM 14 under the control of the RAM control circuit 14, and the RAM 14 stores the data at the required addresses. The mode information detection circuit 22 includes ID-1 to ID-1 shown in FIG.
Each mode information of ID-8 is detected and extracted. For the extraction, as will be described later, necessary means such as latching and multiple matching are used. The mode information extracted by the mode information detection circuit 22 is sent to the state setting bus 3. And
Mode information is transmitted from the state setting bus 3 to each circuit.

Of the three buses provided in the read-only IC 1, the state setting bus 3 has a function of transmitting the mode information to each circuit. From this state setting bus 3, an error correction circuit
7, a servo circuit 8, an internal reference address generation circuit 9, a de-interleave circuit 10, a 12-16 conversion / interpolation circuit 11, a mute circuit 6, and a clock generation circuit 13 receive mode information. By using such a state setting bus 3,
The mode can be switched in each circuit without using a microcomputer, and the cost can be reduced.

The mute circuit 6 is a circuit to which the state setting bus 3 for transmitting mode information is connected, and which outputs a signal for turning off the gate circuit 12 when the mode information changes. The mute circuit 6 is connected to the address bus 5
The mute circuit 6 can mute the output by the gate circuit 12 even when, for example, a discontinuity in the reproduction address occurs. The specific circuit configuration will be described later.

Next, the error correction circuit 7 reads the data stored in the RAM 15 and performs error detection and correction. And
The data is written into the RAM 15 again. The data bus 4 and the address bus 5 are used for error detection and correction. Mode information such as a sampling frequency, the number of channels, and a quantization rule is sent to the error correction circuit 7 via the state setting bus 3.

In the case of the no tracking system, the servo circuit 8
A capstan servo PWM signal (servo reference signal) is output according to the difference between the reproduction address and the internal reference address. Therefore, the address bus 5 is connected, and the state setting bus 3 is also connected, so that the circuit is switched according to the mode information of the state setting bus 3.

The internal reference address generating circuit 9 is a circuit for generating an internal reference address.
Sent to The internal reference address generation circuit 9 needs to make the address progress half the speed when switching from the short play mode to the long play mode among the various modes. Therefore, according to the signal from the state setting bus 3, the internal reference address generating circuit 2 changes the connection relation of the circuit.

The deinterleave circuit 10 is a circuit for generating an address for deinterleaving, and its output is sent to the address bus 5. As in the case of the internal reference address generation circuit 9, mode information is also sent from the state setting bus 3 to the de-interleave circuit 10, and the generated interleave address changes.

The above-described 12-16 conversion / interpolation circuit 11
This circuit has a function of converting 12-bit data to 16 bits and a function of interpolating, for example, data before and after when data cannot be corrected. The output of the 12-16 conversion / interpolation circuit 11 is sent to the D / A converter via the gate circuit 12. Depending on the data quantization rule, 12 bits to 16 bits
Whether the bit conversion is performed or not is different, and the mode information of the state setting bus 3 is used for the switching.

The gate circuit 12 is a circuit for gating data from the 12-16 conversion / interpolation circuit 11, and is controlled by a control signal from the mute circuit 6. That is,
When the mute circuit 6 responds to the change of the mode information or outputs a signal for shutting down the gate circuit 12 in response to discontinuity of the address signal, the gate circuit 12 is turned off and the output signal is output. Will be stopped.

Further, the state setting bus 3 includes a clock generation circuit 13.
When the mode information changes, various generated clocks also change in accordance with the change in the mode information.

FIG. 2 shows a specific circuit of the demodulation unit 2 enclosed by a two-dot chain line in FIG. 1 and transmits an RF signal to the serial-parallel converter 31. Can be The serial / parallel converter 31 converts a serial input signal into a 10-bit parallel output signal. The 10-bit parallel output is a 10-8 conversion demodulation circuit 32
, Where demodulation according to the conversion table is performed.

From the 10-8 conversion demodulation circuit 32, a parallel output is sent to each of the latch circuits 33 to 38. These latch circuits 33 to 38
Then, necessary data is extracted at each timing. The latch circuit 33 extracts the data signal, and the data signal is sent to the data bus 4 via the buffer 45, and the data is stored in the RAM 15 from the data bus 4. The latch circuit 34 takes out an address signal, and the address signal is sent to the address bus 5 via the buffer 46, and data is stored by the signal on the address bus 5. The address signal is composed of a 4-bit frame address and an 8-bit block address.

The latch circuit 35 latches ID-1 and ID-2 in the mode information. As shown in FIG. 6, these mode information ID-1 and ID-2 are included in a block whose last three digits of the block address are "000", and data is latched at that timing. The data latched by the latch circuit 35 is sent to the multiple match detection circuit 41. The multiple match detection circuit 41 is a circuit that detects that the mode information ID-1 and ID-2 are the same over, for example, two blocks and outputs the same. From the multiple match detection circuit 41, the mode information ID-1 is output to the state setting bus 3 via the buffer 47, and the mode information ID-2 is output to the state setting bus 3 via the buffer 48. Here, the mode information ID-2 is 2-bit information related to the sampling frequency, and the signal ID-1 is 2-bit information related to emphasis.

The latch circuit 36 latches ID-3 and ID-4 in the mode information. These mode information ID-3 and ID-4 are included in a block whose last three digits of the block address are "010", and data is latched at that timing. The data latched by the latch circuit 36 is sent to the multiple match detection circuit 42, and data that matches over a plurality of blocks is output. The mode information ID-3 is output from the multiplex coincidence detection circuit 42 to the state setting bus 3 via the buffer 49, and the mode information ID-4 is output to the state setting bus 3 via the buffer 50. Here, the mode information ID-3 is 2-bit information on the number of channels, and the mode information ID-4 is 2-bit information on the digitization rule.

The latch circuit 37 latches ID-5 and ID-6 in the mode information. The mode information ID-5 is 2-bit information on track pitch, and the mode information ID-6 is 2-bit information on copy prohibition. These mode information ID-5,
ID-6 is included in a block whose last three digits of the block address are “100”, and data is latched at that timing. The data latched by the latch circuit 37 is
The mode information ID-5 and ID-6 are sent to the multiple coincidence detection circuit 43 and coincidence over a plurality of blocks.
The signal is output to the state setting bus 3 via 1,52.

Similarly, the latch circuit 38 is a circuit for latching the mode information ID-7 and ID-8. When the data latched by the latch circuit 38 matches over a plurality of blocks by the multiple match detection circuit 44, the data is sent to the state setting bus 3 via the buffers 53 and 54 as mode information ID-7 and ID-8, respectively. Is output.

Thus, in the demodulation unit, the mode information ID-1 to mode information ID-1
ID-8 is extracted, and the respective mode information is sent to the state setting bus 3 so that the circuit can be changed in accordance with the mode switching.

Configuration of Mute Circuit (FIG. 3) The mute circuit 6 is a circuit that generates a signal for stopping signal output when a change in mode information or an address discontinuity occurs. A part of the mute circuit 6 is shown in FIG. The mode information of the state setting bus 3 is input to the latch circuit 42 via the buffer 41. The latch circuit 42 has 30
A pulse is supplied every msec, and data is latched at that timing. The output of the latch circuit 42 is supplied to the next-stage latch circuit 43 and is also used as one input of an EX-OR circuit 44. A pulse is also supplied to the latch circuit 43 every 30 msec, and data is latched at that timing. The output of the next-stage latch circuit 43 is used as the other input of the EX-OR circuit 44. The output of the EX-OR circuit 44 is input to a mute time setting circuit 45. Then, the output of the mute time setting circuit 45 is sent to the gate circuit 12, and whether the gate circuit 12 is turned off or turned on is controlled.

In order to simultaneously detect a plurality of pieces of mode information and discontinuities in addresses, the configuration from the buffer 41 to the EX-OR circuit 44 is provided in parallel, and the logical sum of the output of the EX-OR circuit 44 is obtained. Just do it.

The operation of the mute circuit 6 will be briefly described. First, for example, it is assumed that certain mode information has changed. Then, since information is input to the latch circuit 42 via the buffer 41, the output of the latch circuit 42 changes at the timing of the first pulse supplied to the latch circuits 42 and 43 after the change, The two inputs of the EX-OR circuit 44 receive different level signals. As a result, an “H” level (high level) signal is output from the EX-OR circuit 44, and the “H” level signal is sent to the mute time setting circuit 45. Then, the mute time setting circuit 45 uses, for example, 30 ms.
An “L” level (low level) signal having a pulse width 16 times ec is generated, and this signal is sent to the gate circuit 12. The gate circuit 12 is turned off by the signal of “L” level,
The output is stopped only during that period, and the occurrence of abnormal sound accompanying the change in the mode information is prevented.

Operation at the time of switching the mode of the read-only IC Next, the circuit operation of the read-only IC 1 of this embodiment when the mode information is switched will be described.

For example, assume that the current mode is a short play mode (standard recording mode) in which the sampling frequency is 48 kHz and the quantization rule is 16 bits (straight line). At this time, in the PCM-ID of the PCM block of the magnetic tape, for example, ID-2 is “00”.
(48kHz), ID-3 is "00" (2ch), ID-4 is "00" (16
The mode information is sent to the state setting bus 3 via the mode information detection circuit 22 of the demodulation unit 2.

Next, when the mode is newly set to the long play mode for long-time recording, in the PCM-ID, ID-2 is set to “0”.
"1" (32 kHz) and ID-4 change to "01" (2 bits), respectively. Such a change in mode information is detected by the demodulation unit 2
The signal of the state setting bus 3 is changed through the mode information detection circuit 22 of FIG. Specifically, the buffer 4 shown in FIG.
8,50 output changes.

When the mode information of the state setting bus 3 changes, first, the clock generation circuit 13 switches the clock of the sampling frequency from 48 kHz to 32 kHz. Further, the internal reference address generation circuit 9 switches the address from half speed by switching from the short play mode to the long play mode. In addition,
In the interleave circuit 10, since the interleave addressing is different between the 48 kHz 16-bit short play mode and the 32 kHz 12-bit long play mode, the generated de-interleave address is changed. The 12-16 conversion / interpolation circuit 11 starts conversion to 16 bits when the number of quantization bits becomes 12 bits.

Further, in response to a change in the mode information of the state setting bus 3, the mute circuit 6 generates a signal for turning off the gate circuit 12 as described above. By the generation of this signal, occurrence of an abnormal sound at the time of mode switching is prevented without using a microcomputer. That is, when such a mode is switched, a signal muted for a certain period of time is sent to the D / A converter.

Operation when Playback Address is Discontinuous The mute circuit 6 operates even when the playback address is discontinuous, and the occurrence of abnormal sound is prevented beforehand in the reproduction-only IC 1 in the signal reproducing device of the present embodiment. You.

For example, even in the same mode, when another piece of music is added in the middle of a piece of music, the reproduction address (frame address) becomes discontinuous. When the servo system is set to the no tracking system, the difference between the reproduction address and the internal reference address generates the PWM signal for the capstan servo, so that the servo is transiently disturbed and abnormal noise is generated. Possibilities arise.

Therefore, the read-only IC 1 of this embodiment is provided with an address bus 5
Are connected to a mute circuit 6, which detects discontinuity in the reproduction address. When such a discontinuity in the reproduction address is detected, a signal for turning off the gate circuit 12 is output from the mute circuit 6 using a circuit similar to the configuration shown in FIG. As a result, occurrence of abnormal sound is prevented beforehand.

In the above-described embodiment, the IC chip of the signal reproducing apparatus is dedicated to reproduction, but may be a chip having a recording function.

〔The invention's effect〕

As described above, the signal reproducing apparatus of the present invention is provided with the state setting bus for transmitting the mode information extracted by the mode information extracting means, and when the mode information transmitted via the state setting bus changes. The main data signal transmitted via the main bus can be muted.
For this reason, the occurrence of abnormal noise that does not require a microcomputer can be prevented, and the cost can be reduced because a microcomputer is not required.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of an example of a signal reproducing apparatus according to the present invention, FIG. 2 is a block diagram showing a circuit configuration of an example of a demodulation section, and FIG. 3 shows a part of a mute circuit of the example. FIG. 4 is a diagram showing a tape format to which the present invention can be applied, FIG. 5 is a diagram showing a PCM data block format in the tape format, and FIG. 6 is a diagram showing a PCM data in the PCM data block format.
It is a figure showing the format of -ID. 1 ... reproduction-only IC 2 ... demodulation unit 3 ... state setting bus 4 ... data bus 5 ... address bus 6 ... mute circuit 11 ... 12-16 conversion / interpolation circuit 12 ... gate circuit 13 ... Clock generation circuit 15 RAM

Claims (3)

(57) [Claims] 1. A signal reproducing apparatus for reproducing a recording medium on which a signal having mode information, an address and main data is recorded, comprising: a demodulating means for demodulating a reproduced signal reproduced from the recording medium; Mode information extracting means for extracting the mode information from the demodulated signal; a state setting bus for transmitting the mode information extracted by the mode information extracting means; and a signal among the signals demodulated by the demodulating means. An address bus for transmitting the address, a data bus for transmitting the main data among the signals demodulated by the demodulation means, and a main bus when the mode information transmitted via the state setting bus changes. Mute means for muting the main data transmitted via a bus. 2. The signal reproducing apparatus according to claim 1, wherein said mode information is an identifier for identifying a plurality of sampling frequencies. 3. The signal reproducing apparatus according to claim 1, wherein said mode information is an identifier for identifying a plurality of quantization bit numbers.