JP2792927B2 - 3-line logical comb filter - Google Patents

Description

The present invention relates to an improvement of a three-line logical comb filter.

(B) Conventional technology A three-line logical comb filter for separating a color component from a color video signal is disclosed in Japanese Patent Application Laid-Open No. 59-39184 (H04N9 / 38).

FIG. 3 is a circuit block diagram of a conventional three-line comb filter. As is clear from this figure, the main circuit is composed of a large level selection circuit and a small level selection circuit.

The large-level selection circuit connects the collector and the emitter of the NPN transistors (Q ₁ ) and (Q ₂ ) in common as shown in FIG. 7 and derives the output from the emitter side.
Each input signal is input to the base of each transistor (Q ₁ ) (Q ₂ ) via a capacitor (C ₁ ) (C ₂ ).
In the figure, (R _e ) is a common emitter resistance, and (R ₁ ) (R ₂ ) and (R ₃ ) (R ₄ ) are base bias setting resistances. Therefore, an output corresponding to the input signal having the higher level of the two input signals is derived from the emitter. That is, the large level selection circuit functions as an OR circuit at a positive level,
Functions as an AND circuit at a negative level.

As shown in FIG. 8, the small-level selection circuit is composed of PNP transistors (Q ₃ ) and (Q ₄ ), and a circuit similar to that shown in FIG. 3 is formed. An output corresponding to the smaller input signal is derived.
As a result, the small-level selection circuit functions as an AND circuit at a positive level, and functions as an OR circuit at a negative level.

The filter shown in FIG. 3 receives the original signal (S ₀ ), the level-inverted 1H delay signal (S ₁ ) and the 2H delay signal (S ₂ ), and first receives the first large level selection circuit (1). ) And the first small-level selection circuit (2), the original signal (S ₀ ) and the 2H delay signal (S ₂ )
And inputs the first large-level selection output and the first delay signal (S ₁ ) to the second low-level selection circuit (3), while the first low-level selection output and the first delay signal (S ₁ ) Is input to the second large-level selection circuit (4). Further, the second small-level selection output and the 0-level signal (φ) are supplied to the third large-level selection circuit (5), and the second large-level selection output and the 0-level signal are supplied to the third small-level selection circuit (6). Each is input, and both outputs are input to an addition circuit (7) to derive the addition.

Accordingly, a positive output is derived from the third large level selection circuit (5), and a negative output is derived from the third small level selection circuit (6).

Therefore, since the large-level selection circuit is effective when the input is positive, focusing on only the positive level of the input of the third large-level selection circuit (5), the input signal becomes (S ₀ ∪S ₂ ) ∩S _{Since the} low-level selection circuit is specified as ₁ and the low-level selection circuit is effective at the time of a negative input, focusing only on the negative level of the input of the third low-level selection circuit (6), the input signal also becomes (S ₀ ∪ S ₂ ) ∩Specified as S ₁ . Since the other of the third large-level selection circuit (5) and the third small-level selection circuit (6) receives the 0-level signal (φ), the arithmetic expression is common to both the positive level and the negative level. the output Sout of the three-line logical comb filter which is the output of the circuit (7) is _{Sout = (S 0 ∩S 2)} ∪S 1 become it is seen. Fig. 5 shows the above equation. As is clear from this figure, only the original signal (S ₀ ) or
When only 2H delay signal (S ₂ ) is input, output (Sou
t) does not occur and only the original signal (S ₀ ) or 2H delayed signal (S
If only ₂ ) does not exist, an output (Sout) is generated.

There is also a three-line logical comb filter as shown in FIG. Output obtained from the comb filter (Sout) is _{Sout = (S 0 ∩S 1)} ∪ (S 1 ∩S 2) + (S 0 ∪S 1) ∩ (S 1 ∪S 2) = S 1 ∩ (S ₀ ∪S ₂ ) + S ₁ ∪ (S ₀ ∩S ₂ ). Fig. 7 shows the above equation. The first term in the above equation indicates a hatched area on the upper right of FIG. 7, and the second term indicates a hatched area on the lower right in FIG.

(C) Problems to be Solved by the Invention In the first conventional example shown in FIG. 2, when only the 1H delay signal (S ₁ ) is present, the output signal is muted. In the second conventional example shown in FIG. 6, when only the 1H delay signal (S ₁ ) does not exist, the signal components of the upper and lower lines are mixed.

Therefore, the present invention improves the first conventional example and adds a color signal band component in a 1H delay signal.

(D) Means for Solving the Problems A delay circuit for delaying a video signal in a horizontal synchronization period, an inversion circuit for inverting the polarity of an input signal, and a plurality of circuits for comparing input signals and selectively deriving a large-level input signal. A large-level selection circuit, a plurality of small-level selection circuits that compare input signals to select and derive a low-level input signal, a horizontal correlation circuit that separates color signal components, and an attenuation circuit that attenuates the level of the input signal. the includes a timing delay circuit for timing for the time lag caused by the signal processing in the horizontal correlation circuit, and an adding circuit for adding an input signal, a color video signal (S ₀₎ and the color video signal (S ₀ ), A first large-level selection circuit (1), a first small-level selection circuit (2), and a 2H delay signal (S ₂ ), which are delayed by two horizontal synchronization periods by the delay circuit. 1 large level A second small signal which receives the output of the color selection signal (1) and the 1H delay signal (S ₁ ) obtained by delaying the color video signal (S ₀ ) by one horizontal synchronization period by the delay circuit and inverting by the inversion circuit. A level selection circuit (3), a second large-level selection circuit (4) that receives an output of the first small-level selection circuit (2) and the 1H delay signal (S ₁ ), and the 1H delay A horizontal correlation circuit (8) to which the signal (S ₁ ) is input, an attenuation circuit (9) to which an output of the horizontal correlation circuit (8) is input, and an output of the second small level selection circuit (3) A first timing delay circuit (10) having an input as an input, a second timing delay circuit (11) having an output of the second large-level selection circuit (3) as an input, and the first timing delay circuit A fourth large-level selection circuit (12) having the output of (10) and the output of the attenuation circuit (9) as inputs, A fourth small-level selection circuit (13) which receives the output of the second timing delay circuit (11) and the output of the attenuation circuit (9) as inputs, and the output of the fourth large-level selection circuit (12). A third signal having a 0 level signal (φ) as an input.
A large-level selection circuit (5), a third small-level selection circuit (6) that receives an output of the fourth small-level selection circuit (13) and the 0-level signal (φ), and This is performed by supplying a three-line logical filter provided with an addition circuit (7) for adding the output of the third large-level selection circuit (5) and the output of the third small-level selection circuit (6).

(E) Operation According to the present invention, when only the first delay signal (S ₁ ) is present, the horizontal correlation output of the attenuated first delay signal is derived.

(F) Embodiment An embodiment in which the present invention is additionally applied to the conventional circuit shown in FIG. 3 will be described below with reference to the circuit block diagram of FIG. In FIG. 1, the same reference numerals are given to the same components as those in FIG. 3, and redundant description is omitted.

This embodiment is characterized by a horizontal correlator (8),
Attenuation circuit (9), fourth large level selection circuit (12) and fourth
The point is that a small level selection circuit (13) is added. First, in this embodiment, the 1H delay signal (S ₁ ) whose polarity is inverted is input to the horizontal correlator (8). As shown in FIG. 9, the horizontal correlator (8) serially connects first and second half-period delay circuits (14) and (16) each exhibiting a delay amount corresponding to a half period of a color subcarrier. The 1H delay signal (S ₁ ) obtained by delaying and inverting the color video signal by 1H is delayed by a half cycle of the color subcarrier in a first half cycle delay circuit (14), and further delayed in a second half cycle delay circuit (16). A half cycle of the color subcarrier is delayed. Further, the 1H delay signal (S ₁ ) is applied to the large level selection circuit (17) and the small level selection circuit (20). First
Delayed by a half-cycle delay circuit (14), polarity inversion circuit (15)
The signal (S ' ₁ ) whose polarity has been inverted at ( ₁ ) is input to the large-level selection circuit (18) and the small-level selection circuit (21). The signal (S ″) delayed by the second half-cycle delay circuit (16)
₁ ) is input to the large-level selection circuit (19) and the small-level selection circuit (22). These six selection circuits (17) ~
(22) A 0 level signal (φ) is input to the other input. Each of the large level selection circuits (17), (18) and (19) selects only the positive side input signal, and the small level selection circuits (20) and (21)
(22) selectively derives only negative input signals. The three types of large-level selection outputs are input to the small-level selection circuit (23), and the minimum-level selection output of the positive-level inputs is selected. The three types of small-level selection outputs are input to the large-level selection circuit (24), and the minimum-level selection output of the negative-level inputs is selected. Both select outputs are adder circuits (25)
Is added and derived.

Therefore, the horizontal correlator (8) cuts the color subcarriers of one cycle or less as noise and removes one cycle of the color subcarriers from the color subcarriers exceeding one cycle as is clear from FIG. That is, this horizontal correlator functions to emphasize components having high correlation with respect to the carrier subcarrier frequency and suppress other components.
The horizontal correlator has a known configuration. However, this horizontal correlator, when the luminance component close to the color subcarrier frequency occurs continuously for 1.5 cycles or more,
The output is regarded as a color signal component, and there is a problem in using all the horizontal correlation outputs as the color signal components.

Therefore, in this embodiment, the horizontal correlation output is attenuated by the attenuation circuit (9).
And the component is attenuated in half. This attenuated output is input to the fourth large level selection circuit (12) together with the second small level selection output, and is input to the fourth small level selection circuit (13) together with the second large level selection output. However, the second
The low-level selection output and the second high-level selection output are respectively passed through first and second delay circuits (10) and (11) in order to adjust the timing to the time delay of the attenuation output accompanying the horizontal correlation processing and the attenuation processing. The fourth large-level selection circuit (12) and the fourth small-level selection circuit (13)
Is input to Therefore, when only the 1H delay circuit (S ₁ ) is generated, the positive-side component of the 1H delay signal is output from the fourth large-level selection circuit (10) and negative from the fourth low-level selection circuit (13). Side components are selectively derived. That is, the fourth large-level selection circuit (12) and the fourth small-level selection circuit (13) add the attenuation output to the output of the first conventional circuit, and the added output Sout becomes Sout = ｛1 / 2h (S ₁ )｝ ∪ ｛(S ₀ ∪S ₂ ) ∩S ₁ ｝ [where h (S ₁ ) indicates the carrier component of S ₁ ] (see FIG. 2).

Therefore, according to the present embodiment, the attenuated color signal component is derived even when only the 1H delay signal is generated, and the muting phenomenon unlike the first conventional example does not occur. Also, when only the 1H delay signal does not exist, the second
There is no bleeding of the color signal components as in the conventional example.

Further, the horizontal correlator of this embodiment is configured to remove the color subcarriers one period at a time, but there is no practical problem because the frequency band of the color signal to be demodulated is narrow. However, with respect to the burst signal portion, there is a possibility that the ACC circuit and the like may be disturbed due to the lack of one cycle of the burst signal. Therefore, during the burst signal generation period, a circuit that passes this horizontal correlator (8) may be added if necessary, and it goes without saying that such a configuration is included in the present invention.

(G) Advantageous Effects of the Invention According to the present invention, a three-line logical comb filter with few malfunctions can be formed, which greatly contributes to improvement of color separation characteristics.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention, and FIG.
3 is a circuit block diagram of the first conventional example, FIG. 4 is a circuit block diagram of the same output characteristic, FIG. 5 is a circuit block diagram of the second conventional example, and FIG. Characteristic explanatory diagram, seventh
FIG. 8 is a circuit diagram of a large-level selection circuit, FIG. 8 is a circuit diagram of a small-level selection circuit, FIG. 9 is a circuit block diagram of a horizontal correlation circuit, and FIG. (8) Horizontal correlator, (9) Attenuation circuit, (12)
... Fourth large level selection circuit (13)... Fourth small level selection circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 9/78

Claims (1)

(57) [Claims] 1. A delay circuit for delaying a video signal in a horizontal synchronization period, an inversion circuit for inverting the polarity of an input signal, and a plurality of large-level selection circuits for comparing input signals to select and derive a large-level input signal. A plurality of small-level selection circuits for comparing input signals to select and derive low-level input signals; a horizontal correlation circuit for separating color signal components; an attenuation circuit for attenuating the level of input signals; a timing delay circuit for timing for the time lag associated with the signal processing, and an adding circuit for adding an input signal, a color video signal (S ₀₎ and the color video signal (S ₀₎ of the delay circuit A first large-level selection circuit (1) and a first small-level selection circuit (2), each of which receives a 2H delay signal (S ₂ ) delayed by two horizontal synchronization periods as described above, and the first large-level selection circuit Circuit (1 ) And a 1H delay signal (S ₁ ) obtained by delaying the color video signal (S ₀ ) by one horizontal synchronization period by the delay circuit and inverting the color video signal (S ₀ ) by the inverter circuit. ) and said first output and said 1H delayed signal of the small level selection circuit (2) (S ₁₎ and a second large-level selection circuit which receives the (4), the 1H delayed signal (S ₁₎ Horizontal correlation circuit with input as input (8)
An attenuation circuit (9) receiving an output of the horizontal correlation circuit (8) as an input, a first timing delay circuit (10) receiving an output of the second small level selection circuit (3) as an input, A second timing delay circuit (11) that receives an output of the second large-level selection circuit (3) as an input, an output of the first timing delay circuit (10), and an output of the attenuation circuit (9). A fourth large-level selection circuit (12) that receives the output of the second timing delay circuit (11) and the output of the attenuation circuit (9). 13), and a third large-level selection circuit (5) that receives the output of the fourth large-level selection circuit (12) and the 0-level signal (φ) as inputs.
A third small-level selection circuit (6) that receives an output of the fourth small-level selection circuit (13) and the 0-level signal (φ), and a third large-level selection circuit (5). ) And an output of the third small-level selection circuit (6).