JP2792351B2 - Program development support device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program development support device, and more particularly to a device for tracing an instruction address.

[0002]

2. Description of the Related Art In recent years, the scale of programs has been increasing, and the operating frequency of target microprocessors has been increasing in order to achieve higher performance. For example, in the clock doubler system, the internal processing of the microprocessor is performed at twice the frequency of the bus cycle while the external bus cycle remains unchanged. ICE (In
-Circuit Emulator) stores the address information output from the microprocessor operating at this high frequency in the address storage memory over the entire bus cycle to be observed. The instruction address information is read, and it is checked whether or not the transition has a desired change.

[0003]

However, in the above configuration, since a large number of high-speed memory elements are used for an address storage memory in order to cope with a high-speed microprocessor, an inexpensive microprocessor evaluation device is provided. It was difficult.

In view of the above problems, the present invention limits the address information to be stored in the address storage memory, thereby reducing the memory capacity, making the address storage slower than the operating frequency of the microprocessor and using a low-speed memory. Thus, an inexpensive program development support device corresponding to a high-speed microprocessor is provided.

[0005]

In order to solve the above-mentioned problems, a program development support apparatus according to the present invention receives an instruction address and an addition control signal output from a microprocessor, and inputs the instruction address and the addition control signal. And an address reproducing unit for reproducing an instruction address based on the information stored in the address storing unit.

[0006]

According to the present invention, the instruction address and the addition control signal output from the microprocessor are stored in the address storage memory of the address storage unit when the instruction address is stored. The storage of this information is performed at regular intervals in synchronization with the operation of the microprocessor, for example, an external bus cycle. In this way, by taking in addresses at fixed intervals instead of taking in addresses in every bus cycle, a low-speed memory element can be used as an address storage memory, and the memory capacity required for address storage can be reduced. . At the time of reproducing the instruction address for analyzing the program operation, the address information and the addition control information are read from the address storage unit. Using instruction addresses stored at regular intervals synchronized with microprocessor operation,
The stored instruction address of the cycle is output as a reproduction address as it is.

The instruction address of the cycle not stored is: (1) If the addition control information is active, add the instruction size to the previous instruction address; if not, (2) If the addition control information is not active, subtract the instruction size from the next instruction address By performing the above, reproduction can be performed.

[0008]

(Embodiment 1) A program development support apparatus according to one embodiment of the present invention will be described below with reference to the drawings. The same numbers and symbols in the drawings used in the following description indicate the same elements throughout the drawings. The target processor used in the explanation is a RISC (Reduced Instr.
uction Set Computer) type, specifically, The
SPARC Architecture Manual Version 8 (1990 Dec 11)
The description is made using the SPARC architecture of Sun Micro Systems, Inc.

FIG. 1 is a configuration diagram of a program development support apparatus according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a microprocessor, which outputs an instruction address 100, an addition control signal 102, and an address invalid signal 103.
Reference numeral 2 denotes a program development support device, which comprises an address storage unit 3, an address reproduction unit 4, and a control unit 5. The three signals output from the microprocessor 1 are input to a first input latch 34 of the address storage unit 3. The first input latch 34 stores the three signals at fixed intervals synchronized with the operation of the microprocessor. In this case, the first input latch 34 stores the three signals at a cycle twice as long as the bus cycle of the microprocessor 1. The address information 305, the addition control information 306, and the address invalid information 307 output from the first input latch 34 are stored in the address storage memory 33.

The address reproducing section 4 receives a flip-flop 43 which receives address information 300 which is one of the outputs of the address storage memory 33, and outputs either the output 403 of the flip-flop 43 or the address information 300 to a first input terminal. An adder 40 having a second input 405 of 4 or -4 for performing addition and subtraction of an instruction size (an instruction 1 word is 4 [bytes]), and an output 402 of the adder 40 or a flip-flop 43 And a selector 44 for selecting one of the outputs 403. The output 407 of the selector 44 is input to the switch 45, and the output is output from the program development support device 2 as a reproduction address 400. First input 404 and second input 4 of adder 40
05 is selected by the selection signals 505 and 506 output from the control unit 5, respectively. The selector 44 is selected by an address selection signal 507 output from the control unit 5, and the switch 45 is controlled by an output control signal 508 output from the control unit 5. These control signals are generated based on the addition control information 303 and the address invalid information 304 input to the control unit 5.

FIG. 2 is a diagram showing changes in the instruction address 100, the addition control signal 102, and the address invalid signal 103 in three types of instruction strings. Here, a control transition instruction in which a program is not executed in address order will be described. In the SPARC architecture, an instruction causing a program control transition is called a control transition instruction (CTI: Control Transf
er Instruction), in which the program control transition does not occur immediately after the execution of the control transition instruction but occurs after the execution of the instruction immediately following the control transition instruction (called the delay instruction). Delayed control transfer instruction (DCTI)
Call. In particular, the case where the delay control transition instruction is performed twice consecutively is a delay control transition pair (Delayed Control Transfer Coupling).
les). Table 1 shows an instruction sequence for explaining the delay control transition pair. Address 12 and 1
The transition of the instruction address changes depending on what kind of control transition instruction is placed at address 6.

[0012]

[Table 1]

In the SPARC architecture, program control transitions are classified into three types. The transition of these three types of program control will be described below with reference to FIG. The symbols used in this description are as follows.

B * cc indicates Bicc, Bfcc, or Bccc, and is a conditional branch instruction (including B * A described below) for an integer unit, a floating point unit, and a coprocessor unit, respectively. B * cc untaken indicates that the branch condition is not satisfied in these conditional branch instructions and the program control does not shift.

B * A indicates BA, FBA or CBA, and is a delay control transition instruction in which program control always transitions to the branch destination regardless of the contents of the condition code. Also,
a is an anal bit, and the delay instruction of B * A (a = 0) is always executed, and the delay instruction of B * A (a = 1) is not executed. However, since the instruction is read into the microprocessor 1, there is no difference in the transition of the instruction address by the anal bit.

DCTI unconditional indicates a CALL, JMPL, RETT or B * A (a = 0), and is a delay control transition instruction to which program control transits unconditionally after executing the delay instruction.

DCTI Taken is CALL, JMPL, RETT, B * cc take
n or B * A (a = 0), which is a delay control transition instruction to which the control of the program transits after executing the delay instruction.

In the first instruction sequence shown in FIG. 2A, instructions are read in the order of addresses, and only the address invalid signal 103 becomes active only in the first cycle immediately after the system reset. This is from address 0 to 2
This indicates that none of the instructions up to address 4 are control transition instructions, or that program control has not transitioned even if a single control transition instruction has been executed, such as the branch condition not being satisfied.

In the second instruction sequence shown in FIG.
The address invalid signal becomes active in the first cycle immediately after the system reset, as in the case of the instruction sequence. The control of the program transits to address 40 in the sixth cycle, and the addition control signal 102 becomes active in this cycle. This is because the instruction at address 12 is DCTI Taken and the instruction at address 16 is not a control transition instruction, or (Table 1)
The instruction at address 12 and address 16 are both delay control transition instructions as shown in the instruction sequence, the instruction at address 12 is B * A (a = 1), and the instruction at address 16 is either Either a transition instruction or the instruction at address 12 is DCTI unconditional and the instruction at address 16 is
When B * cc untaken, such program control transition is performed.

In the third instruction sequence shown in FIG.
After the address, the control of the program is shifted to the address 60 in the seventh cycle. The addition control signal 102 becomes active in the cycle in which the program control transitions to address 40, and the address invalidation signal 103 becomes active immediately after the system reset.
It becomes active twice in the cycle in which the program control is shifted to the address. This is because the instructions at addresses 12 and 16 are both delay control transition instructions as shown in the instruction sequence in Table 1, and the instruction at address 12 is a DCTI uncondition instruction.
al, the instruction at address 16 is DCTI Taken or B * A
In the case of (a = 1), such program control transition is performed.

FIG. 3 is a diagram for explaining how the outputs 305, 306 and 307 of the first input latch 34 in the third instruction sequence are stored in the address storage memory 33.

FIG. 4 is a view for explaining the generation of the reproduction address 400 based on the information stored in the address storage memory 33.

Here, the case of the third instruction sequence in which the transition of the program control of the instruction is the most complicated will be described with reference to FIGS. 1, 2, 3 and 4.

When the instruction address is stored, the instruction address 100, the addition control signal 102, and the address invalid signal 103 output from the microprocessor 1 are stored in the first input latch 34. Since the storage is performed in a cycle twice as long as the external bus cycle of the microprocessor 1, even if the same instruction sequence is executed, the information stored and output in the first input latch 34 includes the information shown in FIG. , There are two cases, as shown in FIG. The address information 305, the addition control information 306, and the address invalid information 307 output from the input latch 34 are stored in the address storage memory 33 as shown in FIG. In this way, by taking in the address twice in the bus cycle instead of taking in the address every bus cycle, a low-speed memory element can be used for the address storage memory 33 and the memory capacity required for storage is reduced by almost half. Can be done.

At the time of address reproduction for program analysis,
As shown in FIG. 4, the address information 30 is stored in the address storage unit 3.
0, addition control information 303, and address invalid information 304 are read. The address information 300 is input to the flip-flop 43 and output as a flip-flop output 403 one cycle later.

Hereinafter, the reproduction address 400 in each cycle will be described.
The method of generating the will be described. In the first cycle, the address information 300 is selected as the first input 404 of the adder 40, and -4 is selected as the second input 405. The selector 44 selects the output 402 of the adder 40, and
4 is input to the switch 45. However,
In FIG. 4A, the address invalid information 304 is active. Therefore, the output control signal 508 is also activated and the reproduction address 400 is not output. FIG.
In (b), the output 407 of the selector 44 is the switch 45
It is output as it is and becomes the reproduction address 400.

In the second cycle, the selector 44 selects and outputs the output 403 of the flip-flop 43, and outputs it as the reproduction address 400 from the switch 45.

In the third cycle, as in the first cycle, the address information 300 is selected as the first input 404 of the adder 40, and -4 is selected as the second input 405. The selector 44 selects and outputs the output 402 of the adder 40, and outputs it as the reproduction address 400 from the switch 45.

In the fourth cycle, as in the second cycle, the selector 44 selects the output 403 of the flip-flop 43 and outputs it as the reproduction address 400 from the switch 45.

In the fifth cycle, in FIG.
The behavior is the same as the first and third cycles. In FIG. 4B, the addition control information 303 becomes active and the output 4 of the flip-flop 43 becomes the first input 404 of the adder 4.
03 is selected, and +4 is selected as the second input 405. The selector 44 selects the output 402 of the adder 40, and the output 407 of the selector 44 is input to the switch 45. The output 407 of the selector 44 is directly output from the switch 45 and becomes the reproduction address 400.

In the sixth cycle, the same behavior as in the second and fourth cycles is performed. In the seventh cycle, FIG.
In (a), the output control signal 508 becomes active because the address invalid information 304 becomes active. As a result, the reproduction address is not output, and it can be notified to the outside that the reproduction address is invalid. In FIG. 4B, the behavior is the same as in the first and third cycles.

In the eighth cycle, the same behavior as in the second, fourth and sixth cycles is performed. As described above, the instruction address of the stored cycle is stored as it is in order to store the instruction address in a cycle twice as long as the bus cycle. If the instruction size is not active, the instruction size is subtracted from the next instruction address to reproduce the instruction. However, when the transition of the program control occurs twice consecutively as in the third instruction sequence, the reproduction of the transition address of the first program control is reproduced with a half probability as shown in FIG. Can not. Even in this case, since it is known that the transition of the program control has occurred, there is no problem in debugging the program. Further, in an architecture in which there is no third instruction sequence in which the transition of the program control is performed twice consecutively, the address invalid signal 103 is unnecessary.

The above description has been made on the case where the pipeline operation is executed by the microprocessor 1 without being disturbed. Here, a case where the pipeline operation is disturbed and the execution of the instruction is stopped will be described with reference to FIG.

FIG. 5 is a block diagram of a program development support device for explaining the storage of an instruction address, an addition control signal, and an address invalid signal in the first embodiment. 1 is different from the first input latch 34 and the address storage memory 33 in FIG.
Is controlled by the address storage control signal 104 output from the microprocessor 1.

When the execution of the instruction is stopped, the instruction address 100 output to the outside does not change, and the same instruction address 100 is output until the execution of the instruction is restarted. The address storage signal 104 is output according to the number of execution steps of the instruction. However, since the storage of the address information is performed twice as long as the bus cycle, the address storage signal 104 becomes active once for two execution steps. This address storage control signal 10
4 controls the storage of the first input latch 34 and the address storage memory 33.

As a result, when instruction execution is stopped, there is no need to store an unchanged instruction address in the address storage memory 33, so that the memory capacity required for address storage can be reduced more effectively. Becomes

As described above, the address storage unit which receives the instruction address 100, the addition control signal 102, and the address invalid signal 103 output from the microprocessor and stores the instruction address, the addition control signal, and the address invalid signal. 3 and an address reproducing unit 4 for reproducing an instruction address based on the information stored in the address storing unit, the address information is fetched at twice the cycle of the bus cycle. No memory element is required, and the memory capacity can be reduced.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 6 is a block diagram of a program development support apparatus according to a second embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a microprocessor, which outputs an instruction address 100, an addition control signal 102, and an address invalid signal 103.
Reference numeral 2 denotes a program development support device, which comprises an address storage unit 3, an address reproduction unit 4, and a control unit 5. The three signals output from the microprocessor 1 are input to a first input latch 34 of the address storage unit 3. The instruction address 100 is the second input latch 3
6 is also input. The first input latch 34 stores the three signals in a cycle twice as long as the bus cycle of the microprocessor 1. Similarly, the second input latch 36 stores the instruction address 100 at twice the cycle of the bus cycle. Address information 305, addition control information 306, and address invalid information 307 output from the first input latch 34
Are stored in the address storage memory 33. The address information 308 output from the second input latch 36 is input to the target address storage memory 35 and stored by the address invalid signal 103. However, the first cycle executed immediately after the system reset is not stored and the second cycle is not executed.
Only the target address after the cycle is stored.

The address reproducing unit 4 receives the address information 300 which is one of the outputs of the address storage memory 33 as an input, and outputs either the output 403 of the flip-flop 43 or the address information 300 to the first input. 4 or-to make 404 the instruction size
4 as a second input 405;
The selector 44 selects either the output 402 of the flip-flop 43, the output 403 of the flip-flop 43, or the output 309 of the target address storage memory 35, and the selector 45 that controls the output of the selector 44.

The output of the selector 44 is a reproduction address 400
Is output from the program development support device 2. The first input 404 and the second input 405 of the adder 40 are selected by selection signals 505 and 506 output from the control unit 5, respectively. The selector 44 is selected by an address selection signal 507 output from the control unit 5. The selector 45 is controlled by an output control signal 508 output from the control unit 5. These control signals are generated based on the addition control information 303 and the address invalid information 304 input to the control unit 5. The difference from FIG. 1 is that the second input latch 3
6 and a target address storage memory 35 are provided.

FIG. 7 is a diagram for explaining the third instruction sequence in FIG.
This corresponds to the case (a) and describes generation of a reproduction address. Here, the method of address reproduction in the case of the seventh cycle in FIG. 4A in which the instruction address cannot be reproduced in the first embodiment will be described with reference to FIGS.

When storing the instruction address, the instruction address 100, the addition control signal 102, and the address invalid signal 103 output from the microprocessor 1 are stored in the first input latch 34. The storage is performed in a cycle twice as long as the bus cycle of the microprocessor 1. The second input latch 36 is also performed at twice the cycle of the bus cycle, but the storage cycle is shifted by one cycle from the input latch 34 as shown in FIG. The address information 305, the addition control information 306, and the address invalid information 307 output from the input latch 34 are stored in the address storage memory 33.
Also, the address information 30 output from the input latch 36 is output.
8 is stored by the address invalid signal 103.

At the time of address reproduction for program analysis,
As shown in FIG. 7 (b), the address information 3
00, addition control information 303, and address invalid information 304 are read. The address information 300 is input to the flip-flop 43 and output as a flip-flop output 403 one cycle later.

Hereinafter, a method of generating the reproduction address 400 in the seventh cycle, which is the first cycle when the transition of the program control is performed twice, will be described. Except for the seventh cycle, the instruction address is reproduced in the same manner as in the first embodiment.

In the seventh cycle, when the address invalid information 304 becomes active, the selector 44 does not select the adder output 402 and the target address information 309 is not selected.
Is controlled by an address selection signal 507. As a result, the target address 40 is output as the reproduction address 400. As described above, even when the transition of the program control occurs twice consecutively, the correct target address can always be reproduced.

As described above, the address storage unit receives the instruction address 100, the addition control signal 102, and the address invalid signal 103, and stores the information at a constant interval. An address information storage memory 33 that stores an output of the first input latch and outputs address information, addition control information, and address invalid information;
A second input latch for storing and outputting the instruction address at the same interval as the first input latch; and a target address storage memory for storing the output of the second input latch by the address invalid signal. Thus, the instruction address can be reproduced in all cases only by storing the address twice as long as the bus cycle of the processor.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 8 is a block diagram of a program development support apparatus according to a third embodiment of the present invention. The difference from FIG.
Except for the second input latch 36, a target address input 310
And an address storage control input 31 for controlling address storage
1 is provided. A method of reproducing an instruction address will be described with reference to FIGS.

After the instruction address storage is completed, the address storage memory 33 is read out in descending order and the address invalid information 304 is set to 1
The address of the entry immediately before the entry that is described is read. The instruction at address 12, which is the address obtained by subtracting 4 from this address (address 16 in FIG. 3D), is the first instruction of the delay control transition instruction pair, and is the instruction address for which the target address of this instruction cannot be generated. . The target address of this instruction is extracted from the disassembly result (for example, target address 40 at address 12 in Table 1).
Address) and stored in the target address buffer 35 via the target address input 310. Play address 4
The method of generating 00 is the same as that of the second embodiment, and the correct target address can always be reproduced even when the transition of the program control occurs twice consecutively.

As described above, the address storage unit receives the instruction address 100, the addition control signal 102, and the address invalid signal 103 as inputs, and stores the information at regular intervals. An address information storage memory 33 for storing the output, and a target address for storing the target address of the first delay control transition instruction obtained by disassembling in the instruction sequence in which the delay control transition instruction pair appears, and outputting this as target address information Since the storage memory 35 is provided, the instruction address can be reproduced in all cases only by storing the address twice as long as the bus cycle of the processor.

In the present embodiment, the instruction size and the instruction address are 4 bytes each for the description of the SPARC architecture as an example, but the instruction size and the instruction address may be of any size. Also, the interval between storages in the first and second input latches is twice as long as the bus cycle. However, in a clock doubler type microprocessor in which the bus cycle does not match the operating frequency of the processor, the processor operating frequency is Should be stored twice as often.

[0053]

As described above, according to the present invention, an address storage unit that receives an instruction address and an addition control signal output from a microprocessor and stores the instruction address and the addition control signal is provided. By providing an address reproducing unit that reproduces the instruction address based on the information stored in the memory, the address can be stored later than the bus cycle. Can be easily handled.

Also, since less address information needs to be stored, the number of memory elements to be used can be reduced, and a more inexpensive program development support device can be provided.

Further, since more address information can be stored as the address information to be stored is reduced, it is possible to trace address for a long time with an address storage memory having the same capacity. As a result, the efficiency of program development such as debugging of a large-scale program can be dramatically improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a program development support device according to a first embodiment of the present invention;

FIG. 2 is a timing chart showing changes in an instruction address, an addition control signal, and an address invalid signal in the embodiment.

FIG. 3 is a timing chart showing storage of information in an address storage memory in the embodiment.

FIG. 4 is a timing chart showing address reproduction based on stored information in the embodiment.

FIG. 5 is a configuration diagram of a program development support device for explaining storage of an instruction address, an addition control signal, and an address invalid signal in the embodiment;

FIG. 6 is a configuration diagram of a program development support device according to a second embodiment of the present invention.

FIG. 7 is a timing chart showing address reproduction based on stored information in the embodiment.

FIG. 8 is a configuration diagram of a program development support device according to a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Microprocessor device 2 Program development support device 3 Address storage unit 4 Address reproduction unit 5 Control unit

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kazuki Ninomiya 1006 Kazuma Kadoma, Kadoma City, Osaka Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-4-130932 (JP, A) 102936 (JP, U) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 11/28-11/34

Claims (9)

(57) [Claims] 1. An address storage unit for receiving an instruction address and an addition control signal output from a microprocessor and storing the instruction address and the addition control signal, based on information stored in the address storage unit. A program development support device comprising an address reproducing unit for reproducing an instruction address. 2. The address storage unit according to claim 1, wherein said instruction address and said addition control signal are input and said input latch stores said information at a constant interval, and said output of said input latch is said constant. An apparatus for supporting program development, comprising: an address information storage memory that stores address information and addition control information at the same interval as the interval. 3. The address reproducing unit according to claim 1, wherein the flip-flop receives the address information output from the address storage unit as an input, and receives the address information or the output of the flip-flop as a first input. And a selection of each input and addition / subtraction operation are controlled by addition control information output from the address storage unit, and the output of the addition / subtraction unit or the flip-flop is used as a reproduction address. A program development support device for selecting and outputting any one of the outputs of a loop based on addition control information. 4. An address storage unit according to claim 1, wherein said instruction address and said addition control signal are input together with an address storage control signal output from a microprocessor in accordance with the number of instruction execution steps. An input latch for storing the addition control signal, and an address information storage memory for storing an output of the input latch and outputting address information and addition control information, wherein the input latch and the address information storage memory are A program development support device characterized in that storage is controlled by an address storage control signal. 5. An address storage unit for receiving an instruction address, an addition control signal, and an address invalid signal output from a microprocessor, and storing the instruction address, the addition control signal, and the address invalid signal in the address storage unit. An address reproducing unit for reproducing an instruction address based on the stored information, and notifying that the reproduction address is invalid based on the address invalidation information output from the address storing unit. Support equipment. 6. An address storage unit according to claim 5, wherein said instruction address, said addition control signal, and said address invalid signal are input, and an input latch for storing these information at regular intervals, and an output of said input latch. And an address information storage memory for storing address information, addition control information and address invalid information at the same interval as the predetermined interval. 7. The address storage unit according to claim 6, wherein the second input latch stores and outputs an instruction address at the same interval as the first input latch, and outputs the output of the second input latch to the second input latch. A program development support device characterized by adding a target address storage memory for storing a target address according to an address invalid signal and outputting the target address. 8. An address storage unit according to claim 6, wherein, in an instruction sequence in which the delay control transition instruction is repeated twice, the target address of the first delay control transition instruction obtained by disassembling is stored and the target address is stored. A program development support device comprising a target address storage memory for outputting as address information. 9. An address reproducing unit according to claim 8, wherein any one of three of the output of said adder / subtractor and the output of said flip-flop as well as the target address information output from said target address storage memory is used as a reproduction address. A program development support device for selecting and outputting based on the addition control information and the address invalid information.