JP2790677B2 - Timer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a timer device used for speed checking in, for example, a variable speed vehicle control device, and includes a microcomputer, an output circuit, and a monitoring circuit. The microcomputer starts timing when a start signal is supplied to an input terminal, outputs a time-up signal to a first output terminal, and outputs a signal having a constant frequency to a second output terminal during normal operation. And output a frequency signal different from that in normal operation to a second output terminal during abnormal operation. The output circuit is a circuit that generates a timer output when a time-up signal is given from the first output terminal. The monitoring circuit is connected to the output circuit so as to prohibit the timer output from being generated when the abnormal time frequency signal is supplied from the second output terminal. A general-purpose logic circuit can be used by a computer, the number of parts can be reduced, the time can be set with high accuracy, and an abnormality check function can be provided to provide a highly reliable timer device with high fail-safe characteristics. It was made.

<Prior Art> Conventionally, a timer device generally uses a CR time constant circuit. As is well known, a timer device using a CR time constant circuit outputs a time-up signal when a voltage between terminals of a capacitor charged through a resistor reaches a preset threshold level. The time required from the start of charging until the charging voltage of the capacitor reaches the threshold level is the set time as the timer.

<Problems to be Solved by the Invention> However, it is difficult for the timer device using the CR time constant circuit to set the time with high accuracy. Further, as time setting and circuit operation become more sophisticated and complicated, sophisticated and complicated logic circuits are required, and the versatility is lacking. Furthermore, when realizing a timer device used for speed checking of a variable speed vehicle control device, the side where the time becomes longer in the event of a failure is fail-safe, but a fail-safe timer device using a CR time constant circuit is used. It is not always easy to configure.

Therefore, an object of the present invention is to solve the conventional problems described above, to generalize a logic circuit, thereby reducing the number of components, to set a highly accurate time, and to have an abnormality check function. It is to provide a fail-safe timer device.

<Means for Solving the Problems> In order to solve the problems described above, the present invention is a timer device including a microcomputer, an output circuit, and a monitoring circuit, wherein the microcomputer has at least It has an input terminal to which a start signal is supplied, a first output terminal, and a second output terminal, and starts timing when a start signal is supplied to the input terminal, and a time-up signal. Is output to the first output terminal, and a signal having a constant frequency is output to the second output terminal during normal operation.
During abnormal operation, a frequency signal different from the normal
The output circuit has an input side connected to the first output terminal, and generates a timer output when the time-up signal is supplied from the first output terminal. Wherein the monitoring circuit has an input side connected to the second output terminal, and when a frequency signal at the time of abnormality is given from the second output terminal, prohibits a timer output from being generated. It is characterized by being coupled to the output circuit.

<Operation> The microcomputer starts timing when a start signal is supplied to the input terminal, and outputs a time-up signal to the first output terminal. The output circuit generates a corresponding timer output when the time-up signal is supplied from the first output terminal. Here, the microcomputer is
Usually, a crystal oscillation circuit is provided as a reference time source, so that highly accurate time setting is possible. Therefore, a timer output with high time accuracy can be obtained. In addition, since the time is set by the microcomputer, the microcomputer has versatility, requires less logic circuits other than the microcomputer, and substantially reduces the number of components.

Also, the microcomputer outputs a signal having a constant frequency to the second output terminal during normal operation, and outputs a frequency signal different from that during normal operation to the second output terminal during abnormal operation, The monitoring circuit has a second input
Is connected to the output terminal of the microcomputer and is connected to the output circuit so as to inhibit the timer output from being generated when the abnormal time frequency signal is supplied from the second output terminal. , The timer output is extended to the longer side. Therefore, a fail-safe timer device is obtained.

<Embodiment> FIG. 1 is a block diagram of a timer device according to the present invention. In the figure, 1 is a microcomputer, 2 is an output circuit, and 3 is a monitoring circuit.

The microcomputer 1 has at least an input terminal 101 to which a start signal for timing is supplied, a first output terminal 102, and a second output terminal 103. 104 is a crystal oscillation circuit for supplying a clock signal, and 105 is a correction circuit.

The microcomputer 1 then starts counting when the start signal V _in to the input terminal 101 is supplied, and outputs the time-up signal to the first output terminal 102. The time counting method for outputting the time-up signal includes a method in which the timer time is determined by the number of steps of the program in the microcomputer 1 and a program that is started once when the timer built in the microcomputer 1 times out. A method of determining the time by the number of times and the like can be considered.

When the microcomputer 1 is operating normally according to the program and when the crystal oscillation circuit 104 is oscillating a clock signal of a predetermined frequency, a signal having a constant frequency appears at the second output terminal 103. . When the microcomputer 1 operates abnormally, including a deviation in the clock frequency of the crystal oscillation circuit 104, a frequency signal different from that in the normal state appears at the second output terminal 103.

The output circuit 2 includes a driver 21 and a relay 22, and an input side of the driver 21 is connected to a first output terminal 102. The output side of the driver 21 is guided to a relay 22, and when a time-up signal is given from a first output terminal 102, the driver 21 drives the relay 22 to generate a corresponding timer output. In the embodiment, since the driver 21 is configured as an inverter, the time-up signal is provided with a logic 0, at which time the relay 22 is driven. Then, the contact output when the relay 22 is excited becomes the timer output.

The monitoring circuit 3 has an input side connected to the second output terminal 103, and when the abnormal-time frequency signal is supplied from the second output terminal 103, the monitoring circuit 3 inhibits generation of the timer output. Is combined with In the embodiment, the monitoring circuit 3 includes a bandpass filter 31, a level determiner 32,
The circuit includes a negative rectifier circuit 33, an AND gate 34, a level determiner 35, a voltage doubler negative rectifier circuit 36, and a relay 37. It is known that the monitoring circuit 3 having such a circuit configuration has a fail-safe circuit configuration in which the relay 37 at the last stage is not excited when a circuit failure occurs. 38 is a diode.

FIG. 2 shows an example of a fail-safe negative rectifier circuit 33 necessary for making the monitoring circuit 3 fail-safe. 331, 3
32 is an input terminal, 333 and 334 are output terminals, 335 and 336 are capacitors, and 337 and 338 are diodes. When a pulse input signal having the input terminal 331 as a positive electrode is supplied between the input terminals 331 and 332, the capacitor 335 is charged with the illustrated polarity through the diode 337, and the capacitor 336 negatively outputs the output terminal 333 through the diode 338. since the charge in the direction of the end 334 and the positive, negative rectified voltage V ₀ is obtained at the output terminal 333-334.
In the event of an open or short circuit failure,
Since not appear negative voltage V ₀ to the output terminal 333 and 334, a fail-safe.

AND gate 34 has a negative rectifier circuit at the input end with invert
33 outputs are supplied, and a clock signal is supplied to the other input terminals.

The contact 371 of the relay 37 is connected between the driver 21 of the output circuit 2 and the relay 22. Thus, the monitoring circuit 33 is coupled to the output circuit 2 so as to inhibit the output circuit 2 from generating a timer output.

When the microcomputer 1 is operating normally, a signal having a predetermined frequency appears at the second output terminal 103. This frequency signal is applied to a bandpass filter 31.
And the level is determined by the level determiner 32, and is negatively rectified by the negative rectifier circuit 33. Here, if the oscillating frequency of the crystal oscillation circuit 104 is normal and a rectified output is obtained, the output of the AND gate 34 becomes logic 1 and an output is obtained at the level determination unit 35. The output becomes a predetermined value. Accordingly, the relay 37 is excited by the output of the voltage doubler rectifier circuit 36, and the contact 371 is launched.

With the contact 371 of the relay 37 up, the first output terminal 1
When the time-up signal appears at 02, the drive signal of the driver 21 is supplied to the relay 22 via the contact 371, so that the relay 22 operates and timer output is obtained.

On the other hand, when the microcomputer 1 performs an abnormal operation such as a program runaway, the second output terminal
At 103, a frequency signal different from that during normal operation appears,
Since the output of the band-pass filter 31 substantially disappears and the outputs of the level determiner 32, the negative rectifier circuit 33, the AND gate 34, the level determiner 35, and the voltage doubler negative rectifier circuit 36 disappear, the relay 37 is de-energized. And the contact 371 falls. For this reason, the output circuit 2 is opened between the driver 21 and the relay 22, and even if a time-up signal appears at the first output terminal 102, the relay 22 is not excited. The non-excitation of the relay 22 is fail-safe because the timing at which the timer output occurs is delayed in time and coincides with the direction in which the timer setting time becomes longer.

Even if the microcomputer 1 is operating normally, if the clock frequency of the crystal oscillation circuit 104 becomes incorrect, the output of the AND gate 34 disappears. Therefore, also in this case, the relay 37 is in the non-excited state and the contact 371 is dropped, so that the relay 22 is in the non-excited state, and the timer is controlled in a direction of increasing the set time, and the fail-safe property is maintained.

In the embodiment, the operation state of the relay 22 is input to the microcomputer 1 using the contact 221 of the relay 22. If microcomputer 1 is a relay
If the contact 221 is closed without issuing a command to operate the operation of the second output terminal 103, the second output terminal 103
And outputs a frequency signal corresponding to the abnormal operation. As a result, the relay 37 is in the non-excited state, and the contact 371 falls, so that the relay 22 is in the non-excited state, and the fail-safe property is secured.

Further, the output of the level determiner 32 is fed back to the input of the microcomputer 1. Then, at a certain time interval, for example, every two seconds, the output to the second output terminal 103 is stopped, and it is checked whether the band-pass filter 31 and the operational amplifier constituting the level determiner 32 oscillate. It is supposed to.

FIG. 3 is a block diagram of another embodiment of the timer device according to the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same components. The microcomputer includes at least two systems A and B.

Microcomputer 1A and B based microcomputer 1B of the system A comprises at least a first input terminal 101 and _A, 101 _B which start signal is supplied for clocking, the second input terminal
It has 106 _A , 106 _B , first output terminals 102 _A , 102 _B, and second output terminals 103 _A , 103 _B , respectively. And the first
As in the embodiment shown, the start of time measurement when the start signal V _in is supplied to the first input terminal 101 _A, 101 _B, the time-up signal the first output terminal 102 _A, 102 _B , outputs a signal having a constant frequency during normal operation to the second output terminals 103 _A , 103 _B, and outputs a frequency signal different from that during normal operation to the second output terminals 103 _A , 103 _B during abnormal operation. Output.

First output of the microcomputer 1B of the first output terminal 102 _A and B systems of the microcomputer 1A of the A-system 102
_B is guided to the input terminal of the AND gate 4, and supplies the logical product output to the output circuit 2.

Furthermore, the second input terminal 106 _A of the microcomputer 1A belonging to the A system, the first microcomputer 1B of B system
The output terminal 102 _B is connected, to the second input terminal 106 _B of the microcomputer 1B belonging to the B system is connected to the first output terminal 102 _A of the microcomputer 1A of the A-system, a so-called crosswise connection It has become.

Each microcomputer 1A belonging to the microcomputer 1A and B systems belonging to the A-system, the other system first output 102 _B or 102 from _A autologous second input 106 _A of 10
6 Based on the signal given to _B , the time difference between the output of the own system and the output of the other system is monitored. Then, when a time lag of a predetermined value or more occurs between the two, the second output terminal 10 of the own system is used.
3 and outputs a frequency signal corresponding to the abnormal operation to the _A or 103 _B. When the frequency signal corresponding to the abnormal operation to the second output terminal 103 _A, 103 _B is output, the monitoring circuit 3A, a relay 37 _A, 37 _B constituting the 3B becomes non-excited, its contact 371 _A or 371 _B falls. As a result, the relay 22 constituting the output circuit 2 is de-energized, and the time from when the start signal is supplied to when the time-up signal is output is controlled to be longer, and the fail-safe property is maintained. It is. Thus, in the case of the embodiment shown in FIG.
Since the system microcomputers 1A and 1B are configured to monitor each other, fail-safe performance is further improved. 221 and 222 are contacts of the relay 22.

FIG. 4 shows an application example in which the timer device according to the present invention is incorporated in a variable speed vehicle control device. In the figure, 5 is a track, 6 is a vehicle, 7 is a ground device, and 8 is an on-board device provided on the vehicle 6.

The ground device 7 has a first ground element 71, a second ground element 72, and a receiving circuit 73. First ground child 71 and second ground child 72
Along the running direction a of the vehicle 6, it is arranged at a speed Shosa section with a spacing l _1. Although not shown, a plurality of similar sets of the first ground element 71 and the second ground element 72 are provided.

The first ground element 71 constitutes a kind of antenna for receiving a transmission wave transmitted from the on-board device 8. The transmission wave received by the first ground element 71 is transmitted to the receiving circuit via the matching unit 74.
Entered in 73. The second ground coils 72 constitute a resonance circuit of the coil L ₀ and capacitor C _0.

The receiving circuit 73 includes a resistance attenuator 731, a bandpass filter 7
32, a resistance attenuator 733, an amplifier 734, a level determiner 735, an amplifier 736, and the like. MR is a relay and MR ₁ is its contact.

737 indicates a timer device according to the present invention. The timer device used for the variable-speed vehicle control device is the third device.
The embodiment shown in the figure is desirable from the viewpoint of fail-safe. 22 is the relay shown in FIGS. 1 and 3, etc., 371 _A , 37
1 _B is a contact point of the relays 37 _A and 37 _B.

The on-board device 8 includes an on-board element 81, an oscillation circuit 82, and a frequency selection circuit 83. The vehicle upper arm 81 is a kind of antenna and forms a feedback circuit of the oscillation circuit 82.

The oscillation circuit 82 includes an amplification circuit 821, a phase circuit 822, and a limiter 82.
3 and an amplifier circuit 824, etc., and has a circuit configuration in which the output of the final-stage amplifier circuit 824 is fed back to the input-stage amplifier circuit 821 through the vehicle armature 81. A frequency sorting circuit 830 the frequency sorting circuit 83 for detecting the constantly oscillating frequency f _0, the n resonant frequency f ₁ ~f _n, i.e. the n frequency sorting circuit 831~83n corresponding to n point information It is configured by connecting in parallel. Each of the frequency selection circuits 831 to 83n has a circuit configuration including a band-pass filter, an amplification circuit, a level detector, an amplification circuit, and the like.

In the above vehicle control system, on-board coil 81 is in a state not bound to the second ground element 72, the oscillation circuit 82 is operating in constant oscillation frequency f _0.

When the upper armature 81 of the onboard device 8 provided in the vehicle 6 passes over the first ground arm 71, the oscillation frequency f ₀ is always received by the first ground arm 71, and is guided to the receiving circuit 73. I will In the receiving circuit 73 extracts the component of the constantly oscillating frequency f ₀ by a band-pass filter 731, amplified by the amplifier 734, the level determined by the level determination unit 735 is further amplified by the amplifier 736. Since the output signal of amplifier 736 is provided to relay MR, relay M
R is energized contact MR ₁ is closed.

By contact MR ₁ is closed, the timer device 737 starts counting. Then, when the preset time element is counted, the count-up signal is output from the timer device 737, and the relay 22 is excited. Relay 22 is energized, the contacts 223 is closed, the second ground coils 72, the resonance circuit of the coil L ₀ and capacitor C ₀ is a state of being short-circuited by the contacts 222, not act as a resonant circuit.

In the above configuration, when the vehicle 6 is traveling at a predetermined reference internal speed, the timer device 737 is operated by the timer device 737 after passing the ground child 71 and before passing the ground child 72.
Is up. Therefore, when the vehicle 6 passes over the second ground element 72, the contact 223 is already closed, and the second ground element 72 does not operate as a resonance circuit. Therefore, the vehicle control operation is not performed between the second ground child 72 and the vehicle upper child 81.

However, when the vehicle 6 is traveling at a speed exceeding a predetermined traveling speed, after passing over the first ground child 71 and then passing over the second ground child 72, a timer device is provided. Reference numeral 737 indicates that the timer is counting, the relay 22 is still in the non-excited state, and the contact 223 connected to the resonance circuit of the second grounding element 72 is open. Therefore, when relative to each other when the on-board coil 81 passes through the second ground element 72 on at all times the oscillation frequency f ₀ is Edit the resonance frequency f ₁ ~f _n of the second ground coil 72. The frequency _dividing frequencies f _{1 to} f _n are determined by a frequency selection circuit 83.
It sorts and decodes 1-83n and performs vehicle control such as emergency braking.

When the microcomputer constituting the timer device 737 performs an abnormal operation such as a program runaway or an abnormal oscillation frequency of the crystal oscillation circuit, the contact 371 _A or the contact 371 _B falls as described in FIG. 1 and FIG. And then relay
22 is not excited. Therefore, when the contact point 223 of the relay 22 is kept open and the vehicle armatures 81 are opposed to each other when passing over the second ground arm 72, the oscillation frequency f ₀ is always set to the resonance frequency f ₀ of the second ground arm 72. ₁ ~f _n is Edit, the vehicle control emergency braking or the like is performed. As a result, failsafe in train operation is maintained.

In the above variable-speed vehicle control device, the accuracy of vehicle speed detection depends on the time setting accuracy of the timer device 737. When using the timer device according to the present invention,
Since the time setting can be made highly accurate, a train speed can be detected with high accuracy, and a fail-safe variable-speed vehicle control device can be realized.

<Effects of the Invention> As described above, according to the timer device of the present invention, the following effects can be obtained.

(A) The microcomputer starts timing when a start signal is supplied to an input terminal, outputs a time-up signal to a first output terminal, and the output circuit outputs a time-up signal from the first output terminal. Is provided, a corresponding timer output is generated, so that a highly accurate time setting by a microcomputer is possible, and a timer device capable of obtaining a timer output with high time accuracy can be provided.

(B) Since the time is set by the microcomputer, the timer is versatile, requires less logic circuits other than the microcomputer, and can provide a timer device having substantially fewer parts.

(C) The microcomputer outputs a signal having a constant frequency to the second output terminal during normal operation, and outputs a frequency signal different from that during normal operation to the second output terminal during abnormal operation. The monitoring circuit has an input connected to the second output terminal, and is coupled to the output circuit so as to inhibit a timer output from being generated when an abnormal frequency signal is supplied from the second output terminal. Therefore, when the microcomputer performs an abnormal operation, the timer output is extended to a longer time side. Therefore, a fail-safe timer device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a timer device according to the present invention, and FIG.
The figure is an electric circuit diagram of the negative rectifier circuit that constitutes the timer device,
FIG. 3 is a block diagram of another embodiment of the timer device according to the present invention, and FIG. 4 is a block diagram of a vehicle control device. 1, 1A, 1B ...... microcomputer 2 ...... output circuit 3, 3A, 3B ...... monitoring circuit 101, 101 _A, 101 _B ...... inputs 102, 102 _A, 102 _B ...... first output 103, 103 _A , 103 _B ... second output terminal

Claims (2)

(57) [Claims] 1. A timer device including a microcomputer, an output circuit, and a monitoring circuit, wherein the microcomputer has at least an input terminal supplied with a start signal for timing, and a first output terminal. And a second output terminal, and starts timing when the start signal is supplied to the input terminal, and outputs a time-up signal to the first output terminal. A signal having a constant frequency is output to the second output terminal, and a frequency signal different from that during normal operation is output to the second output terminal during abnormal operation. A monitoring circuit that is connected to a first output terminal and generates a timer output when the time-up signal is supplied from the first output terminal; and an input side of the monitoring circuit is connected to the second output terminal. There are, when the abnormal frequency signal from said second output terminal is provided, so as to prohibit timer output occurs,
A timer device coupled to the output circuit. 2. The microcomputer is provided with at least two systems, and each of the microcomputers includes at least:
A first input terminal to which a start signal for timekeeping is supplied, a second input terminal, a first output terminal, and a second output terminal; When a start signal is supplied, timing is started, a time-up signal is output to the first output terminal, a signal having a constant frequency is output to the second output terminal during normal operation, and a signal is output to the second output terminal during abnormal operation. A frequency signal different from the normal state is output to the second output terminal, and the second output terminal is connected to the first output terminal of a microcomputer of another system, Based on a signal given from the first output terminal, a time difference between the output of the own system and the output of the other system is monitored, and when a time difference between the two outputs exceeds a predetermined value, the second output terminal is monitored. And outputting a frequency signal corresponding to the abnormal operation. Timer device as claimed in.