JP2785644B2 - Decoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding circuit, and more particularly to a current switching type logic circuit (Cu
rent Mode Logic circuit.
The present invention relates to a decoding circuit having a CML circuit configuration.

[0002]

2. Description of the Related Art A CML circuit has a high operating speed because it is based on the operation of a transistor in a non-saturated region, and is therefore widely used as a standard circuit for a decoding circuit requiring a high-speed operation.

An ECL (Emi) which is a typical example of a CML circuit
Describing an example of a decoding circuit using a ter Coupled Logic circuit, this decoding circuit receives a k-bit (k is an integer of 2 or more) input code signal, and for each of these k bits, a true and a complementary code bit. An input buffer circuit for outputting a pair, and an ECL circuit type for receiving a true or a complement for each bit of the output from the input buffer circuit in a different combination to generate a selected level or non-selected level decoded output. The decoding unit includes 2 ^k logic circuits and 2 ^k output circuits for amplifying the decoded outputs.

Each of the logic circuits has a collector arranged in a one-to-one correspondence with k bits of the input code signal and commonly connected to each other, and a base receiving one of the true and complement code bit pairs, respectively. K first bipolar transistors each having a connected emitter, a base receiving a reference voltage (a voltage at an intermediate level between the logic value “1” level and the logic value “0” level of the input code signal), and the base described above. A second bipolar transistor having an emitter connected to the emitter of the first bipolar transistor, a load resistor connected between a collector of the second bipolar transistor and a power supply terminal,
A first constant current source circuit connected at one end to emitters of the first and second bipolar transistors and supplying a predetermined operating current to the transistors in response to an active level of a control signal; A corresponding decode output is generated from a connection point with the collector of the second bipolar transistor.

Each of the output circuits includes a third bipolar transistor including a collector connected to the power supply terminal, a base receiving a corresponding decode output, and an emitter forming an output electrode. A second constant current source circuit connected to the emitter of the third transistor and supplying a predetermined operating current to these transistors in response to the active level of the control signal.

[0006] Assuming that each of the k first bipolar transistors of the logic circuit is turned on and off in response to the logic values "1" and "0" of the input to the base, respectively, When all of the inputs to the bases are at logic level "0", these transistors are all off, the second bipolar transistor is on, and the operating current from the first constant current source circuit is all the second bipolar transistor. Through to the load resistance. At this time, the decode output is at the selected level. on the other hand,
When at least one of the input signals at the bases of the k transistors is at the logic "1" level, the transistor is turned on, so that the voltage of the common connection emitter is attracted to the power supply voltage side and the second bipolar transistor is turned on. Is turned off, and no current flows from the constant current source circuit to the load resistance. At this time, the decode output is at the non-selection level.

When the input code signal to the base consists of only true code bits, the decode output is at the selected level when all of the code bits are at the logical value "0". Sometimes it is a non-selection level. If only the input signal to the base corresponding to the least significant bit of the input code signal is a complementary code bit, the decode output corresponding to the input code signal having the least significant code bit of logical value “1” is at the selected level. , And the non-selection level for other code bit combinations.

[0008] Since the decode circuit comprises a 2 ^k-number of logic circuits for receiving respectively different true / complement code bits combined with one another to supply the input code signal of k bits, 2 ^k
One of the decoded outputs can be at the selected level.

The constant current source circuit included in the above-described logic circuit and output circuit is generally composed of a bipolar transistor and a resistor which receive a control signal of an active level as a base during the operation of the decoding circuit. Recently, MOS transistors are often used because the current in the saturation region can be controlled only by the gate voltage and the number of elements can be reduced.

[0010] The number of circuit elements of the decoding unit in the decoding circuit when the constant current source circuit is constituted by MOS transistors as described above is calculated here. The number of circuit elements of each logic circuit is such that the first bipolar transistor is k in number equal to the number of bits of the input code signal, the second bipolar transistor is a load resistor and the MOS of the first constant current source circuit.
And one transistor. The number of circuit elements in the output circuit is one for each of the third bipolar transistor and the MOS transistor of the second constant current source circuit. Accordingly, the number of circuit elements of one set of the logic circuit and the output circuit is (k + 5), and the number of the circuit elements of the entire decoding section is (k + 5) × 2 ^k since there are 2 ^k of these sets in the decoding section. Becomes That is, in the above-described circuit configuration, in order to increase the number of bits of the input code signal, the number of circuit elements in the decoding unit must be significantly increased.

A representative example of means for realizing multi-bit input code signals without substantially increasing the number of circuit elements is a predecoder system comprising a combination of a 2-4 predecoder and a main decoder. Decoding circuit.

The decoding circuit of this predecoder system has
A 2-4 predecoder for decoding each combination of two bits of the input code signal into four predecode outputs, and a main decoder for receiving and decoding each of these predecode outputs in a different combination from each other; Provide the number of combinations.

A specific circuit of the 2-4 predecoder is, for example, according to a circuit described in “LSI Handbook”, page 510, edited by The Institute of Electronics and Communication Engineers, Ohmsha, Ltd., of a first bipolar transistor receiving an input code signal at its base. A second bipolar transistor having a base for receiving a reference voltage and an emitter connected to the emitter of the first bipolar transistor;
And second load resistors respectively connected to the collectors of the first and second bipolar transistors, and a first constant current source for supplying an operating current to the first and second bipolar transistors and the first and second load resistors. Third and fourth double-emitter type circuits each having a circuit, a base connected to the collectors of the first and second bipolar transistors, respectively, and a pair of emitters forming a predecode output electrode.
, And second and third constant current source circuits for supplying operating currents to the third and fourth bipolar transistors, respectively, for each bit of the input code signal. On the other hand, the main decoder is configured by a circuit equivalent to the decoding unit of the above-described decoding circuit (hereinafter, a first example).

Next, the number of circuit elements of this pre-decoder type circuit is the same as that of the decoding unit of the first example, that is, the input code signal is composed of k bits, and the constant current source circuit is composed of MOS transistors. It is calculated under the condition.

Since the 2-4 predecoder has nine elements per one bit of the input code signal, it has 9 × k elements for all bits of the input code signal. Further, the decoder requires one transistor corresponding to the first bipolar transistor of the above-mentioned decoding part at a rate of one for every two bits of the input code signal, and five other circuit elements (k / 2 + 5).
And a total of 2 ^k decoders are needed, so (k
/ 2 + 5) × 2 ^k pieces. Therefore, the total number of circuits of the predecoder system is 9 × k + (k / 2 + 5) × 2 ^k .

The effect of reducing the number of circuit elements by the circuit of the predecoder system appears when the input code signal is 6 bits or more, and the effect increases as the number of bits increases. For example, in the case of 8 bits, 28% is reduced by 2376 from 3328 in the first example, and in the case of 12 bits, 69632
This is a 35% reduction of 45154 pieces per piece.

[0017]

The above-described conventional decoding circuit has a problem that the number of circuit elements increases in the first example, and the second example of the predecoder system which solves this problem has a high speed operation. During the decoding operation, it is necessary to keep the control signal at the active level and continue to supply the operating current from each of the constant current source circuits to the corresponding transistor. In addition, since the same amount of current flows through all circuits including a circuit corresponding to a non-selection level decode signal, there is a disadvantage that a large amount of operation current does not contribute to the decode operation and power consumption increases. This disadvantage is the same for the first example.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a decoding circuit adapted to a high-speed operation capable of coping with an increase in the number of bits of an input code signal without increasing the number of circuit elements and reducing power consumption.

[0019]

The decoding circuit according to the present invention comprises k bits (k is 3 or more) composed of an m-bit first partial code signal and an n-bit second partial code signal.
An input buffer circuit that outputs a true and a complementary code bit string corresponding to each of the bits of the input code signal in response to the input code signal, and an input buffer circuit that corresponds to each of all the bits of the first partial code signal. true / complement code bits either code of one of comprises 2 ^m pieces of first CML circuit different combinations received by the select level / non-selection level selection control signal and outputs each to each other said first portion code signal sequence A first decoding unit for setting one of the 2 ^m selection control signals to a selection level in response to the content;
Each of the 2 ^m selection control signals is arranged in one-to-one correspondence, receives one of the selection control signals, responds to the selected level, responds to the activation level, responds to the non-selection level, and is lower than the activation level. A constant current source for generating a current at an inactivation level is provided. When the current at the activation level is generated, the second partial code signal receives any one of true / complement bits corresponding to all bits in a different combination. An active-level / inactive-level, inactive-level decode output is generated when the above-mentioned inactive-level current is generated.
ⁿ second CML circuits are provided corresponding to each of the 2 ^m selection control signals, and one of the 2 ⁿ decode signals corresponding to the selection level selection control signal is provided in the second portion. And a second record unit that sets an active level in response to the code content of the code signal.

[0020]

In the decoding circuit according to the present invention, the CML
Since the circuit is used, high-speed operation can be ensured, and only the 1/2 ^m circuit of the 2 ^{m + n} second CML circuits has an activation level operating current, and the activation is performed in other circuits than the above. Since the operating current of the inactivation level lower than the level is supplied, power consumption can be reduced correspondingly. Also, with the increase in the number of bits of the input code signal, 2 ^{m + n} second CMLs
The reduction in the number of circuit elements in the entire second decoding unit due to the reduction in the number of circuit elements in the circuit is 2 ^m first CMs.
Since the number of circuit elements of the entire first decoding unit including the L circuit is exceeded, the number of circuit elements can be reduced correspondingly, and a reduction effect of 10 bits or more can be obtained more than that of a circuit of the predecoder system.

[0021]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a circuit diagram showing a specific circuit example of first and second logic circuit portions of this embodiment.

The decoding circuit of the present invention has m bits (m
Is an integer of 1 or more) of the first partial code signal IN _1i (i =
1, 2,..., M) and k bits (k is an integer of 3 or more and k) consisting of an n-bit (n is an integer of 1 or more) second partial code signal IN _2j (j = 1 _,. = M + n) and an input buffer circuit 1 which outputs true bit strings IN _1i T, IN _2j T and complementary bit strings IN _1i C, IN _2j C corresponding to each bit of the input code signal.
And receiving either one of the true bit sequence IN _1i T of all the bits of the first partial code signal IN _1i and the complementary bit sequence IN _1i C to output a selection control signal of a selection level or a non-selection level. A CML circuit 201 and a first output circuit 202 for converting the selection control signal to a predetermined level are provided, and one of true and complementary bit strings corresponding to all bits of the first partial code signal IN _1i is different from each other. 2 ^m first logic circuit units 2x (x = 1, 2, 2) received in combination
, M, M = 2 ^m ).
A first decoding unit 2 for setting one of 2 ^m selection control signals to a selection level in response to the code content of
Receiving one of the level conversion signals (SCx, hereinafter referred to as selection control signals SCx, x = 1, 2,..., M) of the ^m selection control signals, the activation level and the non-selection in response to the selection level A constant current source circuit for generating a current of an inactive level lower than the activation level in response to the level, and a true bit string IN corresponding to each bit of the second partial code signal IN _2j when the current of the activation level is generated _2j T and complementary bit string IN _2j
C, the second CML circuit 301 which generates an inactive level decoded output when the active level or inactive level current or the inactive level current is generated, and buffers the decoded output (hereinafter, a decode signal). DC _xy , y = 1 to N, N = 2 ⁿ ) second
²ⁿ second logic circuit units (3xy) each having a different combination of true and complementary bit strings corresponding to all bits of the second partial code signal IN _2j. the 2 ^m pieces of selection control signals SCx respectively provided corresponding the 2 ^m pieces of selection control signals to SCx
Among the 2 ⁿ decode outputs DCxy corresponding to the signal of the selected level among the second partial code signals IN
2nd to make active level in response to _2j code content
And a decoding unit 3.

The first logic circuit section 2x and the second logic circuit section 3xy will be described in more detail. The first logic circuit section 2x includes one bit for each bit of the partial code signal IN _1i.
Collectors arranged in a one-to-one correspondence and commonly connected to each other and true value bits IN _1i T of corresponding bits of partial code signal IN _1i
And m bipolar transistors Tb21, Tb22,..., T each having a base for receiving one of the complementary bits IN _1i C and an emitter commonly connected to each other.
base and the bipolar transistor Tb21 receiving the intermediate level of the reference voltage Vrcd of binary b2 and partial code signals IN _1i, Tb22, ..., bipolar transistors Tb2r having a collector for receiving the emitter and the power supply potential V _CC1 connected to the emitter of Tb2m , One end of which is connected to the collectors of bipolar transistors Tb21, Tb22,..., Tb2m, and the other end of which receives power supply potential V _CC1.
1 and a source electrode connected to the power supply of the potential Vbb, a drain electrode connected to the emitters of the bipolar transistors Tb21, Tb22,..., Tb2m and Tb2r, and a gate electrode receiving the control signal CCS.
An N-channel MOS transistor Tm21 of a constant current source circuit for supplying a predetermined operating current to the bipolar transistor in response to the active level of S; and a first CML for outputting a selection control signal from one end of the load resistor R1.
A circuit 201, a bipolar transistor Tb20 having a collector connected to the power supply of the potential V _CC2 and a base receiving the selection control signal, a level shift element LS1 including a diode connected at one end to an emitter of the bipolar transistor Tb20, and a potential Vbb. Having a source electrode connected to the power supply, a gate electrode receiving the control signal CCS, and a drain electrode connected to the other end of the level shift element LS1, the bipolar transistor Tb20 and the level shifter responding to the active level of the control signal CCS. A first output circuit 202 including an N-channel type MOS transistor Tm20 of a constant current source circuit for supplying a predetermined operation current to the element LS1, and outputting a level-selected selection control signal SCx from the drain electrode of the MOS transistor Tm20; Equipped You. On the other hand, the second logic circuit unit 3xy
Are arranged corresponding to each of the bits of the partial code signal IN _2j , the collector and a base receiving one of the true bit IN _2j T and the complementary bit IN _2j C of the corresponding bit of the partial code signal IN _2j. N bipolar transistors Tb31 each having an emitter commonly connected to each other
Bipolar transistor Tb3 having a base receiving .tau.Tb3n and reference voltage Vrcd, and an emitter connected to the emitters of bipolar transistors Tb31-Tb3n.
r, a power supply potential V _CC2 at one end, a load resistor R2 having the other end connected to the collector of the bipolar transistor Tb3r, a source electrode connected to the power supply of the potential Vbb, and a drain connected to the emitters of the bipolar transistors Tb31 to Tb3n and Tb3r. An electrode and a gate electrode receiving selection control signal SCx, and activates an active level in response to signal SCx and inactivates an inactive level in response to an unselected level to bipolar transistors Tb31 to Tb3n and Tb3.
and a second CML circuit 301 including a N-channel MOS transistor Tm31 of a constant current source circuit for supplying a load to the load resistor R2 and generating a decode output from the collector of the bipolar transistor Tb3r, and a collector connected to the power supply of the potential V _CC2. A bipolar transistor Tb30 having a base receiving the decode signal, a source electrode connected to the power supply of the potential Vbb, a drain electrode connected to the emitter of the bipolar transistor Tb30, and a gate electrode receiving the selection control signal SCx. Signal C
An N-channel MOS transistor Tm30 of a constant current circuit for supplying an activation level current in response to the selection level by Sx and an inactivation level current in response to the non-selection level to bipolar transistor Tb30. Output circuit 30 that outputs buffer-amplified decode output _DCxy from the drain electrode of
2 is provided.

In this embodiment, the partial code signal IN
The logical value “1” of _1i and IN _2j is a voltage level higher than the reference voltage Vrcd (hereinafter, high level), and the logical value “0” is a voltage level lower than the reference voltage Vrcd (hereinafter, low level).
Is set to

In the first CML circuit 201 of this embodiment, the bipolar transistors Tb21, Tb22,.
Only when all true / complementary bits of the partial code signal IN _1i input to the base of Tb2m are logical values “0” (low level), all the operating currents from the MOS transistor Tm21 of the current source circuit are supplied to the bipolar transistor Tb2r. , Bipolar transistors Tb21, Tb22,.
Since the current does not flow through Tb2m, these transistors (Tb
21-Tb2m), the selection control signal output from the connection point between the collector and the load resistor R1 is almost at the high level (selection level) of the power supply potential V _CC1 . When at least one of the true / complementary bits of the partial code signal IN _1i input to the bases of the transistors (Tb21 to Tb2m) includes a signal having a logical value “1” (high level), The transistor corresponding to the logical value “1” is turned on, and the load resistance R1
, An operation current flows from the MOS transistor Tm21, so that the selection control signal is at a low non-selection level.

The selection control signal from the first CML circuit 201 is level-shifted by the voltage between the base and the emitter of the bipolar transistor Tb20 of the first output circuit 202 and the voltage between the terminals of the level shift element LS1, and the selection control signal SCx Is supplied to the second logic circuit unit 3xy.

When the selection control signal SCx is at the selection level,
MOS transistors Tm31, Tm30 of constant current source circuit
Activation level current from the bipolar transistor T
The signals are supplied to b31 to Tb3m, Tb3r, and Tb30, and the second logic circuit unit 3xy is activated. In this state, if all the base inputs of the bipolar transistors Tb31 to Tb3n are logic values "0", the activation level current from the MOS transistor Tm31 flows through the bipolar transistor Tb3r to the load resistor R2, so that the voltage drop is large. becomes, the decode signal DC _xy selection level (low level) is outputted through the bipolar transistor TB30. If there is at least one signal of logic value "1" at the base input of bipolar transistors Tb31 to Tb3n, the transistors corresponding to logic value "1" are turned on and bipolar transistors Tb connected in common are connected.
Since the emitter voltage of b3r increases, the bipolar transistor Tb3r is turned off, and the current at the activation level is not supplied to the load resistor R2. As a result, the voltage drop across the load resistor R2 becomes extremely small, from the emitter of the bipolar transistor TB30, decoded output DC _xy of non-selection level (high level) occurs close to the supply potential V _CC2.

When the selection control signal SCx is at the non-selection level, the current of the inactivation level is supplied from the MOS transistors Tm31 and Tm30 to the bipolar transistors Tb31 to Tb31.
It is supplied to Tb3n, Tb3r and Tb30. In this state, even if the base inputs of bipolar transistors Tb31 to Tb3n are all logical values "0" and the current of the inactivation level from MOS transistor Tm31 is all supplied to load resistor R2 through bipolar transistor Tb3r, the current level remains the same. , The voltage drop of the load resistor R2 is small, and the decode signal _DCxy stays within the range of the inactive level (high level). If at least one signal of logical value "1" is present at the base input of bipolar transistors Tb31 to Tb3n, bipolar transistor Tb
Since 3r is turned off, the load resistor R2 is a current from the MOS transistor Tm31 does not flow, therefore decode signal DC _xy also this time is inactive level (high level). That is, when the selection control signal SCx is at the non-selection level, the decode signal _DCxy remains at the inactive level irrespective of the code content of the second partial code signal _IN2j , and the second logic circuit unit 3xy is at the non-selection level. It becomes active.

[0030] As described above, the activation level of current from the MOS transistor Tm31 when the selection control signal SCx selection level, sufficient to bring the decoded signal DC _xy to the active level by the voltage drop across the load resistor R2 The current at the non-selection level is set to a low level so that the voltage drop of the load resistor R2 is small and the decode output _DCxy stays in the inactive level range.

In the conventional decoding circuit, all (2 ^k ) decoding circuits including not only a circuit for decoding output at a selected level (active level) but also a circuit for decoding output at a non-selected level (inactive level) are included. Since the same operating current continues to flow through the circuit, a large amount of operating current does not contribute to the decoding operation, and the current consumption increases. On the other hand, in the present invention, 2 ^k second 2
Of the logic circuit unit 3xy, the current of the activation level flows through only some of the circuits, and the current of the inactivation level lower than the activation level flows through the other circuits. Operating current is reduced, and power consumption can be saved accordingly.

Next, the power saving effect of the present invention will be described in more detail.

First, as conditions, the operating current of the first logic circuit unit 2x and the second logic circuit unit 3xy in the present invention
The activation level current (operating current of a circuit having two current source circuits) is a reference value "1", and the inactivation level current of the second logic circuit unit 3xy is 1 / A (A is a positive real number). )age,
The input code signal is k bits, and the bit numbers of the first and second partial code signals are m bits and n bits, respectively.
Also, the load impedance of the decoded output is assumed to be sufficiently high, and the input buffer circuit is excluded from the target.

The total operating current of the decoding circuit of the present invention under the above conditions is 2 ^m +2 ⁿ + (2 ^k -2 ⁿ ) / A.
The first term of the above equation is the operating current of the first logic circuit section, the second term is the operating current of the second logic circuit section in an activated state, and the third term is the operating current of the second logic circuit section in an inactive state. is there.

On the other hand, the total operating current in the first example of the prior art is 2 ^k , and in the second example, three constant current source circuits are required for one bit of the input code signal in the 2-4 predecoder. Therefore, the operating current of this part is set to 1.5, and 1.5 k +
2 ^k . FIG. 3 shows the respective operating currents when 1 / A = 0 (that is, the current at the inactivation level is 0) by substituting specific numerical values for k, m, and n described above.

Referring to FIG. 3, the operating current of the second conventional example is larger than that of the first example by the amount of the 2-4 predecoder. In contrast to the first conventional example, the operating current of the present invention exhibits a saving effect when k = 3 or more, and the saving effect increases as k increases. The range of the operating current of the present invention in FIG. 3 indicates that the value changes depending on the values of m and n. In the above description, the operating current has been described. However, if the power supply voltages are the same, the operating current ratio and the power consumption ratio become equal, so that the operating current can be replaced with power consumption (the same applies to the following description). ).

In the example of FIG. 3, since 1 / A = 0, that is, the current at the inactive level is set to 0, the effect of saving power consumption is increased, but the transition time from the inactive state to the active state is increased. And the effect on high-speed operation appears. Therefore, a small amount of operating current is supplied even in the inactive state to shorten the transition time and reduce the influence on high-speed operation. FIG. 4 shows the operating current (power consumption) with respect to the number of bits of the input code signal of the present invention and the first conventional example when 1 / A = 1/5.

Referring to FIG. 4, the power saving effect according to the present invention appears when the number of bits (k) of the input code signal is 3 or more, and increases as the number of bits increases. For example, for 8 bits or more, the minimum is almost 30% and the maximum is 70%.
Up to 75% savings. The condition where the maximum saving effect is obtained is when the number m of bits of the first partial code signal and the number n of bits of the second partial code signal are closest to each other, and the minimum saving effect is n. Is 1.

Next, the number of circuit elements of the decoding circuit according to the present invention is calculated as compared with the first and second conventional examples. Also in this case, the input buffer circuit does not count.

In the first and second examples of the prior art, since the calculation formula has already been obtained, the calculation formula is used (first
Example: (k + 5) × 2 ^k , Second Example: 9 × k + (k / 2
+5) × 2 ^k ). In the present invention, the first decoding unit is (m + 6) × 2 ^m , and the second decoding unit is (n + 5) × 2 ^m
k (k = m + n). In the case of the present invention, the number of circuit elements changes according to the values of m and n, and when k is 5 or more, n is 3 or 4.
It becomes the lowest when FIG. 5 shows the number of circuit elements with respect to the bit number k of the input code signal in the first example and the second example of the present invention (in the case of the present invention, only the minimum number of circuit elements is shown). In the present invention, a reduction effect appears when k is 5 or more as compared with the first example of the related art, and the effect increases as k increases. For example, it is reduced by 36% for 10 bits and 42% for 12 bits. When compared with the second conventional example in which the number of circuit elements is reduced, up to 9 bits are almost the same, but with 10 bits or more, the reduction effect appears.
About 2% can reduce about 10%.

Referring to FIG. 6, which shows a modification of the above-described embodiment, the second logic circuit unit 3xy of this modification is shown.
a, the load element connected to the collector of the bipolar transistor Tb3r of the second CML circuit 301a has the source electrode having the power supply potential V _cc2 and the gate electrode having the selection control signal S.
Px-type MOs each receiving Cx and connecting the drain electrode to the collector of the bipolar transistor Tb3r
It is formed by the S transistor Tm32.

In this modification, when the selection control signal SCx is at the non-selection level (low level), the resistance value of the MOS transistor Tn32 can be made small, and when it is at the selection level, it can be made large. The operating current of MOS transistor Tm31 in the inactive state) can be increased, and high-speed operation can be easily ensured.

Although the first and second CML circuits are the ECL circuits using bipolar transistors in the above-described embodiment and the modified embodiment, other CML circuits, for example, circuits using MOS transistors may be used. . Further, when m and n at which the power saving effect is the highest and m and n at which the number of circuit elements are the lowest are different, m and n depend on which of the power consumption and the number of circuit elements is emphasized. May be determined.

[0044]

As described above, according to the present invention, one of the 2 ^m selection control signals is set to the selection level in response to the m-bit first partial code signal of the input code signal, 2 ⁿ CMs corresponding to each of the above selection control signals
Only the 2 ⁿ logic circuit sections corresponding to the selection control signal of the selection level among the logic circuit sections by the L circuit are activated, and one of the output decode signals of the 2 ⁿ logic circuit sections in the activated state is activated. One of them is set to the active level in response to the n-bit second partial code signal of the input code signal, so that a high-speed operation can be secured because the CML circuit is used, and 2 ^{m + n} The activation level of the operating current is applied only to the 1/2 ^m circuit among the second CML circuits;
Since an operating current of an inactivation level lower than the activation level is supplied to circuits other than the above circuits, power consumption can be reduced by that amount, and 2 ^{m + n} number of bits are increased with an increase in the number of bits of the input code signal. The number of circuit elements in the second decoding unit as a whole due to the decrease in the number of circuit elements in the second CML circuit is smaller than that in the entire first decoding unit including 2 ^m first CML circuits. Therefore, the number of circuit elements can be reduced correspondingly, and a reduction effect of 10 bits or more can be obtained more than that of the circuit of the predecoder system.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of first and second logic circuit units of the embodiment shown in FIG.

FIG. 3 is a diagram showing an effect of reducing power consumption under a predetermined condition of the embodiment shown in FIG. 1;

FIG. 4 is a diagram showing an effect of reducing power consumption under another condition of the embodiment shown in FIG. 1;

FIG. 5 is a diagram showing an effect of reducing the number of circuit elements of the embodiment shown in FIG. 1;

FIG. 6 is a circuit diagram of a second logic circuit part of a modification of the embodiment shown in FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Input buffer circuit 2 1st decoding part 3 2nd decoding part 21-2M 1st logic circuit part 201 1st CML circuit 202 1st output circuit 301,301a 2nd CML circuit 302 2nd output Circuits 311 to 3MN, 311a to 3MNa Second logic circuit unit

Claims (6)

(57) [Claims] 1. A k-bit (k is 3 or more) composed of an m-bit (m is an integer of 1 or more) first partial code signal and an n-bit (n is an integer of 1 or more) second partial code signal. An input buffer circuit for respectively outputting true and complementary code bit strings corresponding to each of the bits of this signal in response to an input code signal of (integer), and an input buffer circuit corresponding to each of all the bits of the first partial code signal. wherein comprising a first current switching type logic (CML) circuits either the receiving mutually different combinations select level or non-selection level selection control signal of 2 ^m pieces of output respective true and complement of the coding bit string first 2 in response to the code content of the partial code signal of 1.
a first decoding unit for the selection level of one of the ^m selection control signal, one pair of the 2 ^m pieces of selection control signals 1
And a constant current generator receiving an activation level in response to one of the selection control signals and generating an activation level in response to the selection level and a non-activation level lower than the activation level in response to the non-selection level. A current source circuit for generating an active level or inactive level decoded output by receiving one of the second partial code bit strings in a different combination when generating the active level current, and generating the inactive level current output sometimes in the active level of ^the 2 ⁿ to produce a decoded output second current switching type logic (CML) includes a circuit corresponding to said 2 ^m pieces of selection control signals of said 2 ^m pieces of selection control signals the active level in response to one of the 2 ⁿ pieces of decoded output corresponding to the selection level of the signal to the code content of the second part code signal Decoding circuit, characterized in that it comprises a second decoding section that. 2. An emitter commonly connected to a base corresponding to each of the bits of the first partial code signal and receiving one of a true bit and a complementary code bit of the corresponding bit. A second bipolar transistor comprising m first bipolar transistors, a base receiving a first reference voltage, and an emitter connected to the emitter of the first bipolar transistor; a gate electrode receiving a control signal; A first constant current source for supplying a predetermined operating current to the first and second bipolar transistors in response to the active level of the control signal;
And a MOS transistor for outputting a selection control signal of a selection level / non-selection level in response to the code content of the first partial code signal.
L) circuit and a first output circuit for converting a selection control signal from the first current switching type logic (CML) circuit to a predetermined level and outputting the converted signal, and 2 ^m first logic circuits The second decoding unit is arranged corresponding to each of the bits of the second partial code signal, and the collector connected in common with each other and the true and corresponding bits of the second partial code signal N third bipolar transistors each having a base receiving one of the complementary code bits and an emitter commonly connected to each other, a base receiving a second reference voltage, and an emitter of the third bipolar transistor; the fourth of the 2 ^m pieces and the load element connected to either the collector of the bipolar transistor and the third and fourth bipolar transistor having a connected emitters A gate electrode receiving a level conversion signal of a selection control signal from one of the output circuits; an activation level in response to a selection level of the selection control signal; and a deactivation level in response to a non-selection level. The current
And a second MOS transistor of the constant current source circuit for supplying the second bipolar transistor to the fourth bipolar transistor.
A second current switching type logic (CML) circuit for decoding and outputting an active level / inactive level in response to the code content of the partial code signal of the above, and a decoding output from the second current switching type logic (CML) circuit 2. The decoding circuit according to claim 1, wherein each of the 2 ^m selection control signals includes 2 ⁿ second logic circuit units each including a second output circuit for buffer-amplifying the 2 ^m selection control signals. 3. A fifth bipolar transistor, wherein the first output circuit includes a collector connected to a power supply having a predetermined potential and a base receiving the corresponding selection control signal, and one end of the fifth bipolar transistor being connected to the fifth bipolar transistor. A level shift element connected to the emitter of the transistor and outputting a level conversion signal of the selection control signal from the other end; and a gate electrode receiving the control signal, wherein the fifth bipolar transistor is responsive to an active level of the control signal. 3. The decoding circuit according to claim 2, further comprising a third MOS transistor serving as a constant current source that supplies a predetermined operation current of the level shift element. 4. The decoding circuit according to claim 3, wherein said level shift element is formed by a diode. 5. A base wherein said two output circuits receive a decode output from a second current switching logic (CML) circuit corresponding to a collector connected to a power supply having a predetermined potential and a buffer which is said decode output. A sixth bipolar transistor having an emitter for generating an amplified output, a gate electrode receiving a level conversion signal of the corresponding selection control signal, and an activation level and a non-selection level in response to a selection level of the selection control signal 3. The decoding circuit according to claim 2, further comprising: a fourth MOS transistor serving as a constant current source for supplying a current at an inactivation level to said sixth bipolar transistor. 6. A load element of the second current switching type logic (CML) circuit, comprising: a source electrode receiving a predetermined power supply potential at a source electrode; a gate electrode receiving a level conversion signal of the selection control signal corresponding to the source electrode; And a drain electrode connected to a collector of a fourth bipolar transistor, the decode signal being output from the drain electrode, and a fifth MOS transistor having a conductivity type different from that of the second MOS transistor. 2. The decoding circuit according to 2.