JPH01285090A - Bipolar cmos address selecting circuit - Google Patents

Abstract

PURPOSE:To speed up an address selecting operation and to reduce power consumption in an amplifying circuit by using the amplifying circuit by a current switching type logical circuit of series gate circuit structure. CONSTITUTION:The title circuit is equipped with a third level shift circuit 11a, a fourth level shift circuit lib, an amplifying circuit 12 to decode and amplify by the current switching type logical circuit of the series gate circuit structure, and a buffer circuit 13. In the bipolar CMOS address selecting circuit, an input signal of small amplitude at an ECL level is directly decoded and amplified by the amplifying circuit 12 of the bipolar transistor series gate circuit structure. Thus, the number of the stages of decoders at a MOS level can be decreased and a circuit in which the address selecting operation is speeded up can be obtained. The number of amplifying stages can be decreased, the number of amplifying circuits can be decreased and therefore, the power consumption in the amplifying circuit can be reduced.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a bipolar CMOS address selection circuit configured using a composite circuit of a CMOS circuit of bipolar transistors and field effect transistors, and in particular, A bipolar CMOS address selection circuit that decodes and amplifies the input signal of Q, 8V, low level knee 1.6V) and generates an address selection signal of IMOS level (high level B/Lz knee 0.OV, low level knee 3.OV). It is related to.

[Conventional technology]

Conventionally, the maximum address access time was bipolar ECL
As a large-capacity RAM that has both the speed of memory and the low power consumption of MOS memory, it uses bipolar elements and 0 MO
Bipolar C with 8 elements integrated on the same silicon chip
Memories based on MOS devices have been developed. Such bipolar CMOS memory is 1 e.g. Nikkei Electronics, 19g6.3.10 (no, 390)
, pp. 199-208, in a paper titled ``Bipolar CMOS RAMJ emerging as a high-speed, highly integrated memory.''

In this type of composite circuit of bipolar elements and 0MO8 elements, a level shift circuit is often used to match signal levels between the circuit using bipolar elements and the circuit using 0MO8 elements. In other words, the logic signal of the ECL level (high level knee 0.8V, low level knee 1.6V), which is the logic level of the circuit using bipolar elements, is
Level shift 1-circuits that convert into logic signals at MOS levels (high level knee O, OV, low level knee 5.2 V), which is the logic level of a circuit using MOS elements, are often used, or the circuit used includes a level shift circuit. It is assumed to have a circuit configuration based on circuits. As such a circuit, there is an address selection circuit as shown in FIG. 3, which converts an ECL level signal to a MOS level signal and decodes it.

This address selection circuit consists of a first level conversion circuit 1° amplifier circuit 2. Second level shift circuit 3. Each of the buffer circuit 4 and the decoding circuit 5 is sequentially connected in cascade,
This is a constructed circuit. The first level conversion circuit 1 is an emitter follower circuit whose output terminal is the anode of a diode D connected in series to the emitter of a bipolar transistor Q. The amplifier circuit 2 is a differential amplifier circuit including a pair of bipolar transistors Q, QJ connected to a constant current source. The second level shift circuit 3 is.

This is a current mirror type differential amplifier circuit using a pMOSMOS transistor T□ as a driving transistor.

The buffer circuit 4 is a CMOS transistor T.

This is a bipolar CMOS inverter circuit consisting of bipolar transistors Q, , and Qs. The decoding circuit 5 includes CMOS transistors T7. T.

T,,T,o and bipolar transistors Q,,Q
Bipolar CMOS NAND by 7
It is a circuit. These first level conversion circuits 1. Amplification circuit 2. Second level shift circuit 3. The power supply terminals of the buffer circuit 4 and the decoding circuit 5 have a high potential side connected to a power supply Vcc (0, OV), and a low potential side connected to a power supply V, . . . (-5, 2V).

[Problem to be solved by the invention]

By the way, in order to achieve high integration and high performance, M in an address selection circuit using a bipolar CMO3 as shown in FIG.
When realizing the OS transistor with a high-performance fine MOS transistor whose withstand voltage is -3.0V or less, the second
It is necessary to reduce the power supply voltage supplied to each circuit after the stage amplifier circuit 2 and operate the logic signal level of the MO1S level with the high level side set to O, OV and the low level side set to -3,0■. becomes. In this case, "(i) Since the configuration is such that the MOS level is realized by the amplifier circuit 2, the second level shift circuit 3 becomes unnecessary.

Therefore, with the configuration excluding the second level shift circuit 3,
It is necessary to match with the buffer circuit 4 at the next stage.

(ii) Furthermore, since an amplifier circuit is required for each manual bit, as the number of bits increases, power consumption increases.

(iii) Since the final stage decoding circuit 5 is composed of three CMO circuits, the delay time increases as the number of decodes increases. ” There were other problems.

The present invention has been made to solve the above problems.

An object of the present invention is to reduce the number of circuit stages in a bipolar CMOS address selection circuit and speed up the address selection operation. Another object of the invention is to provide bipolar CMO
The purpose of this invention is to reduce power consumption by reducing the number of amplifier circuits in the S address selection circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, in the present invention, a bipolar CMOS address selection circuit includes a level shift circuit that level-shifts an ECL level input signal to a lower level side by an emitter follower circuit, and a bipolar transistor that outputs the output of the level shift circuit. The circuit includes an amplifier circuit that performs decoding and amplification using a current switching type logic circuit having a series gate circuit configuration, and a buffer circuit that shapes the decoded output of the decode circuit.

[Effect]

According to the above means, the bipolar CMOS address selection circuit includes a level shift circuit, an amplifier circuit having a series gate circuit configuration, and a buffer circuit. The level shift circuit levels-shifts the ECL level input signal to a lower level side using an emitter follower circuit. The amplifier circuit is
The level-shifted ECL level logic signal is decoded and amplified by a current switching type logic circuit having a series gate circuit configuration of bipolar transistors. The buffer circuit also shapes the decoded output from the amplifier circuit. In this way, in the bipolar CMO 3 address selection circuit, a small amplitude input signal at the ECL level is received by an amplifier circuit having a series gate circuit configuration of bipolar transistors.
Directly decode and amplify. As a result, the number of decoder stages at the MOS level can be reduced, and a circuit that can speed up the address selection operation can be achieved. Furthermore, since the number of amplification circuits can be reduced by reducing the number of amplification stages, power consumption in the amplification circuits can be reduced.

〔Example〕

An embodiment of the present invention will be specifically described below with reference to the drawings.

In addition, in all the figures for explaining the embodiment, the same elements are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 1 shows a bipolar CMO according to an embodiment of the present invention.
FIG. 3 is a circuit diagram showing the configuration of a 2-bit decoder of the 3rd address selection circuit. In FIG. 1, 11a is a third level shift circuit, llb is a fourth level shift circuit, 12 is an amplifier circuit having a series gate circuit configuration and decodes and amplifies using a current switching type logic circuit, and 13 is a buffer circuit. . This 2-bit decoder is a circuit that decodes input signals A, , A□ and generates decoded outputs C6-C5.

The third level shift circuit 11a is composed of an emitter follower circuit in which a bipolar transistor Q and diodes D, D4 are connected in series.

Further, the fourth level shift circuit 11b includes a bipolar transistor Q and diodes D, D in series.

It consists of an emitter follower circuit connected to

The third level shift circuit 11a receives the input signal A by using the cathode of the diode D as an output terminal. The level shift amount is adjusted to the signal level required for the upper stage gate of the amplifier circuit 12 of the subsequent series gate circuit configuration. Further, the third level shift circuit 11b includes a diode D,
By using the cathode of the input signal as an output terminal, the level shift amount of the input signal is adjusted to the signal level required for the lower gate of the amplifier circuit 12 of the series gate circuit configuration in the subsequent stage.

The amplifier circuit 12 is composed of a series gate circuit including an upper gate and a lower gate. The output signal of the third level shift circuit 11a is applied to the bases of the upper gate bipolar transistors Q1° and Q□2, and the bipolar transistors Q1° and Q□2 are connected to the bases of the bipolar transistors Q1° and Q□2.

The reference voltage (-1
, 3V) level-shifted first reference voltage V Rts
r, (-2-9V) is applied. At the base of the lower gate bipolar transistor, there is a fourth
The output signal of the level shift circuit 11b is applied to the base of the bipolar transistor circuit, and a second reference voltage is applied to the base of the bipolar transistor circuit 11b, which is obtained by level-shifting the reference voltage by the level-shift voltage level-shifted by the fourth level shift circuit 11b. A voltage V 11 E F□ (-3.7V) is applied.

In addition, bipolar transistor technology is used at the upper gate. ~Q1. A resistor R4 is connected between the collector of each and the high potential side power supply terminal. Decode output B from the connection point between each collector and resistor R4. -B is taken out. The buffer circuit 13 is composed of a CMOS inverter or a bipolar CMOS inverter, and converts the decoded outputs B, ~B3 from the amplifier circuit 12 having a series gate circuit configuration into MO8L/bell (high level: O, OV,
Low level knee 3. OV) is converted into signals 00 to C3 and output.

The operation of the 2-bit decoder configured in this way will be explained. Here, the ECL level input signal A0
．． The operation when both A□ are at high level (-0, 8V) will be explained. The operation in other cases is similar.

The input signal A at the ECL level is generated by the third level shift circuit 11a and the fourth level shift circuit 11b. .

A, are A0'(-2,4V) and A,'(-3V), respectively.
, 2V). At the lower gate of the amplifier circuit 12 having the series gate circuit configuration, the level-shifted input signal A1' (-3, 2V) becomes higher than the second reference voltage V, , F, (-3, 7V), so that Bipolar transistor Q with current switching type logic operation
It's conductive. Furthermore, at the upper gate of the amplifier circuit 12 having the series gate circuit configuration, the level-shifted input signal A0' (-2, 4V) is applied to the first reference voltage V□yx.
c 2-9V), the bipolar transistor Q□ by current-switched logic operation. is conductive. At this time, other transistors, ~Q
Since no current flows through 13, only the decode output B0 becomes a low level, and the other decode outputs B, ~B3 become a high level. In this way, decode output B. Only the signal becomes low level, and a decode output signal for performing a selection operation is obtained. In the amplifier circuit 12 having the series gate circuit configuration, current flows only through one selected transistor, so the resistor R4 is adjusted so that the low level logic output is approximately -2.4V. Thereby, the output of the amplifier circuit 12 can directly drive the inverter of the buffer circuit 13, the inverter of the buffer circuit 13 can generate a MOS level logic signal, and the high level output c0 is selected.

In this way, in the 2-bit decoder with the circuit configuration of this embodiment.

(i) Since the inverter can be connected directly to the rear stage of the amplifier circuit 12 with the series gate circuit configuration, the second level shift circuit is not required, and only the second level shift circuit stage can be made faster.

(n) If the current value of the current source I2 required in the amplifier circuit 12 of the series gate circuit configuration is set to the same value as the current value of the current source 11 of the amplifier circuit 2 (Fig. 3), the current value required for 2-bit decoding is Since the current value of the current source 2 of the amplifier circuit 12 is 1/2 per bit, power consumption can be reduced to about 1/2.

(City) Also, since decoding at the MOS level is not required, the speed can be increased by the number of circuit stages of the decoder at the MOS level. For example, a submicron bipolar C with an effective channel length of MO3+- transistor of 1.0 μm or less.
When implemented using a MOS process, the time required to reach the decoder can be reduced by 20%. ” and other advantages.

FIG. 2 shows a bipolar CM according to another embodiment of the present invention.
FIG. 3 is a circuit diagram showing the configuration of a 3-bit decoder of the OS address selection circuit. This 3-bit decoder consists of the 2 bits shown in Figure 1.
A bit decoder is used as a part of the circuit element. The outputs from the 2-bit decoder 21 and the complementary signal generation circuit 22 are logically processed by the decoder circuit 23 to generate 3 bits.
It has a circuit configuration that performs bit decoding. The complementary signal generation circuit 22 here uses an input signal A2 at the ECL level.
MOS level complementary signal B4. This is a circuit that generates B. The complementary signal generation circuit 22 includes a fifth level shift circuit 22a, an amplification circuit 22b including a bipolar differential amplification circuit, and a buffer circuit 22c. The fifth level shift circuit 22a has a similar configuration to the third level shift circuit 11a (FIG. 1). The amplifier circuit 22b has a similar configuration to the amplifier circuit 2 (FIG. 3). Further, the buffer circuit 22c is a circuit having a similar configuration to the buffer circuit 13 (FIG. 1), and is a circuit configured with a CMOS inverter or a bipolar CMOS inverter. The decoding circuit 23 has eight NANDs (
It consists of a NAND) circuit. Decode circuit 23
Each NAND circuit outputs a decode output B from the 2-bit decoder 21. -B, and the MO of the complementary signal generation circuit 22.
S level complementary signal B4. B, and 2 each.
Takes bit logic and outputs 3-bit decode 00~C7
Output.

In the 3-bit decoder of the other embodiment shown in FIG. The speed can be increased to the extent that the level shift circuit 3 (FIG. 3) of No. 2 is unnecessary.

(n) If the current value required for the amplifier circuit 12 with a series gate circuit configuration and the amplifier circuit 22b with a bipolar differential amplifier circuit is set to be the same as the current value of the current source ■1 of the amplifier circuit 2 (Fig. 3). , the current value of the amplifier circuit required for 3-bit decoding is 2/3, so power consumption can be reduced to about 2/3.

(■) Also, since the decoder circuit can be implemented with a 2-bit NAND circuit, it can operate at higher speeds than a 3-bit NAND circuit. For example, if the effective channel length of the MOS transistor is realized by a submicron bipolar CMOS process of 1.0 μm or less, the time required for decoding can be reduced by about 10%. ” and other advantages.

Although MOS transistors are used in the embodiments described above, an address selection circuit with a similar circuit configuration can be constructed using other types of field effect transistors.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As explained above, according to the present invention, bipolar C
In the MO3 address selection circuit, the input signal is directly amplified and decoded using an amplifier circuit based on a current switching type logic circuit with a series gate circuit configuration as an amplifier circuit, so the number of decoding stages at the MOS level can be reduced. , the circuit configuration can be simplified and the address selection operation can be made faster. Furthermore, since the number of amplifier circuits can be reduced, power consumption in the amplifier circuits can be reduced.

[Brief explanation of the drawing]

FIG. 1 shows a bipolar CMO according to an embodiment of the present invention.
FIG. 3 is a circuit diagram showing the configuration of a 2-bit decoder of the S address selection circuit. FIG. 2 shows a bipolar CM according to another embodiment of the present invention.
A circuit diagram showing the configuration of an OS address selection circuit 3-bit decoder. FIG. 3 is a circuit diagram showing an example of a conventional bipolar CMOS address selection circuit. In the figure, 1... first level shift circuit, 2... amplifier circuit, 3... second level shift circuit, 4... buffer circuit, 5... decoding circuit, lla... Third level shift circuit, llb...Fourth level shift circuit, 12...Amplification circuit with series gate circuit configuration, 1
3... Buffer circuit, 21... 2-bit decoder,
22... Complementary signal generation circuit, 22a... Fifth level shift circuit, 22b... Amplifying circuit, 22c... Buffer circuit, 23... Decoding circuit (two-man NAND
circuit).

Claims (1)

[Claims] (1) A level shift circuit that levels-shifts an ECL level input signal to a lower level side using an emitter follower circuit, and the output of the level shift circuit is decoded and amplified by a current switching type logic circuit configured as a series gate circuit of bipolar transistors. 1. A bipolar CMOS address selection circuit comprising: an amplifier circuit for shaping the decoded output of the amplifier circuit; and a buffer circuit for shaping a decoded output of the amplifier circuit.