JP2785289B2 - Current switching type logic circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a current switching type logic circuit.

[Conventional technology]

With the widespread use of logic circuits, high-speed and stable operation has become increasingly important.

FIG. 4 is a circuit diagram of an example of a conventional current switching type logic circuit.

Current switching type logic circuit receives an input voltage upsilon ₁ to the base B _1, receives the reference voltage V _R to the base B _2, each emitter
Constant-current power supply E ₁ and E ₂ via an emitter resistor r ₁ and r ₂
Connected in common to io, each collector C ₁ and C ₂ constitute a differential circuit of npn transistors Q ₁ and Q ₂ which commonly connected to the power supply of the collector source voltage Vcc via load resistors R ₃ and R ₄ ing.

Here it is generally emitter resistance r ₁ and r ₂ are 0 .OMEGA, resistance r ₁ and a suitable value as a measure to improve the circuit operation speed
r ₂ may be added.

5 and 6 are a transfer characteristic diagram and an input / output voltage waveform diagram for explaining the operation of the circuit of FIG.

As shown in FIG. 5, when the values of the emitter resistors r ₁ and r ₂ are equal, the input / output transfer characteristic indicates a characteristic curve a if the resistance value is small, and a characteristic curve b if the resistance value is large.

The input voltage υ _i is at the operating point X of the characteristic curve a at the “L” level, and as the voltage increases, the output voltage υ o passes through the unity gain points U _AL , the middle points M and U _AH of the AC gain 1 to the operating point Y. Move on.

 The same applies to the characteristic curve b.

The input voltage widths between these unity gain points are A and B, respectively.

Change in the output voltage υo respond to changing from "L" level to the "H" level of the input voltage upsilon _i, if the collector parasitic capacitance C _S shown by the broken line in FIG. 4 is zero found the following characteristic curve _a It quickly reaches the “ _H ” level.

However, as shown in FIG. ₆ , when the time constant τ _S determined by the product of the collector parasitic capacitance _CS and the load resistance R ₄ is larger than the rise time τ _R of the input voltage _{ｉ i} , for example, the characteristic curve The output voltage _{OA OA} of “a” is “H” as compared with the output voltage υ _OB of the characteristic curve B by the difference τ _L between the respective rise delay times τ _dA and τ _dB.
The point in time t _AH at which the level is reached is later than the hour and minute t _BH .

For example, when the rise time τ _R of the input voltage υ _i is 1 μs and the unity gain point width B is 0.6 V, this state is established if the time constant τ _S is 0.33 μs or more.

Therefore, in order to increase the speed, the emitter delay is increased and the rise delay time τ _dB is reduced using the characteristic curve b.

[Problems to be solved by the invention]

In the above-described conventional current switching type logic circuit, when the emitter resistance value is increased to increase the speed, the input / output transfer characteristics gradually change to a stable level of "H" or "L". However, there is a drawback that there are many malfunctions due to the noise of the logic signal because of the approach.

That is, for example, in the case of the characteristic curve b in FIG.
The operating point falls within the unity gain point width B even when a small positive noise is superimposed, and the inversion malfunction is easier than in the case of the characteristic curve a.

 Therefore, speeding up and noise margin were not compatible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a current switching type logic circuit which is high speed and has a large noise margin.

[Means for solving the problem]

A current switching type logic circuit according to the present invention includes a first transistor receiving an input voltage at a base (gate), a second transistor receiving a reference voltage at a base (gate), and each of the first and second transistors. An emitter (source), a constant current power supply, and a resistance connected between the power supply and the first current source;
First and second variable resistance sections controlled to be variable by respective collector (drain) voltages of the second and second transistors, and the first and second collector (drain) sections
And a load resistor respectively connected between the first and second transistors, and a differential circuit using one or both voltages of the collectors (drain) of the first and second transistors as an output voltage; A resistance control unit that controls so that when the collector (drain) voltage of each of the first and second transistors increases (decreases), the resistance value of each of the first and second variable resistance units decreases (increases); It is configured.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of one embodiment of the present invention.

Current switching type logic circuit, the emitter resistance r ₁ and of FIG. 4
It provided a variable resistor portion 2 _A and 2 _B instead of r _2, the control voltage to the resistor portion 2 _A and 2 _B respectively corresponding to input collector voltage υ
It is the same as a conventional current switching type logic circuit except that it has a resistance control unit 1 for supplying _S.

Resistance here variable resistance part 2 _A output voltage υo generated at the output terminal To is increased when the high level "H", the output voltage is controlled so as to decrease at a low level "L".

On the other hand the resistance value of the variable resistor portion 2 _B is controlled to a value opposite to the direction of the resistor section 2 _A.

FIG. 2 is a transfer characteristic diagram for explaining the operation of the block shown in FIG.

First, the resistance of the variable resistor 2 _A resistance value of r _A resistor unit 2 _B r _B
In this case, the input / output transfer characteristic can be expressed by the following equation (1).

Here, Δυ: potential difference between input voltage υ _i and reference voltage V _R K: Portsman constant T: absolute temperature e: electron charge: _L : low-level output voltage υ _O : output voltage I _C : constant current source current The first term in (1) shows the transfer characteristic when the emitter resistance of the npn transistors Q ₁ and Q ₂ does not exist at all, and the change in the transfer characteristic with respect to the resistances r _A and r _B is the second term. Good.

First, the second term of equation (1) becomes a (2) when the output voltage upsilon _O is equal to the low level output voltage upsilon _L.

Δυ ′ = − I _C · r _B (2) Accordingly, the transfer characteristic in this case is determined by the resistance value r _B.

On the other hand, the transfer characteristic from the variable resistor portion 2 _B is controlled such that a high resistance by the resistance control circuit 1 becomes a characteristic close to the characteristic curve b described in FIG. 5 above.

Next, where the input voltage upsilon _i rises from the low level "L" corresponding to the operating point X, the output voltage upsilon _O rises along a characteristic curve b of FIG. 5.

In this case, the variable resistor portion 2 _B approaches characteristic curve a of Figure 5 the resistance value with the increase in the output voltage upsilon _O decreases.

Furthermore the high level output voltage upsilon _O corresponds to the operating point Y "H"
That is, it approaches the collector power supply voltage V _CC and the potential difference is almost 0 V
Then, the second term of Expression (1) becomes Expression (3).

_{Δυ '= I C · r A} ... (3) That is, the resistance value r _A of the transmission characteristic is resistance unit 2 _A in this vicinity
Is determined by

Since this time the variable resistor portion 2 _A is a high resistance by the resistance control circuit 1, the characteristic curve b shown in FIG. 5 again.

As described above, the output voltage upsilon _O variable resistor section 2 _A and 2 _B in the intermediate operating point M near the output voltage upsilon _O is "H" or "L" level to lower than when the intermediate operating point M The transfer characteristic in the vicinity becomes steep as in the case where the emitter resistance is small.

On the other hand, the transfer characteristic near the high level “H” becomes low like the case where the emitter resistance is high near the low level “L”.

That is, at the beginning of the transition from the "H" or "L" level of the input / output voltage, the output voltage changes from the operating point X or Y of the characteristic curve b shown by the broken line in FIG. _{As O} approaches the intermediate operating point M, it approaches a characteristic curve a shown by a dotted line when a low resistance is used as the emitter resistance.

As a result, the transfer characteristic of this current switching type logic circuit is
The characteristic is shown by the characteristic curve e in the figure.

Therefore, in the embodiment, the characteristic at the time of high emitter resistance corresponds to the input voltage υ _i , the rising delay time of the output voltage υ _O is shortened, the high speed characteristic is obtained, and the characteristic curve is obtained for the noise overlapping the logic signal. The unity gain point width E having a small e corresponds to preventing malfunction.

 FIG. 3 is a circuit diagram of FIG.

The variable resistance sections 2 _A and 2 _B are n-channel MOS transistors M ₁
And has a M _2, is applied to the gates of the transistors M ₁ and M ₂ output voltage upsilon _O via the emitter floor circuit according npn transistors Q ₃ and Q ₄ of the resistance control unit 1,
The on-resistance between the drain and the source is controlled.

When the transistor Q ₁ is the base voltage or output voltage v _O of the transistor Q ₄ in the on state is "H" level, the drain-source resistance of the MOS transistor M ₂ is a low resistance.

On the other hand since the emitter of the transistor Q ₃ are is "L" level, the drain-source on-resistance of the MOS transistor M ₁ becomes high resistance.

 That is, the above-described circuit operation is performed.

Here has been described the example of using a bipolar transistor as the transistor Q ₁ to Q _4, the same effect can be obtained by using the n-channel MOS transistors instead.

The resistance control unit 1 output voltage upsilon _O and transistor
Although enter both the collector voltage of Q _1, both voltages may control the gates of the MOS transistors by generating a reverse-phase voltages by entering one of the voltages so reversed phase.

〔The invention's effect〕

As described above, in the current switching type logic circuit according to the present invention, by providing the variable resistor controlled between the emitter (source) of the current switching transistor and the constant current power supply according to the output voltage value, At the initial stage of the voltage change, the same operating speed can be expected as when a high resistance is inserted into the emitter, and near the intermediate operating point, the emitter resistance decreases and the transmission characteristic becomes sharp, resulting in noise for the logic signal. This has the effect of keeping the margin high.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram of FIG. 1, FIG. 4 is a circuit diagram of an example of a conventional current switching type logic circuit, FIG. 5 and FIG. 4A and 4B are a transfer characteristic diagram and an input / output voltage waveform diagram for explaining the operation of the circuit of FIG. 4. 1 ... resistance control section, 2 _A , 2 _B ... variable resistance section, _IO ... constant current power supply, M ₁ , M ₂ ... MOS transistor, Q _{1 to} Q ₄ ... 1st to 1st
Fourth npn transistor, V _CC ...... Collector power supply voltage, υ
_i: Input voltage, υ _O output voltage, υ _R: Reference voltage, υ
_{S ......} control voltage, R _1, R ₂ ...... load resistor.

Claims (3)

(57) [Claims] 1. A first circuit receiving an input voltage at a base (gate).
, A second transistor having a base (gate) receiving a reference voltage, emitters (sources) of the first and second transistors, a constant current power supply, and resistances connected between the first and second transistors, respectively. A first and second variable resistance unit controlled to be variable by each collector (drain) voltage of the second transistor; and a first power supply between the first and second collectors (drain) and the DC power supply. A load resistor connected to each of the first and second
And a differential circuit that uses one or both voltages of the collectors (drains) of the transistors as output voltages, and when the collector (drain) voltages of the first and second transistors increase (decrease), A current control type logic circuit, comprising: a resistance control section for controlling each resistance value of the second variable resistance section to decrease (increase). 2. The resistance control section connects each base (gate) to each of the first and second collectors (drain).
2. The current switching logic circuit according to claim 1, further comprising third and fourth transistors that use each emitter (source) voltage as a control voltage for said first and second variable resistance units. 3. The first and second variable resistance sections have respective sources and respective drains connected between respective emitters (sources) of the first and second transistors and the constant current power supply, respectively. First and second variable resistance MOs that input the control voltage to each gate and vary the resistance value by ionic resistance
3. The current switching type logic circuit according to claim 2, further comprising an S transistor.