JP2780567B2 - Integrated circuit power supply - Google Patents
Integrated circuit power supplyInfo
- Publication number
- JP2780567B2 JP2780567B2 JP4152891A JP15289192A JP2780567B2 JP 2780567 B2 JP2780567 B2 JP 2780567B2 JP 4152891 A JP4152891 A JP 4152891A JP 15289192 A JP15289192 A JP 15289192A JP 2780567 B2 JP2780567 B2 JP 2780567B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- integrated circuit
- switch element
- detection circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【０００１】[0001]
【産業上の利用分野】この発明は、動作中の集積回路
（以下、ＩＣという）が電源回路に静電ノイズ等を受け
てラッチアップし、異常動作することとなっても、上記
静電ノイズがなくなれば再び上記集積回路を正常に回復
させる給電回路に関するものである。BACKGROUND OF THE INVENTION The present invention relates to an integrated circuit (IC) that is operating and operates abnormally even if the integrated circuit (hereinafter referred to as IC) latches up due to electrostatic noise or the like in a power supply circuit and operates abnormally. The present invention relates to a power supply circuit for restoring the integrated circuit to a normal state when the power supply disappears.
【０００２】[0002]
【従来の技術】周知のように、ＣＭＯＳなどのＩＣで
は、電源端子に過大な静電ノイズなどの外乱ノイズを受
けると、このＩＣの電源，接地間に過大な電流が流れ、
この電流は電源を切らない限り流れ続け、ＩＣを劣化さ
せるほか、最悪時には破損に至らしめる。このため、従
来は、その外来の入力回路中にノイズ除去のフィルタを
設ける等の対策をしているが、外乱の高圧パルスをすべ
てフィルタで除去することは難しく、また、このフィル
タの破損や劣化などもある。従って、その異常状態を自
動的に回復することができないという不都合があった。2. Description of the Related Art As is well known, when an external noise such as an excessive electrostatic noise is applied to a power supply terminal of an IC such as a CMOS, an excessive current flows between the power supply and ground of the IC.
This current continues to flow unless the power is turned off, deteriorating the IC, and at worst, causing damage. For this reason, conventionally, measures have been taken, such as providing a noise removal filter in the external input circuit.However, it is difficult to remove all of the high-voltage pulses due to disturbances. There are also. Therefore, there is a disadvantage that the abnormal state cannot be automatically recovered.
【０００３】[0003]
【発明が解決しようとする課題】この発明は上記のよう
な従来の問題点に着目してなされたものであり、静電ノ
イズの到来により、一旦ラッチアップしたＩＣを正常に
回復させて、正規に該ＩＣを動作可能にする集積回路の
給電装置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and it has been found that, due to the arrival of electrostatic noise, an IC that has been once latched up can be recovered normally, It is another object of the present invention to provide an integrated circuit power supply device that enables the IC to operate.
【０００４】[0004]
【課題を解決するための手段】この発明に係る集積回路
の給電装置は、直流電源から第１のスイッチ素子を介し
て電源の供給を受ける集積回路群において、前記直流電
源の電源電圧の検出回路と、前記第１のスイッチ素子の
ベース端子と前記検出回路の出力端の間に接続された第
２のスイッチ素子とを具備し、前記検出回路の出力が設
定値以下のとき第１のスイッチ素子をオフとし、前記集
積回路群への電源の供給を遮断することを特徴とする。A power supply device for an integrated circuit according to the present invention is a circuit for detecting power supply voltage of a DC power supply in an integrated circuit group supplied with power from a DC power supply via a first switch element. And a second switch element connected between a base terminal of the first switch element and an output terminal of the detection circuit, wherein the first switch element is provided when an output of the detection circuit is equal to or less than a set value. And turning off the power supply to the integrated circuit group.
【０００５】[0005]
【作用】この発明によれば、集積回路のいづれか一つが
ラッチアップすれば、検出回路が電源電圧の低下を検知
して、上記第１のスイッチ素子がオフとなり、集積回路
に対する電源電圧の供給を遮断する。これによってラッ
チアップはなくなる。ラッチアップしてから電源を遮断
するまでの時間が短いので、集積回路は殆ど回復するこ
とができる。According to the present invention, if any one of the integrated circuits latches up, the detection circuit detects a drop in the power supply voltage, the first switch element is turned off, and the supply of the power supply voltage to the integrated circuit is stopped. Cut off. This eliminates latch-up. Since the time between latch-up and power-off is short, the integrated circuit can be almost recovered.
【０００６】[0006]
【実施例】以下に、この発明の一実施例を図について説
明する。図１において、１は集積回路であり、ここでは
ＣＰＵである。２はこのＣＰＵ１に対する電源電圧の供
給をオン，オフ制御する第１のスイッチ素子としてのＰ
ＮＰタイプのトランジスタ、３は電源回路に入れられた
サージ吸収を兼ねる電圧平滑用のインダクタ、４はイン
ダクタ３及び抵抗５を介して電源回路の電圧、つまりＣ
ＰＵの電源電圧を検出する検出回路（ＩＣ）である。こ
こではリセットＩＣ（ＣＭＯＳ）でよい。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 denotes an integrated circuit, here, a CPU. Reference numeral 2 denotes a P as a first switch element for controlling the supply of the power supply voltage to the CPU 1 on and off.
An NP-type transistor 3 is a voltage smoothing inductor which also serves as a surge absorber and is provided in the power supply circuit, and 4 is a voltage of the power supply circuit via the inductor 3 and the resistor 5, that is, C
A detection circuit (IC) for detecting a power supply voltage of the PU. Here, a reset IC (CMOS) may be used.
【０００７】また、６は検出回路ＩＣ４の出力側に抵抗
７を介してベースが接続された第２のスイッチ素子とし
てのＮＰＮタイプのトランジスタで、このトランジスタ
６のエミッタは接地され、また、コレクタは、エミッタ
及びコレクタが上記電源回路の途中に接続された上記ト
ランジスタ２のベースに、抵抗８を介して接続されてい
る。Reference numeral 6 denotes an NPN-type transistor as a second switch element having a base connected to the output side of the detection circuit IC4 via a resistor 7, the emitter of the transistor 6 being grounded, and the collector being connected to the collector. , An emitter and a collector are connected via a resistor 8 to the base of the transistor 2 connected in the middle of the power supply circuit.
【０００８】また、検出回路ＩＣ４の出力は抵抗９及び
コンデンサ１０からなる平滑回路を介して、ＣＰＵ１の
リセット入力端子に供給されるような接続となってい
る。The output of the detection circuit IC4 is connected to a reset input terminal of the CPU 1 via a smoothing circuit including a resistor 9 and a capacitor 10.
【０００９】次に動作について説明する。まず、電源電
圧が正常に維持されている場合には、直流電源の電源電
圧（ＶDD）がトランジスタ２を介してＣＰＵ１に供給さ
れる。すなわち、この状態では、検出回路ＩＣ４の出力
が“Ｈ”となり、従って、トランジスタ６，２がそれぞ
れオンになり、ＣＰＵ１に正規の電源電圧が供給され、
所期の動作を行う。Next, the operation will be described. First, when the power supply voltage is normally maintained, the power supply voltage (V DD ) of the DC power supply is supplied to the CPU 1 via the transistor 2. That is, in this state, the output of the detection circuit IC4 becomes "H", so that the transistors 6 and 2 are turned on, and the normal power supply voltage is supplied to the CPU 1.
Perform the intended operation.
【００１０】一方、上記のような、正規の動作を行って
いるＣＰＵ１に対して、静電ノイズなどによるサージ電
圧が、トランジスタ２を介して供給されると、このＣＰ
Ｕ１はラッチアップ状態となることがあり、この場合に
は、ＣＰＵ１において電源とアースが導通状態となり、
上記電源回路の電位が大きく低下することになる。On the other hand, when a surge voltage due to electrostatic noise or the like is supplied via the transistor 2 to the CPU 1 which is performing a normal operation as described above, this CP 1
U1 may be in a latch-up state. In this case, the power supply and the ground become conductive in CPU1,
The potential of the power supply circuit is greatly reduced.
【００１１】このため、検出回路ＩＣ４はこの状態を検
出して出力が“Ｌ”となり、従って、トランジスタ６，
２がオフとなって、ＣＰＵ１への電源供給を遮断すると
共に、ＣＰＵ１にはリセットがかかることになる（ラッ
チアップ解除）。このため、このＣＰＵ１のラッチアッ
プが継続することによる破壊やＣＰＵ１による被制御手
段の誤動作を未然に回避できることになる。As a result, the detection circuit IC4 detects this state and the output becomes "L".
2 is turned off, the power supply to the CPU 1 is cut off, and the CPU 1 is reset (latch-up release). Therefore, destruction due to the continued latch-up of the CPU 1 and malfunction of the controlled means by the CPU 1 can be avoided.
【００１２】また、上記サージ電圧の発生が止んだ場合
には、検出回路ＩＣ４はこれを検出して、トランジスタ
６，２をそれぞれ直ちにオンにし、電源電圧をＣＰＵ１
に供給することになる。このため、このＣＰＵ１は再び
正常な動作を回復することになる。When the generation of the surge voltage is stopped, the detection circuit IC4 detects this and immediately turns on the transistors 6 and 2, respectively, and reduces the power supply voltage to the CPU1.
Will be supplied to Therefore, the CPU 1 recovers the normal operation again.
【００１３】尚、電源投入時は、検出回路ＩＣ４のスレ
ッショルド電圧以上で、これの出力が“Ｈ”であるた
め、トランジスタ２，６がオンとなり、ＣＰＵ１に給電
されると共に、上記スレッショルド電圧以上で上記平滑
回路を介してリセットがかけられることになる。このと
き、検出回路ＩＣ４はこのような通常のリセット出力
と、上記異常時のリセット出力とに兼用されることにな
る。When the power is turned on, the output of the detection circuit IC4 is higher than the threshold voltage of the detection circuit IC4, and the transistors 2 and 6 are turned on to supply power to the CPU 1. Reset is performed via the smoothing circuit. At this time, the detection circuit IC4 is used for both the normal reset output and the reset output at the time of the abnormality.
【００１４】[0014]
【発明の効果】以上のように、この発明によれば直流電
源からスイッチ素子を介して電源の供給を受ける集積回
路群において、検出回路に上記集積回路群に対する電源
電圧を検出させ、その検出電圧レベルが設定値以下のと
き、上記スイッチ素子をオフにし、電源の供給を遮断さ
せるような構成としたので、静電気ノイズなどの外来ノ
イズによって上記ラッチアップ集積回路が破壊されるの
を未然に防止でき、上記外来ノイズがなくなった後は、
前記ラッチアップ集積回路を正常に回復させて、再び正
規に動作できるという効果が得られる。As described above, according to the present invention, in an integrated circuit group supplied with power from a DC power supply via a switching element, a detection circuit detects a power supply voltage for the integrated circuit group, and the detected voltage is detected. When the level is equal to or lower than the set value, the switch element is turned off and the power supply is shut off, so that the latch-up integrated circuit can be prevented from being destroyed by external noise such as electrostatic noise. After the external noise has disappeared,
The effect is obtained that the latch-up integrated circuit can be restored to normal and operate normally again.
【図１】この発明の一実施例による集積回路の給電装置
を示す回路図である。FIG. 1 is a circuit diagram showing a power supply device for an integrated circuit according to an embodiment of the present invention.
１ 集積回路（ＣＰＵ） ２ 第１のスイッチ素子（トランジスタ） ４ 検出回路（ＩＣ） ６ 第２のスイッチ素子（トランジスタ） Reference Signs List 1 integrated circuit (CPU) 2 first switch element (transistor) 4 detection circuit (IC) 6 second switch element (transistor)
Claims (1)
て電源の供給を受ける集積回路群において、 前記直流電源の電源電圧の検出回路と、前記第１のスイ
ッチ素子のベース端子と前記検出回路の出力端の間に接
続された第２のスイッチ素子とを具備し、前記検出回路
の出力が設定値以下のとき第１のスイッチ素子をオフと
し、前記集積回路群への電源の供給を遮断することを特
徴とする集積回路の給電装置。An integrated circuit group that receives power supply from a DC power supply via a first switch element, wherein a power supply voltage detection circuit of the DC power supply, a base terminal of the first switch element, and the detection circuit A second switch element connected between the output terminals of the first and second circuits, and when the output of the detection circuit is equal to or less than a set value, the first switch element is turned off, and the supply of power to the integrated circuit group is cut off. A power supply device for an integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4152891A JP2780567B2 (en) | 1992-05-20 | 1992-05-20 | Integrated circuit power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4152891A JP2780567B2 (en) | 1992-05-20 | 1992-05-20 | Integrated circuit power supply |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05326825A JPH05326825A (en) | 1993-12-10 |
| JP2780567B2 true JP2780567B2 (en) | 1998-07-30 |
Family
ID=15550389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4152891A Expired - Fee Related JP2780567B2 (en) | 1992-05-20 | 1992-05-20 | Integrated circuit power supply |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2780567B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3429213B2 (en) | 1999-02-26 | 2003-07-22 | シャープ株式会社 | Integrated circuit |
-
1992
- 1992-05-20 JP JP4152891A patent/JP2780567B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05326825A (en) | 1993-12-10 |
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