JP2777149B2 - Design change method of integrated circuit layout - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a layout design changing method in an automatic integrated circuit placement / wiring system using a computer.

(Prior Art) Automatic layout / wiring systems using computers are widely used for layout design of large-scale integrated circuits. When the layout by this system is completed, the layout result is verified, for example, whether the connection is correct, whether the design satisfies the design standards, and whether the predicted circuit characteristics satisfy the specifications. These verification tasks consume a lot of computer and designer resources. However, after or during the verification work,
In many cases, a system design (including functional design and logical design) side, which is the first half of the design process, receives a notification to change circuit connections. Usually, the relationship between the system design and the layout design of an integrated circuit often proceeds in parallel as shown in FIG. 4, and the layout design receives an instruction for design change from the system design during the verification work. There are many cases. Under these circumstances, how to efficiently reflect the request for design change that occurred on the system design side in the layout design result, how to minimize the effect on the layout result after verification work, and change the layout Is a problem. In particular, the addition of a new cell is a problem.

Conventionally, several schemes for performing such a layout design change have been implemented. The most common approach is
This is a method of manually correcting the layout result using a graphic editor or the like. However, this method requires a great deal of effort by the layout designer. Further, since the correction is performed manually, there is a high possibility that the result will include an error. Another method is to use connection information as a result of a system design change and to perform automatic placement and wiring from the beginning again ignoring all existing layouts. However, this method has a problem that all evaluations and verifications performed on the results of the previous layout design are attributed to water bubbles.

(Problems to be Solved by the Invention) As described above, in the conventional automatic placement and routing system for integrated circuits, it is possible to quickly and efficiently cope with a correction request from the system design side generated after the layout design is completed. There was no problem.

An object of the present invention is to provide a layout design change method in an integrated circuit automatic layout system that can solve such a problem and automatically perform a layout design change corresponding to a circuit change on the system design side. With the goal.

[Constitution of the Invention] (Means for Solving the Problems) In the present invention, a cell is added (including replacement) to modify the layout of an integrated circuit already designed by an integrated circuit layout system with a circuit change. In this case, a cell is added at or near a position where a predetermined evaluation function determined from a connection relationship between a cell to be added and a cell already laid out is minimized.

(Operation) According to the present invention, the position of a cell to be added is automatically determined based on an evaluation function that takes into account the connection relationship between the cell and the already-placed cell, so that the layout can be changed quickly. . In addition, since the layout result is not wasted and no manual operation is used, the probability of an error occurring in the correction is small. If a cell cannot be placed at a position where the evaluation function is minimized, placing it in a region near the cell can sufficiently cope with a desired circuit change.

If there is no gap at the position where the cell to be added is placed, the existing cell in the vicinity is once peeled off to make it unplaced, and the cell to be added is first placed with priority. In this case, how to select a cell to be unplaced (in some cases, a set of a plurality of cells) has a great influence on whether or not a design change can be efficiently implemented with a minimum change to the original design. . Therefore, in this case, it is effective to evaluate the efficiency of the change and the possibility of the minimum change for all of the conceivable unplaced cell candidates, to determine the priority, and to try. In addition, when there are a plurality of unarranged cell candidates, the next cell to be arranged becomes smaller, so that the possibility of rearrangement increases, and the possibility that the convergence of the process becomes faster is large.

Further, by performing the cell replacement operation, it becomes necessary to add a cell again. However, by repeating the same processing, there is a possibility that the cell can be rearranged without performing the unplacement. However, in an integrated circuit with a small unused area, it may take an impractical time to find a void in a cell. In such a case, it is effective to seek the judgment of the layout designer. Therefore, it is preferable to limit the number of repetitions of the process by designating it.

Further, in the layout modification according to the present invention, in the cell replacement operation, the moving target is calculated using the same function as the evaluation function used in the automatic arrangement, which is useful for improving the automatic arrangement.

(Embodiment) In the embodiment of the present invention, a cell at or near an optimum position for adding a cell is peeled off, a cell to be added is provisionally placed there, and a cell that has been peeled off (not placed) is added. A basic processing procedure of recursively executing a process of adding a cell is used for the coded cell). If the recursive procedure succeeds, the cell is adopted. If the recursive procedure fails, the provisional arrangement is restored and the replacement process is performed for a new candidate.
This will be specifically described with reference to the drawings.

FIG. 1 is a flowchart showing a processing procedure of a layout design change according to one embodiment. In the process starting from ST0 in the figure, first, in step ST1, a check is performed for limiting a range to search for an empty area for cell arrangement.
The restriction method here is that, when a replacement trial is performed for each candidate, the replacement relationship in the trial forms a tree (search tree) in graph theory with each cell as the root.
For example, there is a method of limiting the height of the search tree.
If the limit is exceeded here, the process exits from this processing in step ST11. Within the limits,
Proceed to the next step 2ST.

In step ST2, the position (X _T , Y _T ) where the cell is added is calculated. As the position calculation method, here, the sum of the squares of the distance between the position of the cell to be added and the positions (xi, yi) of n other cells connected to this cell is used. Is used as an evaluation function, and (X _T , Y _T ) that minimizes this is calculated.

Next, in step ST3, the calculated position (X _T , Y _T )
Alternatively, it is checked whether or not there is a void area in which the cell is placed in the vicinity. This becomes clear by examining the relationship between the occupied area of the additional cell and the void area. If there is a void area where a cell can be placed, the cell is placed here in step ST31, and the process ends in step ST32.

If there is no gap, cells or a set of cells that can be unplaced at the designated position or in the vicinity thereof are enumerated in step ST4, and priorities are given to their trial order to make a list of unplaced candidates. This priority is given, for example, by giving priority to a cell having a smaller shape so that the unplaced cells can be easily rearranged after the placement.

Hereinafter, the candidate list created in step ST4 is repeatedly evaluated for evaluation. First, in step ST5,
It is checked whether or not the candidate list is empty, and if it is empty, there are no candidates of this level, so this level is ended in step ST51.

In step ST6, the cell at the head of the candidate list is unplaced. At the same time, a necessary part of the wiring connected to the cell is deleted. A cell to be added to the gap generated by the wiring deletion is put on trial. Although the target cell is saved by this processing, an unplaced cell is generated as a secondary effect, and this is processed in the next step.

That is, in step ST7, for the unplaced cells generated in the previous step, the previous processing procedure is recursively called to search for voids and perform cell placement. Here, if all the non-arranged cells are arranged, it is a success, so this is checked in step 8. If successful, the process is completed in step ST81.

If the current attempt fails, the associated unplaced cells and removed wiring are restored in step ST9 to prepare for a new candidate attempt.

FIG. 2 shows a specific example of the above-described processing procedure in terms of the level of cell movement. In this example, chip 21
Trying to add cell 22 to. As a result of the evaluation using the evaluation function, it is assumed that the optimal arrangement position of the cell 22 is the area 23 indicated by the broken line. Now, to place cell 22 in area 23,
Two cells 23 already arranged in this area 23 in area
A and 23B need to be replaced. Therefore, cell 23A is 240
And the cell 23B attempts to move to the 250 position. 250 cells to 251 position, 251 cells to
The gap was found by repeating the substitution successively to the 252 position. On the other hand, cell 23B moves to 240 and replaces two cells here, one of which finds a gap at position 2401, and the other performs a chain replacement with 241,242 to find a gap. And converge.

FIG. 3 is a diagram for explaining a cell arrangement position calculating method according to another embodiment of the present invention. In this example, chip 30 is n
Is divided into a plurality of regions (n = 3 × 3 in the figure), and the number of nets that intersect the boundary is defined as an evaluation function. That is, the number of intersections of the connecting nets between the added cells and the already arranged cells intersects the boundary depending on where the added cells 31 are arranged in the divided area, and the arrangement position is set so as to minimize this number. To determine. In the example of the figure, when the cell 31 is arranged in the region 321 as shown by the solid line, the connection net intersects the boundary at five places, and when the cell 31 is arranged in the region 322 as shown by the broken line, it becomes three places. Intersect with the border. Therefore, in this case, the area indicated by the solid line is selected as the arrangement position.

[Effects of the Invention] As described above, according to the present invention, it is possible to quickly change a layout design in response to a design change request from the system design side generated after the completion of layout design. In this case, since the information of the layout result thus far is utilized, the change can be minimized, and the occurrence of a layout error can be reliably prevented. In addition, the labor required for re-verification of the layout result is small.

[Brief description of the drawings]

FIG. 1 is a flowchart for explaining the processing procedure of one embodiment of the present invention, FIG. 2 is a diagram for explaining the operation at a specific chip level, and FIG. FIG. 4 is a diagram for explaining a method of calculating a cell arrangement position. FIG. 4 is a diagram showing a relationship between a system design and a layout design of an integrated circuit. 21: chip area, 22: cell to be added, 23: position to be added.

Claims (3)

(57) [Claims] 1. An integrated circuit automatic layout system for realizing a desired circuit by arranging and wiring cells having unit functions on a substrate using a computer, and changing a layout of an already arranged integrated circuit to a desired circuit. When a cell is added for correction according to the above, the position of the cell to be added (XT, YT) and the positions (xi, yi) of the other n cells already laid out in connection with this cell are A function that can calculate the distance of the variable as a variable, and adding a cell at or near a position where the evaluation function is minimized. 2. An integrated circuit automatic layout system for realizing a desired circuit by arranging and wiring cells having unit functions on a substrate using a computer, and changing a layout of an already arranged integrated circuit to a desired circuit. When adding a cell for correction according to the above, the integrated circuit is divided into a plurality of regions, and the number of nets that intersect the boundary is used as an evaluation function, and the position where this evaluation function is minimized when adding a cell Or a method of changing the design of an integrated circuit layout, characterized by adding a cell in the vicinity thereof. 3. If there is no void area to which cells can be added, 1
One or a plurality of already placed cells are regarded as unplaced cells, cells to be added are arranged in the obtained gaps, and similar processing is performed for unplaced cells as cells to be added. 3. The method for changing a design of an integrated circuit layout according to claim 1 or 2.