JP2774361B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In particular, a semiconductor integrated circuit adopting a redundant configuration is intended to improve the yield by avoiding the occurrence of defective redundant circuits while increasing the integration density. A semiconductor integrated circuit, comprising: a main circuit unit that repeatedly arranges the circuit; and at least one redundant circuit having the same configuration as the circuit, wherein a defective circuit of the main circuit unit is replaced with the redundant circuit. The wiring interval of the redundant circuit is wider than each of the above circuits. Further, the wiring interval is an interval between bit lines or an interval between word lines in a memory cell array.

[Industrial applications]

The present invention relates to a semiconductor integrated circuit, particularly to a semiconductor integrated circuit employing a redundant configuration.

In general, although increasing the degree of integration of a semiconductor integrated circuit is desirable in terms of operating speed and function enhancement, failure due to, for example, adhesion of dust or the like is likely to occur with the miniaturization of circuit patterns.

In order to prevent such a problem, for example, in a semiconductor memory device in which the same circuit is repeatedly arranged, a spare circuit (redundant circuit) having the same configuration as that of the above-described circuit is installed in advance, and a defect generating circuit is formed by the redundant circuit. Substitution is performed.

Such a redundant circuit is indispensable especially for a semiconductor memory device having a large capacity, and contributes to an improvement in yield by relieving a semiconductor memory device in which a defect has occurred.

[Conventional technology]

An example of a conventional redundant configuration can be seen in a highly repetitive one such as a memory cell of a semiconductor memory device.

That is, in the semiconductor memory device, a large number of bit lines are arranged, a large number of word lines are arranged so as to intersect with the bit lines, and memory cells are connected to respective intersections of the bit lines and the word lines. Bit lines, word lines and memory cells are formed by regularly arranging the same circuit pattern.If a circuit having the same pattern as those of the bit lines, word lines and memory cells is formed in advance as a redundant circuit, defective The yield can be improved by replacing the circuit.

[Problems to be solved by the invention]

However, in such a conventional semiconductor integrated circuit, since the same design rule is applied to the replacement target circuit and the redundant circuit, for example, when the circuit pattern is made ultra-fine in order to increase the integration density, the redundant Similarly, the circuit is also miniaturized and defects occur at the same rate. As a result, there is a problem that the replacement cannot be performed and the yield cannot be improved.

The present invention has been made in view of such a problem, and an object of the present invention is to increase the integration density and avoid the occurrence of a defect in a redundant circuit to improve the yield.

[Means for solving the problem]

In order to achieve the above object, the present invention comprises a main circuit section in which a plurality of identical circuits are repeatedly arranged, and at least one redundant circuit having the same configuration as the circuit, wherein a defective circuit in the main circuit section is provided. Is replaced with the redundant circuit, wherein the wiring interval of the redundant circuit is wider than each circuit of the main circuit section. Further, the wiring interval is an interval between bit lines or an interval between word lines in a memory cell array.

[Action]

In the present invention, since the degree of miniaturization of the redundant circuit is larger than that of the main circuit, particularly, the wiring interval of transistors and the like is wider, so that, for example, even when the same minute dust adheres to both the main circuit part and the redundant circuit, the redundant circuit side The degree of failure occurrence is reduced.

Therefore, the redundancy replacement is performed without any trouble, and the yield is improved when the integration density is increased.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIGS. 1 to 4 show an embodiment of a semiconductor integrated circuit according to the present invention, which is an example applied to a semiconductor memory device.

In FIG. 1, reference numeral 10 denotes a main memory cell array as a main circuit portion, 11 denotes a redundant memory cell array as a redundant circuit, and these main memory cell array 10 and redundant memory cell array 11 are laid out at predetermined positions on the same chip 12. ing.

The main memory cell array 10 includes a pair of multiple bit lines
BL _i (i is a bit line numbers 1 and 2, a and a counter in the same number ...) with arranging a set of, and intersecting the bit lines BL _i also numerous each set word lines WL _j (j Are arrayed as a set of word line numbers 1, 2,...
_i and memory cells M _ij in each intersection of the word line WL _j (i is the bit line number, j is the word line number) is constituted by connecting.

Here, LB is an interval between a pair of bit lines BL _i and ▼, and LW is an interval between adjacent word lines WL _i and WL _i .

One representative memory cell M _1,1 has a load resistance R
a, Rb, cell transistors Ta and Tb, and select transistors Tc and Td. When the word line WL _i is added word line selection complementary signal, the select transistor Tc, Td becomes conductive pair of bit lines BL _i, ▲ ▼ and the cell transistor T
a, Tb are connected, and thereby the bit lines BL _i , ▲
The potential of ▼ is written to the cell transistors Ta and Tb, or the potential of the cell transistors Ta and Tb is changed to the bit lines BL _i and
It is read out by ▲ ▼. If the semiconductor memory device is read-only, it goes without saying that only the latter read operation is performed.

On the other hand, the redundant memory cell array 11 has the same configuration as that of the main memory cell array 10, and the same components are identified by the same reference numerals (with dashes (')).

The difference between these primary and redundant memory cell arrays is that
The number of bit lines and word lines of the redundant memory cell array 11 and the number of memory cells are smaller than those of the main memory cell array 10, and the degree of miniaturization is different.

That is, is an appropriate number that exceeds the total number of defective circuits (the number of defective bits) included in the main memory cell array 10, and is generally much smaller than the total number of bits of the main memory cell array 10.

The degree of miniaturization is a design rule in a broad sense, and specifically refers to the size of a transistor and the size of a wiring. However, in the case of the semiconductor memory device of this embodiment, the size of each transistor constituting a memory cell, And the size of word lines, and the spacing (particularly the spacing) between bit lines and word lines. For example, the interval “LB ′” between a pair of bit lines in the redundant memory cell array 11 and the interval “L
W ′ ”is the distance“ LB ”between the bit lines of the main memory cell array 10.
And greater than the word line spacing "LW" (LB <LB ',
LW <LW ').

FIGS. 2A and 2B are diagrams showing the bit line intervals LB and LB 'of the main memory cell array 10 and the redundant memory cell array 11 in comparison with each other. Here, LB' is 10% smaller than LB. The above is set to be large.

FIGS. 3A and 3B are pattern layout diagrams of main parts of the main memory cell array 10 and the redundant memory cell array 11, and correspond to the circuit shown in FIG. 4A or FIG. is there.

As described above, according to the present embodiment, both bit line intervals are set so that the side of the redundant memory cell array 11 becomes large.
Since LB and LB 'are set, for example, when fine dust adheres to the chip 12 during manufacturing, the redundant memory cell array
The degree of occurrence of defects (for example, short-circuiting between lines) on the 11 side can be reduced, and the redundancy replacement of the main memory cell array 10 can be performed without any trouble, thereby improving the manufacturing yield.

This effect is particularly effective when the degree of miniaturization of the main memory cell array 10 is reduced, that is, when the integration density is increased. This is because if the degree of miniaturization of the redundant memory cell array 11 is larger than the degree of miniaturization of the main memory cell array 10, even if the dust particles are such that the main memory cell array 10 may become a critical obstacle, the redundant memory cell array 11
This is because no hindrance occurs at all, or even if it does, the effect can be relatively reduced according to the difference in the degree of miniaturization.

In the above embodiment, the difference is provided in the bit line interval. However, the present invention is not limited to this. For example, the difference may be provided in the word line interval.

Further, the application is not limited to the semiconductor memory device, and any circuit may be used as long as the same circuit is repeatedly arranged and a spare circuit having the same configuration as the circuit is provided.

〔The invention's effect〕

According to the present invention, a difference is made in the degree of miniaturization of a main circuit and a redundant circuit that replaces the main circuit. Therefore, it is possible to increase the integration density and avoid the occurrence of defects in the redundant circuit to improve the yield. Can be.

[Brief description of the drawings]

1 to 4 show an embodiment of a semiconductor integrated circuit according to the present invention. FIG. 1 is a layout diagram thereof, and FIGS. 2 (a) and 2 (b) are diagrams of a main memory cell array and a redundant memory cell array. FIGS. 3 (a) and 3 (b) show the layouts of main parts of the main memory cell array and the redundant memory cell array, respectively. FIGS. It is a circuit diagram of a portion corresponding to a main part layout. 10: Main memory cell array (main circuit section), 11: Redundant memory cell array (redundant circuit).

Claims (2)

(57) [Claims] 1. A main circuit unit for repeatedly arranging a plurality of identical circuits, and at least one redundant circuit having the same configuration as the circuit, wherein a defective circuit of the main circuit unit is replaced with the redundant circuit. In the semiconductor integrated circuit, a wiring interval of the redundant circuit is wider than each circuit of the main circuit unit. 2. The semiconductor integrated circuit according to claim 1, wherein said wiring interval is an interval between bit lines or an interval between word lines in a memory cell array.