JP2773616B2 - Synchronous reference wave generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference wave generator for synchronizing reference waves generated by a plurality of devices. For example, in the case of synchronous broadcasting such as FM stereo broadcasting, each FM
This is useful for generating a reference wave of a broadcast machine.

[0002]

2. Description of the Related Art An FM stereo broadcast is broadcast by two audio channels, a main channel and a sub channel, and a stereo composite signal is composed of a main channel signal, a sub channel signal and a pilot signal in consideration of compatibility with monaural broadcasting. Have been.

In the field of FM stereo broadcasting, digitization is being promoted for reasons such as improvement of characteristics, improvement of operation stability, and prevention of sound quality deterioration in a transmission system. In particular, a stereo reference wave (a subcarrier signal of 38 KHz and a pilot signal of 19 KHz) required for a stereo modulator of an FM broadcaster has a read-only memory (hereinafter, referred to as ROM) storing these signal data. Generated using That is, the address counter is sequentially incremented, and the reference wave data is read from the ROM based on the address, thereby generating a sine wave as the reference wave.

[0004]

However, in the above-mentioned conventional reference wave generating apparatus, the address counter for giving the read address to the ROM is reset when the power supply of the broadcasting machine is turned on, so that the reference signal output from the ROM is reset. The wave is effective only on the broadcaster concerned, and cannot be synchronized with other broadcasters.

[0005] For example, when FM stereo synchronous broadcasting is performed by a plurality of FM broadcasters, since a reference wave generated by each FM broadcaster cannot be synchronized, a phase difference occurs between the FM broadcasters. There is a problem that characteristics such as the degree of left and right separation of stereo broadcasts are deteriorated.

An object of the present invention is to provide a synchronous reference wave generation device that can generate a reference wave synchronized between a plurality of devices.

[0007]

According to the present invention, there is provided a synchronous reference wave generating apparatus, comprising: reset signal generating means for generating a reset signal synchronized with a reference clock of an input signal commonly supplied to a plurality of apparatuses; Address generation means for resetting the address according to the operation clock of the device and incrementing the address in accordance with the operation clock of the device; reference wave storage means for storing the reference wave data in advance and generating the reference wave by sequentially reading out the data according to the address; It is characterized by consisting of.

In addition, a synchronous reference wave generating device according to the present invention includes a reference clock extracting means for extracting a reference clock from an input signal supplied to a plurality of devices, and one of the reference clocks synchronized with the reference clock. / N (n is an integer) a reset signal generating means for generating a reset signal having a cycle, a count means reset by the reset signal and incrementing a count in accordance with an operation clock of the device, and And a reference wave storage unit for storing the reference wave in advance corresponding to the cycle of the reset signal and sequentially reading the data according to the count value to generate the reference wave.

[0009]

The reset signal is synchronized with a reference clock extracted from an input signal commonly supplied to a plurality of devices. The reset signal causes the address generation means to increment the address while being reset, sequentially read reference wave data from the reference wave storage means according to the address, and generate a reference wave synchronized with the input signal.

The reset signal is synchronized with the reference clock and has a period of 1 / n (n is an integer) of the reference clock. The reference wave storage means stores reference wave data corresponding to the period of the reset signal. The reference wave data is read from the reference wave storage means in accordance with the addresses sequentially generated in the cycle of the reset signal, and a reference wave synchronized with the input signal is generated.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a synchronization reference wave generating apparatus according to the present invention. Note that this embodiment corresponds to a reference wave generation circuit in each broadcaster of FM stereo synchronous broadcasting, and the generated reference wave is a 38 KHz subcarrier signal and a 19 KHz pilot signal. In this embodiment, a digital audio signal is used as a common input signal for each broadcaster.
AES that constitutes one block with 192 frames at KHz
1 illustrates a digital audio signal of the / EBU standard.

In FIG. 1, an input signal decoder 1 extracts a reference clock signal a from a digital input signal, and a reset pulse generator 2 outputs a reset pulse b to an OR circuit based on the extracted reference clock signal a. The address counter 3 outputs the address count value d while being reset by the reset signal input through the OR circuit, and accordingly, the decoder 4 outputs the decoder output c at a constant cycle (an integer multiple of the reset pulse b) as described later. Output to OR circuit. The subcarrier ROM 5 and the pilot ROM 6 receive the count value d as a read address and output a subcarrier signal and a pilot signal as reference waves, respectively.

The reset pulse generator 2 and the address counter 3 operate according to the operation clock fs. The operation clock fs has a frequency of about several MHz. Here, it is assumed that fs = 1536 KHz.

First, the input signal decoder 1 performs AES / EB
It is composed of a dedicated integrated circuit that decodes a U-standard digital audio input signal, extracts a reference clock signal a of one block period (4 msec) from the audio input signal, and outputs it to the reset pulse generation unit 2. Note that one block cycle is calculated by (sampling cycle × number of block frames). Here, 1/48 KHz × 192 frames = 4 m
sec.

The reset pulse generator 2 generates a reset pulse b having the same pulse width as the operation clock cycle T = 1 / fs in synchronization with the reference clock signal a (period: 4 msec) and outputs it to the OR circuit.

FIG. 2 is a block diagram of the reset pulse generator 2. The reset pulse generator 2 includes two-stage latch circuits 201 and 202 and a NAND gate 203. The latch circuits 201 and 202 operate at an operating clock fs
To latch the reference clock signal a from the decoder 1 sequentially. The NAND gate 203 receives the output of the latch circuit 201 and the inverted output of the latch circuit 202, synchronizes with the above-described reference clock signal a, has one block cycle (4 msec), and has an operation clock cycle T = A reset pulse b having a pulse width of 1 / fs is generated.

The address counter 3 operates at an operating clock fs.
(1536 KHz), the count value d is incremented, and O
It is reset by a reset signal input through the R circuit and restarts counting. The count value d, which is the output of the address counter 3, is input to the decoder 4, and the decoder 4 sets the count value d to a predetermined value fs−1 (here, 1536−
1 = 1535), and outputs a decoder output c which goes to a low level to the OR circuit. Therefore, the cycle in which the decoder 4 outputs a low level is always 1 msec. This value of 1 msec corresponds to the reference wave data amount stored in the ROMs 5 and 6 described later.

The OR circuit takes the logical sum of the reset pulse b and the decoder output c and outputs the result to the address counter 3 as a reset signal. The count value d of the address counter 3 is input to the subcarrier ROM 5 and the pilot ROM 6 as a read address, and the subcarrier signal and the pilot signal are respectively read according to the read address.

FIG. 3 schematically shows data stored in the subcarrier ROM 5 and the pilot ROM 6, respectively. In this embodiment, each ROM is 1 m
The table for sec is stored. That is, the 38 kHz sin wave data is stored in the subcarrier ROM 5.
The 19-kHz sine-wave data is stored in the pilot ROM 6 for 19 cycles.

The decoder 4 generates a decoder output c having a period of 1 msec, thereby matching the period (4 msec) of the reference clock signal a with the amount of data (for 1 msec) stored in the ROMs 5 and 6. . Therefore, even if another input signal (for example, 3 msec, 6 msec, etc.) having a different cycle of the reference clock signal a is input, a pulse of 1 msec cycle synchronized therewith is always output from the decoder 4 and data of 1 msec is stored. ROM5
And 6 can be read. Of course, the cycle of the output c of the decoder 4 is not limited to 1 msec.
And 6 is determined by the amount of data stored in.

FIG. 4 is a timing chart for explaining the operation of this embodiment. First, the input signal decoder 1 extracts a reference clock signal a having a period of 4 msec. This reference clock signal “a” is, as shown in FIG.
The waveform levels of the reference clock signal a are sequentially detected at the timings of the operating clock fs that are successively input to the latch circuits 201 and 202 connected in stages, and based on the change in the detected level, the NAND gate 203 outputs the reference clock signal. In synchronization with the rise of the signal a, the operation clock cycle T =
A reset pulse b having a pulse width of 1 / fs is output.

A predetermined value (fs-1) for comparison with the count value d is set in the decoder 4 in advance. Here, since the operation clock frequency fs = 1536 KHz, the predetermined value is set to 1535, and the count value d
Becomes 1535 every 1 msec when 0 reaches 1535 from 0.

The address counter 3 increments the count in accordance with the operation clock fs. However, as described above, the output c of the decoder 4 goes low every 1 msec. Reset. Accordingly, as shown in FIG. 3, the count value d of the address counter 3 is output to the ROMs 5 and 6 as a read address which is synchronized with the reference clock signal a of the digital audio input signal and changes at a cycle of 1 msec.

Therefore, the sine waves of the subcarrier signal and the pilot signal output from the subcarrier ROM 5 and the pilot ROM 6, respectively, are synchronized with the reference clock of the audio input signal.

FIG. 5 is a schematic block diagram showing an example of an FM stereo broadcast system using this embodiment. Each FM
Each of the broadcasters 501 to 503 is provided with the reference wave generation circuit of the present embodiment, and generates a stereo reference wave (subcarrier signal and pilot signal) synchronized with a digital audio input signal provided in common.

[0027]

As described above in detail, the synchronous reference wave generating device according to the present invention reads out the reference wave data from the reference wave storage means in synchronization with the input signal commonly input to a plurality of devices. A reference wave synchronized between a plurality of devices can be generated in each device. For this reason, when the present invention is applied to, for example, synchronous broadcasting such as FM stereo broadcasting, deterioration of left / right separation characteristics can be prevented, and excellent stereo broadcasting can be achieved.

Further, the synchronous reference wave generating device according to the present invention generates a reset signal synchronized with the reference clock of the input signal and having a period of 1 / n (n is an integer) of the reference clock, and stores the reset signal in the reference wave storage means. By storing the reference wave data corresponding to the cycle of the reset signal, the reference wave can be generated from the reference wave storage unit even if the cycle of the reference clock of the input signal changes.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronization reference wave generation device according to the present invention.

FIG. 2 is a block diagram illustrating a specific configuration of a reset pulse generator 2 according to the present embodiment.

FIG. 3 is a waveform diagram schematically showing data stored in a subcarrier ROM 5 and a pilot ROM 6 in the present embodiment.

FIG. 4 is a timing chart for explaining the operation of the present embodiment.

FIG. 5 is a schematic block diagram illustrating an example of a system for FM stereo synchronous broadcasting using the present embodiment.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 input signal decoder 2 reset pulse generator 3 address counter 4 decoder 5 subcarrier ROM 6 pilot ROM a reference clock signal b reset pulse c decoder output d count value

Claims (5)

(57) [Claims] 1. A synchronization reference wave generation device provided in each of a plurality of broadcasting devices for establishing synchronization of each reference wave in said plurality of broadcasting devices, wherein a digital audio signal commonly supplied to said plurality of broadcasting devices is provided. Reference clock extracting means for extracting a reference clock from an input signal; and one of the reference clocks synchronized with the reference clock.
Reset signal generating means for generating a reset signal having a cycle of / n (n is an integer), counting means reset by the reset signal and incrementing the count according to the operation clock of the device, A reference wave storage unit that stores the reference wave in advance corresponding to the cycle of the reset signal and sequentially reads out the data according to the count value to generate the reference wave. . 2. The broadcasting apparatus according to claim 1, wherein the plurality of broadcasting apparatuses are FM stereo broadcasting apparatuses constituting a synchronous broadcasting system, and the digital audio input signal is an audio digital signal having a cycle of the reference clock as one block unit. The synchronous reference wave generator according to claim 1. 3. The reference wave comprises a subcarrier signal and a pilot signal of FM stereo broadcast, and the reference wave storage means includes a first read-only memory for storing the subcarrier signal and a first read-only memory for storing the pilot signal. 3. The synchronous reference wave generation device according to claim 2, comprising two read-only memories. 4. A synchronization reference wave generation device provided in each of a plurality of FM stereo broadcasting devices and establishing synchronization of each reference wave generated by said plurality of FM broadcasting devices. Reset signal generating means for generating a reset signal synchronized with a reference clock of a commonly supplied digital audio input signal; address generating means reset by the reset signal and incrementing an address according to an operation clock of the device; A reference wave storage unit for storing reference wave data in advance and sequentially reading out the data according to the address to generate the reference wave. 5. The reference wave comprises a subcarrier signal and a pilot signal of FM stereo broadcast, and the reference wave storage means stores a first read-only memory for storing the subcarrier signal and the pilot signal. The synchronous reference wave generating device according to claim 4, comprising a second read-only memory.