JP2772182B2 - Invalidation method of shadow access register at the time of access register converter purge instruction - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a space indicator STD (Segment-Table Descriptor) for designating a virtual storage space by designating an access address number when an access instruction to a main memory is executed.
Signing) is obtained by using the access register conversion unit ART and registered in the shadow access register, and thereafter, the information processing device is configured to obtain the space indicator at high speed by referring to the shadow access register. The present invention relates to a shadow access register invalidation method at the time of executing an purge instruction PALB of an ART, which also invalidates a shadow access register at the time of an access register conversion unit purge instruction.

When executing a load instruction or a store instruction for a main memory, an absolute address of the main memory is obtained by using an access register mechanism. The access register mechanism is
An access list entry token ALET obtained by designating a specific access register by execution of the access instruction is given to the access register conversion unit ART, and the space indicator ST
The dynamic address conversion unit DAT obtains the absolute address of the main storage MSU from the virtual address as the address in the space created by executing the instruction and the space designation value STD.

However, every time an access instruction is executed, the space indicator STD is used by using the access register conversion unit ART.
Is complicated and time-consuming, so once
When the space indicator STD is obtained, the access register number is registered as an index in the shadow access register, and thereafter, the speed is increased by obtaining the space indicator STD by referring to the shadow access register by the access register number.

The access register conversion unit ART
Are implemented as a reference buffer ALB for the access register conversion unit, the contents of which are loaded from the main storage MSU, and when there is a change in the contents on the main storage MSU side, the address register conversion unit purge instruction PALB Erase and then reload from main storage MSU. In this case, the contents of the shadow access register are all reset. However, the space indicator STD indicating the instruction space is predetermined, and is not changed on the main memory MSU side, and the space indicator STD of the instruction space which is not changed even when reloaded is deleted and registered. The efficiency is poor because it is fixed, and improvement of this point is desired.

[0005]

2. Description of the Related Art FIG. 4 is an explanatory diagram of a conventional access register mechanism having no shadow access register. FIG.
In the figure, reference numeral 10 denotes an access register unit, for example, 16
Access registers AR0 to AR15. Each of the access registers AR1 to AR15 has a space indicator STD of a virtual space when a load instruction or a store instruction is executed.
Access-List-Entry Token used to obtain the request is stored.

Reference numeral 12 denotes an access register conversion unit ART (Ac
cess-Regiater Translation), and the access list entry token AL from the access register unit 10
ET and an access list instruction source origin ALDSO (Access-List Desi
gnation Source Origin) and the identification number DM of the VM domain indicating the currently operating virtual machine (Virtual Machine)
ID and a space indicator ST indicating a virtual space.
D is obtained and the dynamic address translation unit 14 (DAT; Dynamic A
ddressTranslation).

[0007] Here, the access list instruction source origin ALDSO determines the value of the control registers CR2 to CR5 by the primary list bit (Primary-List Bit) in the access entry token ALET obtained from the access register unit 10. Take. Reference numeral 32 denotes a general-purpose register unit (base register unit) which includes general-purpose register registers GR0 to GR15, receives designation of a general-purpose register number GR-NO according to an access instruction, and uses one or a plurality of designated general-purpose register values. Then, an internal address in the virtual space is created as a virtual address and output to the dynamic address translator 14.

The dynamic address translation unit 14 is realized as a translation reference buffer TLB (Translation Lookside Buffer), and receives a space indicator ST from the access register translation unit 12.
D and a virtual address (in-space address) created from the contents of the general-purpose register unit 32 are input and converted into an absolute address (Absolute Address) of the main storage MSU. FIG. 5 shows an example of a load instruction for the main memory.
FIG. 5A shows the instruction format, and FIG. 5B shows the contents.

That is, the instruction format of the load instruction LD is:
It is a 4-byte instruction and it is a load instruction "58"
, And the target register is a general-purpose register GR1.
The index register is a general-purpose register GR3, the base register is a general-purpose register GR4, and an offset "FFF" is stored. The VM domain currently running on the operating system OS is:
When this load instruction LD is received, for example, an operation of referring to the internal address (GR3 + GR4 + FFF) of the virtual space specified by the space indicator STD obtained based on the access register AR4 and storing the result in the general-purpose register GR1 is performed. .

FIG. 6 shows the operation of the access register mechanism when the load instruction LD of FIG. 5A is executed.
For example, the access register AR4 is specified by the access register number AR-NO from the operation system OS, and the access list entry token AELT stored in the access register AR4 is given to the access register conversion unit 12.

As shown in FIG. 4, the access register conversion unit 12 accesses the access list entry token ALE.
T, an access list instruction from the control register unit 32, a source / origin ALDSO, and a V currently operating.
Space indicator ST using identification number VMID of M domain
Find D. On the other hand, the contents of the general-purpose registers GR3 and GR4 of the general-purpose register section 30 are read, and (GR3 + GR4 +
FFF), an internal address is created, and the space indicator ST
The address is input to the dynamic address translator 14 together with D, and the absolute address is obtained to access the main storage MSU. The load data read from the main storage MSU is stored in a general-purpose register GR1 specified as a target register.

However, in such an access register mechanism, the space indicator STD is obtained by using the access register conversion unit 14 every time an access instruction is executed. bad. FIG. 7 shows a method for speeding up the conversion to the space indicator STD.
The shadow access register (Shadoe Acces
s Register) 16.

The shadow access register 16 stores a space indicator STD by using the access register number AR-NO as an index, and a valid code (Valid Code) indicating whether or not the space indicator STD is stored in the storage unit 18.
20 is provided, and a 1-bit code is stored in the valid code section 20. Bit 1 indicates valid and bit 0 indicates invalid.

The registration and use of the shadow access register 16 are performed as follows. When the access register number AR-NO is obtained by executing the access instruction, the shadow access register 16 is referred to, and when the valid code of code bit 1 is obtained from the valid code unit 20, the space indicator of the corresponding storage unit 18 is obtained. The STD is read and output to the dynamic address translator 14. At this time, the conversion operation of the access register conversion unit 12 based on the valid code is prohibited.

On the other hand, when the invalid code of code bit 0 is obtained from the valid code section 20, the access register converting section 14 performs the space indicator S in the same manner as in FIG.
The TD is obtained and stored in the storage section 18 of the shadow access register 16 specified by the access status number AR-NO, and the valid code of the code bit 1 is set in the corresponding valid code section 20.

Such a shadow access register 16
Again after registering the access register number AR-N
In O, the shadow access register 16 is referred to, and in this case, a valid code is obtained. Therefore, the space indicator STD stored in the corresponding storage unit 18 is read and output to the dynamic address translation unit 14. By using the shadow access register 16 in this way, the number of times of conversion processing to the space indicator STD using the access register conversion unit 12 can be reduced, and the processing can be speeded up.

On the other hand, the contents of the access register converter 12 are loaded from the main memory MSU, and are stored in the main memory MSU.
If there is a change in the contents of the access converter ART stored in U, the access register converter 12 is erased by the purge instruction PALB of the access register converter reference buffer, and then reloaded. Since it is necessary to erase the contents of the shadow access register 16 at the same time, conventionally, as shown in FIG. 8, all entries of the shadow access register 16 are erased in response to a purge signal.

Incidentally, the conversion to the STD by specifying the space by the access register conversion unit 12 is performed when the value of the access list entry token ALET obtained from the access register unit 10 is 0 or 1, Access list entry without translation by
The value of the control register CR1 indicating the primary space when the token ALET = 0 is used as it is as the space indicator STD, and the access list entry talk
It is defined that the value of the control register CR7 indicating the secondary space when ALET = 1 is used as it is as the space indicator STD.

Normally, the primary space specified by the control register CR1 and the secondary space specified by the control register CR7 are used as instruction spaces, and are frequently accessed because they are instruction spaces. Access register conversion unit A stored in
RT does not change the contents of the instruction space. Therefore, it is expected that the storage unit 18 of the shadow access register 16 will frequently register space indicators STD equal to the values of the control registers CR1 and CR7 indicating the instruction space.

However, in the conventional invalidation processing of the shadow access register 16 when the purge instruction PALB of the access register conversion unit reference buffer is executed, all the entries are erased, and the change is made on the main memory side. The space indicator STD indicating an instruction space that does not exist is registered again when it is used next time, and the conversion efficiency to the space indicator STD using the shadow access register 16 is reduced.

The present invention has been made in view of such a conventional problem, and the shadow access register is used even when the jadow access register is invalidated when the purge instruction PALB of the access register conversion unit reference buffer is executed. An object of the present invention is to provide a shadow access register invalidation method at the time of an access register conversion unit purge instruction, which enables efficient conversion to a space indicator STD.

[0022]

FIG. 1 is a diagram illustrating the principle of the present invention. First, the present invention is directed to an information processing apparatus having the following access register mechanism. The access register mechanism includes an access register unit 10, an access register conversion unit 12, a dynamic address conversion unit 14, a shadow access register unit 16 Is provided.

The access register section 10 is composed of a plurality of access registers AR0 to AR15 storing access list input tokens ALET. The access register converter 12 converts the access list input token ALE from any access register ARi specified by the access register number AR-NO obtained by executing the access instruction.
T is converted into a space indicator STD indicating a virtual storage space.

The dynamic address translator 14 inputs the space indicator STD from the access register translator 12 and a virtual address indicating an address in the space obtained based on the access instruction, and translates the address into an absolute address of the main storage MSU. I do. Further, the shadow access register unit 16 includes a storage unit 18 for the space indicator STD and an effective code unit 20 for indicating whether or not the storage state of the space indicator STD is stored, corresponding to the access register number AR-NO. The operation refers to the valid code section 20 corresponding to the access register number AR-NO obtained by executing the access instruction, and if a valid code is obtained, reads out the space indicator STD of the corresponding storage section 18 and Output to the dynamic address translation unit 14.

On the other hand, when an invalid code is obtained, the space indicator STD obtained by the access register conversion unit 12 is stored in the storage unit 18 and a valid code is set to 20 without a valid code. Then, the space indicator STD is read from the storage unit 18 and output to the dynamic address translation unit 14. Regarding the information processing apparatus having such an access register mechanism, in the shadow access register invalidating method at the time of the access register conversion unit purge instruction of the present invention,
The presence / absence of the space indicator STD is stored in the valid code unit 20 of the shadow access register unit 16 together with a code indicating that the stored space indicator STD indicates a predetermined storage space with a high access frequency.

Then, the purge mechanism unit 22 erases the contents of the access register conversion unit 12 and reloads the contents from the main memory. When the purge instruction PALB of the access register conversion unit is executed, the valid code unit 20 of the shadow access register unit 16 is deleted. If the valid code indicates that the space indicator STD of the predetermined space having a high access frequency is stored, the reset of the space indicator STD of the storage unit 18 is prohibited and left, and the valid code has a high access frequency. When the storage of the space indicator STD other than the predetermined space is indicated, the space indicator STD of the storage unit 18 is reset to enable re-registration.

More specifically, the code stored in the effective code section 20 of the shadow access register section 16 has an identification function for indicating that a space indicator STD for designating an instruction space has been stored. Resets the space indicator STD of the instruction space when the access register converter purge instruction PALB is executed, and resets the space indicator STD other than the instruction space to enable re-registration.

Here, the valid code section 20 of the shadow access register section 16 stores a 2-bit code, a 2-bit code 00 indicates invalidity, 01 indicates storage of a space indicator STD of the primary instruction space, and 10 Shows the storage of the space indicator STD of the secondary instruction space.
Indicates storage of the space indicator STD of the non-instruction space. Further, the purge mechanism unit 22 compares the code of the valid code unit 20 with a reference code indicating the storage of the space indicator STD in the instruction space, and compares the output of the comparison units 24 and 26 with the purge signal. A logical product is taken, and when a mismatch output is obtained from the comparison units 24 and 26, the space indicator ST of the storage unit 18 is obtained.
A reset unit for resetting D and prohibiting resetting of the space indicator STD of the storage unit when a coincidence output is obtained from the comparison units and.

Further, the access register conversion unit 12 determines that the primary list bit of the access list input token ALET obtained from the access register AR is O or 1
Otherwise, access list input token ALET,
An identification number DMID indicating a VM domain which is a virtual machine currently operating, and an access list input token ALET
With the value ALDSO obtained from the control registers CR2 to CR5 specified by the primary list bits of
The space indicator STD is obtained based on one entry.

On the other hand, the access list input token ALE
If the primary list bit of T is 0 or 1, then
The values of the control registers CR1 and CR7 indicating the instruction space are output as they are as space indicators STD.

[0031]

According to the shadow register invalidating method at the time of the purge instruction of the access register converting section of the present invention, the valid code section 2 of the shadow access register 16 is used.
0 indicates the presence / absence of registration (entry) of the space indicator STD, and at the same time, the space indicator S indicating an instruction space that does not need to be changed.
For example, a 2-bit code indicating that the TD is stored is set, and when the purge instruction PALB of the access register conversion unit reference buffer is executed, the reference buffer ALB functioning as the access register conversion unit ART is erased and, at the same time, the shadow access register is deleted. A space designator STD indicating an instruction space with the valid codes in 16 being 01 and 10.
Is prohibited, and the space indicator STD indicating the instruction space is left.

Therefore, by executing the purge instruction PALB of the access register conversion unit reference buffer ALB, a new access register conversion unit ART from the main memory refers to the reference buffer A.
Even after reloading to the LB, the space indicator STD indicating the instruction space can be obtained immediately by referring to the shadow access register 16. Since the frequency of access to the instruction space is high, the space indicator STD using the shadow access register 16 is used. The conversion efficiency to the child STD can be improved.

[0033]

FIG. 2 is a block diagram showing an embodiment of an access register mechanism used in the present invention. 2, reference numeral 10 denotes an access register unit having access registers AR0 to AR15, and reference numeral 12 denotes an access register conversion unit (AR).
T), 14 are an identification address conversion unit (DAT), 16 is a shadow access register unit, 30 is a control register unit having control registers CR0 to CR15,
Reference numeral 32 denotes a general-purpose register unit including general-purpose registers GR0 to GR15.

Although the construction and function of these are basically the same as those of the conventional mechanism shown in FIG. 7, in the present invention, a 2-bit code is stored in the effective code section 20 of the shadow access register section 16. I have. The 2-bit code stored in the valid code section 20 has a function as a valid code indicating whether or not the space indicator STD is stored in the storage section 18 and a function of identifying whether or not the space indicator STD indicates an instruction space.

That is, the 2-bit code stored in the valid code section 20 is [code bit] [STD storage state] [indication space type] 00 invalid code None 01 valid code primary instruction space 10 valid code secondary instruction space 11 Effective code means non-instruction space.

Reference numeral 22 denotes a purge mechanism unit, which refers to the valid code unit 20 in each entry of the shadow access register unit 16 when the purge instruction PALB of the access register conversion unit reference buffer ALB for realizing the access register conversion unit 12 is executed. Space indicator STD of storage unit 18
Reset is performed selectively. That is, when the referenced 2-bit code of the valid code unit 20 is “01” indicating registration of the space indicator STD of the primary instruction space, or “10” indicating registration of the space indicator STD of the secondary instruction space, Erasing by resetting the storage unit 18 by the purge signal is prohibited, and the space indicator STD is left as it is.

On the other hand, the effective code part 20-2 referred to
When the bit code is “11” indicating the registration of the indicator STD of the non-instruction space other than the primary instruction space and the secondary instruction space, the space indicator STD of the storage unit 18 is reset by the purge signal by the purge signal. Erase, and the valid code part 20 is also returned to “00”. FIG. 3 is a block diagram showing an embodiment of the purge mechanism unit 22 of FIG. 2 together with the shadow mask register unit 16.

In FIG. 3, the purge mechanism unit 22 includes comparison units 24 and 26 and an AND circuit 2 functioning as a reset unit.
8 are provided. A reference code “01” indicating the storage of the space indicator STD of the primary instruction space is set to one of the inputs of the comparison unit 24, and the storage of the space indicator STD of the primary instruction space is set to one input of the comparison unit 26. Is set. Further, the comparison unit 2
The other input of 4, 26 is given the 2-bit code of the valid code section 20.

When the purge command PALB is executed, the comparators 24 and 26 sequentially read the 2-bit codes of the valid code section 20 of the shadow access register 16 and compare them with the reference codes "01" and "10". Output 0
And a comparison output 1 is generated in the case of a mismatch. Therefore, the 2-bit code of the valid code section 20 is changed to the invalid code “0”.
If it is "0" or "11" indicating the storage of the space indicator STD of the non-instruction space, the comparators 24 and 26 detect mismatch with the reference codes "01" and "10", and the comparison output is output. Since the reset signal from the AND circuit 28 also becomes 1 since the purge signal is also 1 and the space indicator STD stored in the storage unit 18 is reset and erased, and re-registration is possible.

On the other hand, when the 2-bit code of the valid code section 20 is “01” indicating the registration of the space indicator STD of the primary instruction space, the comparison section 24 determines that the reference code “01” matches. Is detected and the comparison output becomes 0,
The AND circuit 28 is disabled, the reset signal is not made valid, and the space indicator STD indicating the primary instruction space stored in the storage unit 18 is left without being erased.

If the 2-bit code of the valid code section 20 is "10" indicating the registration of the space indicator STD of the secondary instruction space, the comparison section 26 detects the coincidence with the reference code 10 and The comparison output becomes 0 and AN
The D circuit 28 is disabled, the reset signal is not made valid, and the space indicator STD indicating the primary instruction space stored in the storage unit 18 is left without being erased.

By such invalidation processing based on the purge signal, the space indicator S indicating the primary instruction space and the secondary instruction space is stored in the shadow access register unit 16.
TD is left as it is, and a space indicator S indicating a non-instruction space
In the access after the TD is erased and the address register conversion unit 12 has been reloaded from the main storage MSU, it is not necessary to re-register the space indicator STD indicating the instruction space. AR-NO Shadow Access Register 16
, The space indicator STD can be obtained immediately, the conversion process can be made efficient by the amount that does not require re-registration, and the frequency of access to the instruction space is high. Therefore, the space indicator STD using the shadow access register 16 is used. The overall conversion efficiency of the STD can be significantly increased.

In the above embodiment, the access register mechanism when operating in the virtual machine mode is taken as an example. In the normal machine mode, if the ID number DMID of the VN domain for the access register converter 12 is ignored. It can be applied to the normal computer mode. In the above-described embodiment, the case where 16 access address registers are provided is taken as an example. However, an appropriate number may be used as needed.

Furthermore, the number of virtual spaces and the allocation state of instruction spaces in the virtual space are also determined as needed, and are not limited by the embodiments.

[0045]

According to the present invention, as described above, the space indicator STD registered in the shadow access register is provided.
Is not erased by the purge instruction PALB of the access register conversion unit reference buffer, which eliminates the need for re-registration after reloading the access register conversion unit. Increase the conversion efficiency of space indicators using access registers,
As a result, the address conversion at the time of executing the access instruction by the access register mechanism can be performed at higher speed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a configuration diagram of an embodiment of a purge mechanism of FIG. 2;

FIG. 4 is an explanatory diagram of a conventional access register mechanism having no shadow access register.

FIG. 5 is an explanatory diagram showing an example of a load instruction for causing the access register mechanism to perform address conversion.

FIG. 6 is an explanatory diagram showing an address conversion operation when the load instruction of FIG. 5 is executed.

FIG. 7 is an explanatory diagram of a conventional access register mechanism having a shadow access register.

FIG. 8 is an explanatory diagram showing a conventional purge process for a shadow access register.

[Explanation of symbols]

 10: access register section 12: access register conversion section (ART) 14: dynamic address conversion section (DAT) 16: shadow access register section 18: space indicator storage section 20: valid code section 22: purge mechanism section 24, 26 : Comparison unit 28: reset unit 30: control register unit 32: general-purpose register unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 12/08-12/12

Claims (5)

(57) [Claims] 1. A access obtaining a plurality of access register access register unit having a motor, a space indicator indicating a virtual memory space based on the contents of any access register designated by the access instruction execution time of the access register number A register translation unit, a dynamic address translation unit for inputting a virtual address indicating a space address obtained based on the space indicator and the access instruction obtained by the access register translation unit and translating the virtual address into an absolute address of a main memory; A storage unit for storing a space indicator using an access register number as an index, and a shadow access register unit for outputting a space indicator according to the access register number when executing an access instruction. and whether storage space indicator to the access register unit, the space indicator is a predetermined storage that store 2 bits to store the state identification code <br/> de consisting purge instruction of the access register translation unit to reload from the erase to main memory the contents of the access register translation unit for indicating that the indicated between During execution of the state identification code of the shadow access register section.
The code is compared with a fixed reference code to determine the status.
If the code and the reference code match , the reset of the space indicator in the storage unit is prohibited and retained, and the state identification code is left.
When the code does not match the reference code , a purge mechanism that resets the space indicator of the storage unit and allows re-registration is provided. System. 2. The shadow access register invalidation system at the time of an access register conversion section purge instruction according to claim 1, wherein an instruction space representing an instruction is specified in a code stored in a state identification code section of said shadow access register section. The purge mechanism unit has an identification function indicating that a space indicator to be stored is stored, and when the access register conversion unit purge instruction is executed, resetting of the space indicator indicating the instruction space is prohibited and left. A method of invalidating a shadow access register at the time of a purge instruction of an access register conversion unit, wherein a space indicator other than the above is reset to enable re-registration. 3. A shadow access register invalidating method at the time of an access register conversion section purge instruction according to claim 2, wherein a 2-bit code is stored in a state identification code section of said shadow access register section. indicates invalid in 00, 01 shows a storage space indicator of plastics Lee Mali instruction space, shows the storage space indicator of secondary instruction space 10, a storage space indicator of non-instruction space further 11 A shadow access register invalidation method at the time of an access register conversion section purge instruction. 4. A method according to claim 2, wherein said purge mechanism unit stores a code of said status identification code unit and a space indicator of an instruction space. A comparison unit for comparing the output of the comparison unit with a purge signal, and when a mismatch output is obtained from the comparison unit, resets a space indicator of the storage unit; A reset unit for prohibiting resetting of the space indicator of the storage unit when a coincidence output is obtained from the unit, and a shadow access register invalidation method at the time of an access register conversion unit purge instruction. 5. In the shadow access registers invalidation method when claim 1, wherein the access register translation unit purging instruction, the access register is te conversion unit, the value of the access list entry token obtained from the access register but in the case of other than 0 or 1, and the access-list-entry token,
Determining a space indicator based on three entries: an identification number indicating a currently operating VM domain, and a value obtained from a control register specified by a primary list bit of the access list input token; A shadow access register invalidation method at the time of an access register conversion unit purge instruction, wherein when the value of the input token is 0 or 1, the value of the control register indicating the instruction space is output as it is as a space indicator.