JP2769160B2 - Electronic component mounting method - Google Patents

Electronic component mounting method

Info

Publication number
JP2769160B2
JP2769160B2 JP63127719A JP12771988A JP2769160B2 JP 2769160 B2 JP2769160 B2 JP 2769160B2 JP 63127719 A JP63127719 A JP 63127719A JP 12771988 A JP12771988 A JP 12771988A JP 2769160 B2 JP2769160 B2 JP 2769160B2
Authority
JP
Japan
Prior art keywords
electronic component
flux
solder
chip
mounting method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63127719A
Other languages
Japanese (ja)
Other versions
JPH01297889A (en
Inventor
喜文 北山
徳人 浜根
幸男 前田
浩一 熊谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63127719A priority Critical patent/JP2769160B2/en
Publication of JPH01297889A publication Critical patent/JPH01297889A/en
Application granted granted Critical
Publication of JP2769160B2 publication Critical patent/JP2769160B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明はチップ形部品等の電子部品を高精度に印刷配
線板へ取付ける電子部品取付け方法に関するものであ
る。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting an electronic component such as a chip-type component on a printed wiring board with high accuracy.

従来の技術 近年、電子部品、特にチップ部品は増々小型化する傾
向にある。
2. Description of the Related Art In recent years, electronic components, particularly chip components, have been increasingly miniaturized.

以下図面を参照しながら、上述した従来のチップ部品
の印刷回路基板への取付け方法の一例について説明す
る。
Hereinafter, an example of a method for attaching the above-described conventional chip component to a printed circuit board will be described with reference to the drawings.

第2図は従来のチップ部品の取付け方法を示す工程図
である。
FIG. 2 is a process diagram showing a conventional method for mounting chip components.

同図において、まず、基板1上に形成された導体2上
のレジスト3が形成されていない部分に電気メッキ法,
溶融ハンダ浸漬法などによって半田4を形成する(第2
図(a))、次に基板1、レジスト3、半田4を覆うよ
うにフラックス5を全面に塗布する(第2図(b))、
次にチップ部品6の電極7とハンダ4とを位置合わせし
たのちフラックス5の粘着力を利用してマウントと同時
に仮固定する(第5図(c))、最後に200℃から250℃
に加熱されたリフロー炉に通して半田4を再溶融させて
チップ部品6の電極7と合金層を形成させてチップ部品
6を基板1に取付けていた(第2図(d))。
In the figure, first, a portion of a conductor 2 formed on a substrate 1 on which a resist 3 is not formed is formed by electroplating,
The solder 4 is formed by a molten solder immersion method or the like (second
(A), and then apply a flux 5 over the entire surface so as to cover the substrate 1, the resist 3, and the solder 4 (FIG. 2 (b)).
Next, after positioning the electrode 7 of the chip component 6 and the solder 4, they are temporarily fixed at the same time as the mount using the adhesive force of the flux 5 (FIG. 5C), and finally from 200 ° C. to 250 ° C.
Then, the solder 4 was re-melted by passing through a reflow furnace heated to form an electrode 7 and an alloy layer of the chip component 6, and the chip component 6 was attached to the substrate 1 (FIG. 2 (d)).

発明が解決しようとする課題 しかしながら、上記のような構成では、フラックス5
の塗布量が管理できないので、チップ部品6の下部にあ
るフラックス5の溶剤成分が半田4が溶解する前に激し
く沸とうするために、チップ部品6が位置ずれチップ部
品6が立つ(マンハッタン現象)場合も生じていた。
However, in the above configuration, the flux 5
Since the application amount of the solder cannot be controlled, the solvent component of the flux 5 below the chip component 6 violently boil before the solder 4 is melted, so that the chip component 6 is displaced and the chip component 6 stands up (Manhattan phenomenon). Cases had also occurred.

この課題に鑑み、本発明は電子部品の位置ずれが生じ
ない電子部品取付方法を提供するものである。
In view of this problem, the present invention provides an electronic component mounting method that does not cause a displacement of the electronic component.

課題を解決するための手段 この目的を達成するため本発明の電子部品取付方法
は、基板上に形成された導体上の、レジストが形成され
ていない部分に半田層を形成する工程と、前記半田層上
のみにスクリーン印刷によりフラックスを塗布する工程
と、前記フラックスが塗布された一対の半田層上にチッ
プ型電子部品をマウントし、前記半田層をリフローさせ
る工程とを有するものである。
Means for Solving the Problems In order to achieve this object, an electronic component mounting method according to the present invention comprises a step of forming a solder layer on a portion of a conductor formed on a substrate where a resist is not formed; The method includes a step of applying a flux only on the layer by screen printing, and a step of mounting a chip-type electronic component on a pair of solder layers to which the flux has been applied, and reflowing the solder layer.

作用 この構成により、電子部品の下部にはフラックスが塗
布されていないために、フラックスの沸とうによる電子
部品の位置ずれやマンハッタン現象は発生しなくなる。
Operation With this configuration, since no flux is applied to the lower part of the electronic component, the displacement of the electronic component and the Manhattan phenomenon due to the boiling of the flux do not occur.

実 施 例 以下本発明の一実施例について、図面を参照しながら
説明する。
Embodiment An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例における電子部品取付方法
を示す工程図である。同図においてまず、基板11上に形
成された導体12上のレジスト13が形成されていない部分
に電気メッキ法,溶融ハンダ浸漬法によって半田層14を
形成する(第1図(a))、次にスクリーン印刷法によ
ってロジン系フラックス15を半田層14上に塗布する(同
図(b))、次にチップ部品16の電極17と半田層14とを
位置合わせしたのちチップ部品16を基板11にマウントし
て、フラックス15の粘着力を利用して仮固定する(同図
(c))、最後に200℃〜250℃の温度に加熱されたリフ
ロー炉に通して半田層14を溶解させチップ部品16の電極
17と合金層を形成させて基板11にチップ部品16を取付け
る(同図(d))。
FIG. 1 is a process chart showing an electronic component mounting method according to one embodiment of the present invention. In FIG. 1, first, a solder layer 14 is formed by electroplating or molten solder immersion on a portion of a conductor 12 formed on a substrate 11 where a resist 13 is not formed (FIG. 1A). Then, a rosin flux 15 is applied on the solder layer 14 by a screen printing method ((b) in the same figure). Next, the electrode 17 of the chip component 16 and the solder layer 14 are aligned, and then the chip component 16 is applied to the substrate 11. It is mounted and temporarily fixed using the adhesive force of the flux 15 ((c) in the same figure). Finally, it is passed through a reflow furnace heated to a temperature of 200 ° C. to 250 ° C. to melt the solder layer 14 and chip components. 16 electrodes
The chip component 16 is mounted on the substrate 11 after forming an alloy layer with the alloy 17 (FIG. 4D).

以上のように実施例によれば、半田層14上にフラック
ス15を部分塗布することによって、チップ部品16の位置
ずれやマンハッタン現象がなくなる。
As described above, according to the embodiment, by partially applying the flux 15 on the solder layer 14, the displacement of the chip component 16 and the Manhattan phenomenon are eliminated.

発明の効果 以上のように本発明は、電子部品を取付けるランド部
にのみフラックスを塗布することによって、フラックス
中の溶剤の沸とうによる電子部品の位置ずれやマンハッ
タン現象を防止することができる。
Effect of the Invention As described above, the present invention can prevent the displacement of the electronic component and the Manhattan phenomenon due to the boiling of the solvent in the flux by applying the flux only to the land where the electronic component is to be mounted.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(d)は本発明の一実施例における電子
部品取付方法を示す工程断面図、第2図(a)〜(d)
は従来の電子部品取付方法を示す工程断面図である。 11……基板、12……導体、13……レジスト、14……半田
層、15……フラックス、16……チップ部品、17……電
極。
1 (a) to 1 (d) are process cross-sectional views showing a method of attaching an electronic component according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (d).
FIG. 4 is a process sectional view showing a conventional electronic component mounting method. 11 ... board, 12 ... conductor, 13 ... resist, 14 ... solder layer, 15 ... flux, 16 ... chip parts, 17 ... electrodes.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 前田 幸男 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (72)発明者 熊谷 浩一 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (56)参考文献 特開 昭55−67190(JP,A) (58)調査した分野(Int.Cl.6,DB名) H05K 3/34──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yukio Maeda 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-55-67190 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H05K 3/34

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】基板上に形成された導体上の、レジストが
形成されていない部分に半田層を形成する工程と、前記
半田層上のみにスクリーン印刷によりフラックスを塗布
する工程と、前記フラックスが塗布された一対の半田層
上にチップ型電子部品をマウントし、前記半田層をリフ
ローさせる工程とを有する電子部品取付方法。
A step of forming a solder layer on a portion of the conductor formed on the substrate on which a resist is not formed, a step of applying a flux only on the solder layer by screen printing, Mounting a chip-type electronic component on a pair of applied solder layers, and reflowing the solder layer.
JP63127719A 1988-05-25 1988-05-25 Electronic component mounting method Expired - Fee Related JP2769160B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63127719A JP2769160B2 (en) 1988-05-25 1988-05-25 Electronic component mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63127719A JP2769160B2 (en) 1988-05-25 1988-05-25 Electronic component mounting method

Publications (2)

Publication Number Publication Date
JPH01297889A JPH01297889A (en) 1989-11-30
JP2769160B2 true JP2769160B2 (en) 1998-06-25

Family

ID=14967015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63127719A Expired - Fee Related JP2769160B2 (en) 1988-05-25 1988-05-25 Electronic component mounting method

Country Status (1)

Country Link
JP (1) JP2769160B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5567190A (en) * 1978-11-15 1980-05-21 Matsushita Electric Works Ltd Soldering method

Also Published As

Publication number Publication date
JPH01297889A (en) 1989-11-30

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