JP2766415B2 - Digital waveform smoother circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital waveform smoother circuit for limiting the frequency band of a digital signal by waveform processing.

[0002]

2. Description of the Related Art In general, in a radio transmission system in satellite communication or terrestrial microwave communication, a carrier modulation transmission system in which a carrier is modulated by a digital signal is used. PSK
(Phase shift keying) modulation is one of them, and basically switches the phase of a carrier wave according to "1" or "0" of a digital signal.

By the way, a digital signal is a rectangular wave,
It contains many harmonic components. Therefore, if PSK modulation is applied to this digital signal as it is, its frequency band is widened and multiplex transmission becomes difficult. Therefore, it is conceivable to dull the waveform of the digital signal to remove the higher harmonic component and limit the band. Hereinafter, a circuit that performs such waveform processing is referred to as a digital waveform smoother circuit.

In the above-described waveform processing, it is common to use a low-pass filter. However, in practice, it is difficult to converge vibration after rising and falling, and it is not easy to set characteristics. Therefore, USP 4,339,724 (reference “DIGITAL
COMMUNICATIONS ”(author Dr. KAMIO FEHER, Ph. D., M.
A. Sc, P. Eng.) Has been considered.

[0005] As shown in FIG.
To fourth signal sources 31 to 34, first to fourth switches 35 to 38 for deriving outputs of the signal sources 31 to 34 according to control signals, and switches 35 to 38 according to input digital signals. Logic circuit 3 for generating a control signal for
9.

The first and second signal sources 31 and 32 each have an amplitude E and a frequency that is 1 / the frequency of the input digital signal.
4 sine wave signals, but out of phase with each other by π. The third and fourth signal sources 33 and 34 are respectively +
The DC voltage signals of E and -E are generated. Each switch 35 ~
The signals derived at 38 are combined and output, but are further fed back to the logic circuit 39.

Now, it is assumed that a digital signal (a data string based on the NRZ code) shown in FIG. The logic circuit 39 determines a change in the state of the input digital signal, and based on the determination result, determines whether the switch 3
On / off control of 5-38 is performed to select one of the outputs of signal sources 31-34 for each symbol. This allows
As shown in FIG. 10B, a signal waveform from which the harmonic components of the input digital signal have been removed is obtained.

However, in the digital waveform smoother circuit using the filter having the above configuration, a plurality of signal sources are connected to one.
It is difficult to increase the speed of a switch that selects for each symbol, and cannot cope with the bit rate of a digital signal used in recent satellite communication and the like. Further, since a plurality of signal sources are required, the structure is complicated, and there is a great problem in terms of miniaturization and reliability.

[0009]

As described above, conventionally, there has been no effective means for removing a harmonic component of a high-speed digital signal and smoothing the waveform.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a digital waveform smoother circuit capable of smoothing the waveform of a high-speed digital signal with a simple structure, realizing miniaturization and improving reliability. With the goal.

[0011]

In order to achieve the above object, a digital waveform smoother circuit according to the present invention comprises: a delay circuit for delaying an input digital signal representing data by first and second levels by one symbol; A logic gate circuit that takes an exclusive OR of the output of the delay circuit and the input digital signal, a clock generation circuit that generates a clock having a frequency sufficiently higher than the frequency of the input digital signal,
A clock derivation circuit for selectively deriving an output clock of the clock generation circuit when an output signal of the logic gate circuit is at a first level; counting an output clock of the circuit; A counter for returning the count value to the initial value when the state changes from the first level to the first level; and a sine wave waveform digital signal for one cycle in a data area twice as many as the number of clocks included in one symbol of the input digital signal. A waveform data storage circuit that stores data and outputs corresponding digital data using the output of the counter as a read address; a digital-to-analog conversion circuit that converts the output of the waveform data storage circuit to an analog signal; And a low-pass filter for extracting only the fundamental wave from the first characteristic.

A delay circuit for delaying an input digital signal representing data by the first and second levels by one symbol, a logic gate circuit for obtaining an exclusive OR of an output of the delay circuit and the input digital signal, A clock generation circuit for generating a clock having a frequency sufficiently higher than the frequency of the input digital signal; and selectively outputting an output clock of the clock generation circuit when an output signal of the logic gate circuit is at a first level. A clock deriving circuit, a latch circuit for latching a frequency specific value, and a cumulative value of the latched value according to an output clock of the clock deriving circuit, wherein the input digital signal is shifted from a second level to a first level.
An accumulator for returning the operation value to the initial value when the state changes to the level of, and a storage circuit for storing sine wave waveform digital data for one cycle in advance, and outputting the corresponding digital data using the output of the accumulator as a read address A digital-to-analog conversion circuit for converting the output of the storage circuit into an analog signal; a low-pass filter for extracting only a fundamental wave from the output of the circuit; and frequency setting means for setting the frequency specific value to the frequency of the input digital signal The second feature is a configuration having the following.

[0013]

According to the first feature, the input digital signal is delayed by one symbol, the exclusive OR with the input digital signal is obtained, and the clock is selectively derived when the level is the first level. The counter is reset when the input digital signal changes state from the second level to the first level, and the count output is used as a read address in a storage circuit in which sine wave waveform data is stored in advance. The corresponding data is read and converted to an analog signal to extract only the fundamental wave.

In the second feature, the input digital signal is delayed by one symbol to obtain an exclusive OR with the input digital signal, and the clock is selectively selected when the level is the first level. On the other hand, a value corresponding to the frequency of the input digital signal is latched by a latch circuit, and the held value is sent to an accumulator, and is cumulatively added according to the derived clock. When the state changes from the first level to the first level, the operation value is returned to the initial value, and the operation value is given as a read address to a storage circuit in which the sine wave waveform data is stored in advance, and the corresponding data is read out. Convert and extract only the fundamental wave.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the configuration of a digital waveform smoother circuit according to a first embodiment of the present invention. FIG.
, 1 is an input terminal, and the digital signal DS supplied to this terminal 1 is directly EX-OR (exclusive OR)
The signal is supplied to one input terminal of the gate circuit 2, is delayed by one symbol (T) by the delay circuit 3, and is supplied to the other input terminal of the EX-OR gate circuit 2. Further, it is supplied to a reset input terminal R of a counter 6 described later.

The output of the EX-OR gate circuit 2 is AN
It is supplied to one input terminal of a D (logical product) gate circuit 4. The clock CLK generated by the clock generator 5 is supplied to the other input terminal of the AND gate circuit 4.
The clock generator 5 generates a clock CLK which is sufficiently higher (10 times or more) than the input digital signal DS, and may use its own oscillator. Can be obtained by dividing the frequency. Here, for simplicity of description, it is assumed that m clocks are included in one symbol of the digital signal DS.

The output of the AND gate circuit 4 is supplied to the clock input terminal CK of the binary counter 6. The counter 6 counts the input clock CLK up to a maximum value of 2 m and outputs the count value. The count value is reset at the rise of the digital signal DS. The output of the counter 6 is used as a read address for a waveform generating RO.
M (read only memory) 7.

In the ROM 7, a sine wave waveform sin (θ) for one cycle (-π / 2 to + π / 2) is stored in advance at addresses 1 to 2m.
A data string corresponding to (−π / 2) (= cos θ) is stored. The output of the ROM 7 is converted into a voltage signal by a D / A (digital / analog) converter 8, and unnecessary high-frequency components (return frequency components and the like) are removed by a low-pass filter 9, which is derived from an output terminal 10. Is done. The operation of the above configuration will be described with reference to FIG.

Now, it is assumed that a digital signal DS based on the NRZ code as shown in FIG. This input digital signal DS is directly supplied to one end of the EX-OR gate circuit 2, and the delay circuit 3
As shown in FIG. 2B, the signal is delayed by one symbol and EX
Supplied to the other end of the OR gate circuit 2; EX-OR
The gate circuit 2 takes the exclusive OR of FIGS. 2A and 2B, thereby obtaining a waveform output as shown in FIG. 2C.

On the other hand, from the clock generator 5, FIG.
As shown in (g), m clocks CLK are generated in one symbol period of the input digital signal DS. This clock CLK is input to the AND gate circuit 4 together with the EX-OR output of FIG. The clock CLK is derived from the AND gate circuit 4 while the EX-OR output is at a high level, as shown in FIG. This clock CLK is supplied to the counter 6.

The counter 6 counts the clock CLK from the AND gate circuit 4 in order, and sends the count value to the ROM 7 as a read address of the ROM 7. However, the counter 6 is reset at the rising edge of the input digital signal DS, and its count value is set to “0”. 1
The number of clocks CLK included in a symbol is m,
The ROM 7 stores waveform data in the range of -π / 2 to 0 of cosθ from address “0” to “m” and waveform data in the range of 0 to + π / 2 of cosθ from “m + 1” to “2m”. It is remembered.

Here, the EX-OR output is high when each symbol of the input digital signal DS is inverted from the previous state. Therefore, if the symbols continue to be inverted, the EX-OR output becomes high level for two or more symbols, and the AND gate circuit 4 continuously outputs 2 m or more clocks. However, even in this case, since the counter 6 is reset when the count value reaches 2 m, the read address is 2
It does not exceed m and starts counting from 1. Therefore,
From the ROM 7, the waveform data of cos θ is sequentially read and output.

The EX-OR output is at a low level when each symbol of the input digital signal DS is in the same state as the previous state. During this period, the clock CLK is not output from the AND gate circuit 4, and the counter 6 stops counting. Therefore, the read address becomes constant, and the ROM 7 keeps reading the corresponding data.

When the output of the ROM 7 is converted into an analog signal by the D / A converter 8, a waveform signal shown in FIG. 2 (e) is obtained, which is passed through a low-pass filter 9 to extract a fundamental wave. The waveform signal shown in FIG. 2 (f) is obtained. This signal is a smoothing waveform of the input digital signal without any modification.

Therefore, the digital waveform smoother circuit having the above configuration uses one ROM as a signal source,
A smoothing waveform can be obtained simply by controlling the read address according to the symbol change of the input digital signal. For this reason, it is not necessary to prepare a plurality of signal sources unlike the related art, and it is not necessary to provide a switch for selecting the signal source for each symbol, and the bit rate of a digital signal used in recent satellite communication and the like is reduced. Therefore, the structure can be simplified, the size can be reduced, and the reliability can be improved.

In the above-described embodiment, since the timing of the clock CLK affects the output waveform, it is necessary to perform stable control so that m symbols are surely included in one symbol of the input digital signal DS and are synchronized. is there. FIG. 3 shows a specific configuration of the clock generator 5 that performs this control process.

In FIG. 3, reference numeral 51 denotes a bit clock regenerator for regenerating a bit clock BCLK shown in FIG. 2H from the input digital signal DS. This bit clock B
CLK is input to the phase comparator 52 and the 1 / m frequency divider 53
Is compared with the phase of the output clock. This phase comparator 52
Is converted into a voltage signal by a low-pass filter 54, and then becomes a control input of a voltage-controlled oscillator (hereinafter, referred to as VCO) 55.

The VCO 55 oscillates and outputs a clock having a frequency corresponding to the control voltage. The output clock is frequency-divided by the frequency divider 53 to 1 / m and sent to the phase comparator 52. At the same time, the clock generator 5
Is sent to the AND gate circuit 4 described above.

That is, the clock generator 5 constitutes a phase-locked control loop (hereinafter, referred to as a PLL), and converts a bit clock BCLK from an input digital signal DS.
And compares the phase of the output clock CLK with a clock obtained by dividing the output clock CLK by 1 / m. Based on the comparison result, the VCO 55
By controlling the oscillating frequency, the clock CLK included in m symbols in one symbol is generated while synchronizing with the input digital signal DS.

According to the above configuration, it is possible to stably control the timing of the clock CLK so as to ensure that m clocks are included in one symbol of the input digital signal DS and that they are synchronized.

In the case where digital signals having different bit rates are appropriately switched and handled, it is not impossible to realize even with the above configuration. However, the frequency of the clock CLK, that is, the number of clocks CLK in one symbol is determined by the input digital signal. Since it increases and decreases in proportion to the bit rate, it is necessary to use, for example, a D / A converter 8 that can perform high-speed conversion, and to control the cutoff frequency of the low-pass filter 9. Therefore, such a problem can be solved by configuring as shown in FIG. 4 and making the frequency of the clock CLK substantially equal.

In FIG. 4, a programmable frequency divider which can set a plurality of integer frequency division ratios m corresponding to various data rates is used as the 1 / m frequency divider 53, and the ROM 7 is previously set to the frequency division ratio m. Corresponding multiple waveform data (cos θ: -π / 2
≦ θ <+ π / 2) is stored. Frequency division ratio m of frequency divider 53
The waveform data selection of the ROM 7 can be set by the data rate switching signal CS. FIG. 5 shows an operation in the case of smoothing digital signals DS having different data rates in the above configuration.

Now, (a1), (a2), (a) in FIG.
Digital signals DS1, DS2, DS shown in 3) respectively
Consider the case where 3 is smoothed. Here, for the sake of simplicity, the frequency of the clock CLK is assumed to be constant, and the number m of clocks in one symbol is D
It is assumed that S1 is 4, DS2 is 6, and DS3 is 8.

First, three kinds of digital signals D to be handled in advance
S1, DS2, DS3 respectively corresponding to the first, second,
The third waveform data is stored in the ROM 7 in association with the division ratios m = 4, 6, and 8. Then, before the digital signal is input, the frequency division ratio m of the programmable frequency divider 53 is set to a value corresponding to the data rate by the data rate switching signal CS, and the waveform data corresponding to the read address of the ROM 7 is read. Is set as follows.

In order to smooth the digital signal DS1, the frequency division ratio m of the frequency divider 53 is set to 4. FIG.
As is clear from the above description, the output clock of the AND gate circuit 4 when the digital signal DS1 of 1) is input is as shown in FIG. 5B1. The counter 6 counts up according to the input clock, and is reset when it reaches eight. Since the ROM 7 has been switched to the read state of the waveform data corresponding to m = 4, when the data output obtained from the read address from the counter 6 is D / A converted, it becomes as shown by the solid line in FIG. 5 (c1). . By passing the D / A conversion output through the low-pass filter 9, a smoothing waveform as shown by a dotted line in FIG.

Next, when switching to the smoothing of the digital signal DS2, the data rate switching signal CS
The programmable frequency divider 53 is set to m = 6, and the ROM 7 is set to the second waveform data reading state. FIG. 5 (a2)
The output clock of the AND gate circuit 4 when the digital signal DS2 is input is as shown in FIG.
The counter 6 is reset when it reaches twelve. When the data output of the ROM 7 obtained by the read address from the counter 6 is D / A converted,
(C2) As shown by the solid line, the low-pass filter 9
, A smoothing waveform as shown by a dotted line in FIG.

The same applies to the case where switching to the smoothing of the digital signal DS3 is performed. The programmable frequency divider 53 is set to m = 8 by the data rate switching signal CS, and RO
M7 is set to the third waveform data reading state. FIG.
AND when digital signal DS3 of (a3) is input
The output clock of the gate circuit 4 is as shown in FIG. 5 (b3), and the counter 6 is reset when it reaches 16 and the data output of the ROM 7 is D / A converted.
(C3) As shown by the solid line, the low-pass filter 9
, A smoothing waveform as shown by a dotted line in FIG.

Therefore, according to the above configuration, when digital signals having different bit rates are appropriately switched and handled, the frequency of the clock CLK is substantially constant regardless of the bit rate of the input digital signal. There is no need to use a converter that can perform high-speed conversion processing and to control the cutoff frequency of the low-pass filter 9 as the converter 8.

In the above embodiment, the counter 6,
Although the ROM 7 for waveform generation and the D / A converter 8 were used, a high-speed signal generator DFS (Dire
ct Frequency Synthesiser) can also be used.
FIG. 6 shows an example of this DFS.

In FIG. 6, reference numeral 11 denotes the entire DFS, 111 denotes a frequency setting data input terminal, 112 denotes a clock input terminal, 113 denotes a reset signal input terminal, and 11 denotes a reset signal input terminal.
4 is an analog signal output terminal.

In the DFS 11, the latch circuit 1
15 is the frequency setting data FS0 to FS from the terminal 111
The data value N set by 29 is temporarily stored. The data N stored here is sent to an accumulator (arithmetic unit) 116. The accumulator 116 accumulates and adds the value latched by the latch circuit 115 by the number of clocks CLK from the terminal 112, and the operation value is returned to “0” by the reset signal RS.

The operation output of the accumulator 116 is sent to the sine wave generation ROM 117 as a read address. Sine wave waveform data is stored in the ROM 117 in the order of addresses, and when a read address from the accumulator 116 is received, data of the corresponding address is output. The output of the ROM 117 is converted into an analog voltage signal by a D / A converter (DAC) 118 and transmitted from a terminal 114.

In this circuit configuration, the reset of the accumulator 116 responds to the fall of the input signal.
As shown in the figure, the circuit includes a triangular wave generating ROM 119 and a multiplexer (MPX) 111.
0, DAC 1111, computing unit 1112, 1 for generating a rectangular wave
113 is provided, but is not used here, and a description thereof will be omitted.

That is, in the DFS 11, the number of steps N of the accumulator 116 is set by the data N latched by the latch circuit 115. Therefore, the read address changes in N steps, and the sine wave output frequency of the ROM 117 can be set arbitrarily according to the relationship with the clock CLK.

FIG. 7 shows an example in which the DFS 11 having the above configuration is used.
2 shows a configuration of a digital waveform smoother circuit corresponding to FIG. However, in FIG. 7, the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 7, the frequency selection data is supplied to the data input terminal 111 of the DFS 11, the output clock of the AND gate circuit 4 is supplied to the clock input terminal 112, and the inverter 12 is connected to the reset signal input terminal 113. An input digital signal DS is supplied via the terminal.
The output signal of the analog signal output terminal 114 is supplied to the low-pass filter 9.

In the above configuration, in the DFS 11, the frequency selection data is FS, the frequency of the clock CLK is Fi,
Bit rate of input digital signal DS is 1 / T, DFS
Assuming that the oscillation frequency is Fd, 2 × (1 / T) = Fd,
Fd = (Fi / 2 ²⁹ ) × FS holds. Then, T =
By setting the frequency of the frequency selection data N and the clock CLK to be 20 ³⁰ / (Fi · FS),
A sine wave signal synchronized with the input digital signal DS can be obtained.

More specifically, even in this configuration, similarly to the case of FIG. 1, the input clock C
LK is ON / OFF controlled by the EX-OR output, and the accumulator 116 corresponding to the counter 6 is reset by the rise of the input digital signal DS, that is, the fall of the output of the inverter 12.

Therefore, even if the symbols of the input digital signal DS continue to be inverted, the EX-OR output becomes high level for two or more symbols, and the AND gate circuit 4 continuously outputs 2 m or more clocks, the accumulator 116
Is reset when the operation value reaches 2 m, so that the read address does not exceed 2 m and changes from 0 to N steps anew. Therefore, the ROM 11
7 sequentially reads and outputs the cos θ waveform data.

The EX-OR output goes low when each symbol of the input digital signal DS is in the same state as the previous state, so that the clock CLK is not output from the AND gate circuit 4 and the accumulator 116 outputs The addition is stopped. Therefore, the read address becomes constant, and R
The OM 117 keeps reading the corresponding data.

The output of the ROM 117 is the D / A converter 1
The signal is converted into an analog signal by the low-pass filter 9.
And becomes only the fundamental wave component. This signal is a smoothing waveform of the input digital signal without any modification. According to this configuration, it is needless to say that the structure can be further simplified, and downsizing and improvement in reliability can be realized.

In the configuration of FIG. 7, in order to stably control so that m clocks CLK are included in one symbol of the input digital signal DS without fail and synchronized, it is necessary to use FIG.
The configuration may be exactly the same as that of the embodiment. FIG. 8 shows the configuration. The operation is the same as that of FIG. 3, and therefore, in FIG. 8, the same parts as those in FIG.

In each of the embodiments described above, the case where the input digital signal is a data string based on the NRZ code has been described. However, it is needless to say that the present invention can be applied to other encoding formats. In addition, various modifications may be made without departing from the spirit of the present invention, and the present invention can be similarly implemented.

[0055]

As described above, according to the present invention, it is possible to provide a digital waveform smoother circuit capable of smoothing the waveform of a high-speed digital signal with a simple structure, realizing miniaturization and improving reliability.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a basic configuration as an embodiment of a digital waveform smoother circuit according to the present invention.

FIG. 2 is a waveform chart for explaining the operation of the embodiment.

FIG. 3 is a block circuit diagram showing a circuit configuration for synchronizing clock generation with an input digital signal in the embodiment of FIG. 1;

FIG. 4 is a block circuit diagram showing a configuration for supporting a plurality of digital signals having different bit rates in the embodiment of FIG. 1;

FIG. 5 is a waveform chart for explaining the operation of the embodiment of FIG. 4;

FIG. 6 is a block circuit diagram showing a configuration example of a high-speed signal generator DFS used in another embodiment according to the present invention.

FIG. 7 is a block circuit diagram showing the configuration of another embodiment according to the present invention using the DFS of FIG. 6;

8 is a block circuit diagram showing a circuit configuration for synchronizing clock generation with an input digital signal in the embodiment of FIG. 7;

FIG. 9 is a block circuit diagram showing a configuration of a filter conventionally considered to be used for a digital waveform smoother circuit.

FIG. 10 is a waveform chart for explaining the operation of the circuit of FIG. 9;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Digital signal input terminal, 2 ... EX-OR gate circuit, 3 ... 1 symbol delay circuit, 4 ... AND gate circuit,
5: clock generator, 51: bit clock regenerator, 5
2: phase comparator, 53: 1 / m frequency divider, 54: low-pass filter, 55: VCO, 6: binary counter, 7:
ROM, 8: D / A converter, 9: low-pass filter, 1
0: smoother waveform output terminal, 11: DFS, 111 ...
Frequency setting data input terminal, 112: clock input terminal, 113: reset signal input terminal, 114: analog signal output terminal, 115: latch circuit, 116: accumulator, 117: ROM for sine wave generation, 118: DA
C.

Claims (7)

(57) [Claims] 1. A delay circuit for delaying an input digital signal representing data by a first and a second level by one symbol, a logic gate circuit for obtaining an exclusive OR of an output of the delay circuit and an input digital signal, A clock generation circuit for generating a clock having a frequency sufficiently higher than the frequency of the input digital signal; and selectively outputting an output clock of the clock generation circuit when an output signal of the logic gate circuit is at a first level. A clock deriving circuit, a counter for counting an output clock of the circuit, and returning the count value to an initial value when the state of the input digital signal changes from a second level to a first level; Sine wave waveform digital data for one period, twice as many as the number included in one symbol of the digital signal, is stored.
A waveform data storage circuit that outputs the corresponding digital data using the output of the counter as a read address, a digital-to-analog conversion circuit that converts the output of the waveform data storage circuit into an analog signal, and outputs only the fundamental wave from the output of this circuit. A digital waveform smoother circuit comprising a low-pass filter for extracting. 2. The digital waveform smoother circuit according to claim 1, wherein said clock generation circuit is controlled in synchronization with a bit clock of said input digital signal. 3. An oscillator for generating a clock having a frequency which is m times (m is a natural number) times the input digital signal and varying the frequency in accordance with a control signal, and an output of the oscillator. A frequency divider that multiplies by 1 / m, a phase comparator that compares the phase of the output clock of the frequency divider with the bit clock of the input digital signal, and controls the frequency of the oscillator based on the output of the phase comparator 3. The digital waveform smoother circuit according to claim 2, further comprising a frequency control unit that performs the control. 4. The frequency divider is a programmable frequency divider capable of arbitrarily setting m, and a plurality of sine wave waveform digital signals corresponding to a plurality of input digital signals having different bit rates are stored in the waveform data storage circuit. 4. A digital waveform smoother circuit according to claim 3, wherein data is stored, and further comprising bit rate switching control means for switching control of m setting of said frequency divider and data selection of a storage circuit according to an input digital signal. . 5. A delay circuit for delaying an input digital signal representing data by a first and a second level by one symbol, a logic gate circuit for obtaining an exclusive OR of an output of the delay circuit and an input digital signal, A clock generation circuit for generating a clock having a frequency sufficiently higher than the frequency of the input digital signal; and selectively outputting an output clock of the clock generation circuit when an output signal of the logic gate circuit is at a first level. A clock derivation circuit, a latch circuit for latching a frequency specific value, and a cumulative value of the latched value of the latch circuit according to an output clock of the clock derivation circuit;
When the input digital signal changes state from the second level to the first level, an accumulator for returning the operation value to an initial value, and sine wave waveform digital data for one cycle are stored in advance, and the output of the accumulator is read. A storage circuit that outputs corresponding digital data as an address, a digital-to-analog conversion circuit that converts the output of the storage circuit into an analog signal, a low-pass filter that extracts only a fundamental wave from the output of the circuit, Frequency setting means for setting the frequency of the input digital signal to the frequency of the input digital signal. 6. The digital waveform smoother circuit according to claim 5, wherein said clock generation circuit is controlled in synchronization with a bit clock of said input digital signal. 7. An oscillator for generating a clock having a frequency of m (m is a natural number) times the input digital signal, and varying the frequency in accordance with a control signal, and an output of the oscillator. A frequency divider that multiplies by 1 / m, a phase comparator that compares the phase of the output clock of the frequency divider with the bit clock of the input digital signal, and controls the frequency of the oscillator based on the output of the phase comparator 7. The digital waveform smoother circuit according to claim 6, further comprising frequency control means for performing the operation.