JP2765059B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and is particularly suitable for application to the manufacture of a highly integrated semiconductor integrated circuit device.

[Summary of the Invention]

The present invention provides a method of manufacturing a semiconductor device, comprising: forming an insulating film on a semiconductor substrate on which a first conductive type semiconductor region and a second conductive type semiconductor region are formed; Forming a first opening in a portion corresponding to the one conductivity type semiconductor region, forming a first conductivity type semiconductor film, and forming the first conductivity type semiconductor film and the insulating film in the first conductivity type semiconductor film and the insulating film; Forming a second opening in a portion corresponding to the semiconductor region of the second conductivity type; forming a semiconductor film of the second conductivity type; and forming the second opening at least until the semiconductor film of the first conductivity type is exposed. Patterning by etching back the two-conductivity-type semiconductor film, forming the conductor film, and etching the conductor film and the first-conductivity-type semiconductor film at least until the insulating film is exposed; Process and To Bei. Thus, the manufacturing process can be simplified, and the reliability of the wiring can be improved.

[Conventional technology]

Aluminum (Al) in semiconductor integrated circuit devices
For example, when the wiring such as the wiring and the underlying semiconductor region (diffusion layer) are conducted, the wiring is brought into contact with the semiconductor region through a contact hole formed in the interlayer insulating film. However,
Since the diameter of the contact hole has become finer with the miniaturization of the element, it has become difficult to embed the wiring inside the contact hole by only the conventionally used sputtering method. Therefore, in recent years, attention has been paid to a method of burying a metal formed by a CVD method inside the contact hole and forming a wiring such as Al thereon. As one of the methods, a method of embedding a W film in a contact hole by a selective CVD method of tungsten (W) is known. However, this W selective CVD method has many technical difficulties, such as insufficient selectivity due to the difficulty in suppressing the nucleus growth of W on the insulating film, and is currently established. Not a technology.

Therefore, recently, polycrystalline silicon (S) which has higher resistance than W in terms of film adhesion and easy growth is excellent.
i) A method of filling a contact hole with a film has attracted attention.

Japanese Patent Application Laid-Open No. 60-103646 discloses that a semiconductor crystal is selectively grown inside a contact hole formed on a semiconductor region by a vapor phase growth method, and impurities in the semiconductor region are removed during the vapor phase growth. A method of manufacturing a semiconductor device in which the semiconductor crystal is made to have the same conductivity type as that of the semiconductor region by diffusing the semiconductor crystal into the semiconductor crystal is disclosed.

[Problems to be solved by the invention]

In the conventional method of filling a contact hole with a polycrystalline Si film as described above, since the resistance of the polycrystalline Si film is considerably high, impurities are ion-implanted into the polycrystalline Si film after the polycrystalline Si film is buried inside the contact hole. It is necessary to reduce the resistance. For this reason, semiconductor regions having different conductivity types, for example, n ⁺ -type semiconductor regions and p ⁺ -type semiconductor regions exist in a semiconductor substrate, such as a CMOS LSI, and wiring is contacted to these semiconductor regions through contact holes. If necessary, after the polycrystalline Si film is buried inside these contact holes, n is added to the polycrystalline Si film buried inside the contact holes on the n ⁺ type semiconductor region.
It is necessary to selectively implant a p-type impurity and ions into the polycrystalline Si film embedded in the contact hole on the p ⁺ -type semiconductor region. Therefore,
In this case, two ion implantations, an n-type impurity and p
Two times of lithography are required to form a resist pattern for selectively ion-implanting a mold impurity. For this reason, conventional polycrystalline Si
The method of filling the contact holes with the film has a problem that the manufacturing process of the semiconductor device is complicated.

On the other hand, as the wiring, a wiring composed of only an Al film or a three-layer structure of Al / TiN / Ti using a titanium nitride (TiN) film and a titanium (Ti) film as a barrier metal is used. I have. However, there has been a problem that a wiring composed of only an Al film is easily broken by electromigration or the like. Further, in the wiring using the above-described barrier metal, even if the Al film is disconnected, the underlying TiN / Ti film portion may maintain electrical connection in some cases, but the thickness of the TiN / Ti film is usually Due to the small size and high resistance of TiN, Joule heat is remarkably generated when a current flows through the TiN / Ti film, and finally the TiN / Ti film is broken by this heat,
There is a problem that the wiring is completely disconnected.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of simplifying a manufacturing process when a semiconductor film such as a polycrystalline Si film is embedded in an opening formed on a semiconductor region having a different conductivity type. To provide.

Another object of the present invention is to provide a semiconductor device capable of improving the reliability of wiring when a semiconductor film such as a polycrystalline Si film is buried inside an opening formed on a semiconductor region having a different conductivity type. It is to provide a manufacturing method.

[Means for solving the problem]

In order to achieve the above object, the present invention relates to a method for manufacturing a semiconductor device, comprising a step of forming a semiconductor substrate (1) on which a first conductivity type semiconductor region (4) and a second conductivity type semiconductor region (5) are formed. Forming a first opening (C ₁ ) in a portion of the insulating film (6) corresponding to the semiconductor region (4) of the first conductivity type; Forming a one-conductivity-type semiconductor film (7), and forming a first-conductivity-type semiconductor film (7) and an insulating film (6) on portions corresponding to the second-conductivity-type semiconductor region (5). Forming a _second opening (C ₂ ), forming a second conductive type semiconductor film (8), and forming a second conductive type semiconductor film (7) at least until the first conductive type semiconductor film (7) is exposed. A step of etching back the film (8); a step of forming the conductor film (10);
0) and a step of patterning by etching the first conductive type semiconductor film (7) at least until the insulating film (6) is exposed.

[Action]

According to the above-described means, the first conductive type semiconductor film (7) and the second conductive type semiconductor film (8) are respectively provided inside the first opening (C ₁ ) and the second opening (C ₂ ). Since the semiconductor film can be directly buried, the semiconductor film is buried in the first opening (C ₁ ) and the second opening (C ₂ ) as in the prior art, and then the semiconductor film is formed in order to reduce the resistance of the semiconductor film. This eliminates the need for ion implantation of impurities into the film,
The semiconductor film embedded in the first opening (C ₁ ) and the second opening (C ₂ ) has a first conductivity type impurity and a second conductivity type impurity, respectively.
There is no need to form a resist pattern for selectively ion-implanting conductive impurities. This eliminates the need for two ion implantations and two lithography operations, which are conventionally required, thereby simplifying the semiconductor device manufacturing process.

Further, the conductor film (10) and the first conductivity type semiconductor film (7)
Is etched until at least the insulating film (6) is exposed, thereby forming wirings (11, 12) including the conductor film (10) and the semiconductor film (7) of the first conductivity type. In this case, even if the conductor film (10) constituting the wirings (11, 12) is broken due to electromigration or stress migration, the first conductive type semiconductor film (7) as the lower layer does not break. Since current can flow through the one-conductivity type semiconductor film (7), even if the conductor film (10) is disconnected, the wiring (11, 12)
Will not break. Therefore, this wiring (11,12)
Has excellent electromigration resistance and stress migration resistance. Thereby, the reliability of the wiring can be improved.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. This embodiment is an embodiment in which the present invention is applied to the manufacture of a CMOS LSI.

1A to 1I show a CMOS LS according to an embodiment of the present invention.
The manufacturing method of I is shown.

In this embodiment, as shown in FIG. 1A, a p-well 2 is first formed by ion-implanting a p-type impurity such as boron (B) into a semiconductor substrate 1 such as an n-type Si substrate. Form. Next, the surface of the semiconductor substrate 1 is selectively thermally oxidized to form a field insulating film 3 such as an SiO ₂ film, thereby performing isolation between elements. Next, a gate insulating film (not shown) such as an SiO ₂ film is formed on the surface of the active region surrounded by the field insulating film 3 by, for example, thermal oxidation. Next, for example, a polycrystalline Si film is formed on the entire surface by, for example, a CVD method, and an n-type impurity such as, for example, phosphorus (P) is doped into the polycrystalline Si film by an ion implantation method or the like to reduce the resistance. The polycrystalline Si film is patterned into a predetermined shape by etching to form a gate electrode (not shown). When the gate electrode is formed of a polycide film, patterning is performed after forming a high melting point metal silicide film such as a molybdenum silicide (MoSi ₂ ) film on the polycrystalline Si film. Next, for example, an n-type impurity such as As is ion-implanted into the p-well 2 using the gate electrode as a mask while the surface of the portion other than the p-well 2 is covered with, for example, a photoresist (not shown). Thus, for example, an n ⁺ -type semiconductor region 4 and an n ⁺ -type semiconductor region (not shown) located on the side opposite to the semiconductor region 4 with respect to the gate electrode are formed in self-alignment with the gate electrode. Thereafter, the photoresist is removed. The gate electrode,
With respect to the semiconductor region 4 and the gate electrode,
N-channel MOSFET
Is configured. Next, a p-type impurity such as B is ion-implanted into the semiconductor substrate 1 using the gate electrode as a mask while the surface of the p-well 2 is covered with, for example, a photoresist (not shown). p ⁺
Semiconductor region 5 and ap ⁺ type semiconductor region (not shown) located on the opposite side of semiconductor region 5 with respect to gate electrode
To form Thereafter, the photoresist is removed.
The p-channel MOSFET is constituted by the gate electrode, the semiconductor region 5 and the semiconductor region located on the opposite side of the semiconductor region 5 with respect to the gate electrode. The p-channel MOSFET and the above-mentioned n-channel MOSFET constitute a CMOS.

Next, as shown in FIG. 1B, an interlayer insulating film 6 such as a SiO ₂ film is formed on the entire surface by, eg, CVD.

Next, as shown in FIG. 1 C, and contact holes C ₁ By selectively etched by a portion corresponding to the semiconductor region 4 for example, reactive ion etching (RIE) method of the interlayer insulating film 6 Form.

Next, as shown in FIG. 1D, for example, an n-type polycrystalline Si film 7 is formed on the entire surface by, for example, a CVD method. In this case, the inside of the contact hole C ₁ is filled with the n-type polycrystalline Si film 7.

Next, as shown in FIG. 1E, a portion of the n-type polycrystalline Si film 7 and the interlayer insulating film 6 corresponding to the semiconductor region 5 is selectively etched away by, for example, RIE to form a contact hole C. Form ₂ .

Next, as shown in FIG. 1F, for example, a p-type polycrystalline Si film 8 is formed on the entire surface by, for example, a CVD method. In this case, the contact hole C ₂ is filled with the p-type polycrystalline Si film 8.

Next, the p-type polycrystalline Si film 8 is etched back by, for example, RIE until at least the n-type polycrystalline Si film 7 is exposed. As a result, as shown in FIG.
Si p-type polycrystalline Si film 8 on the film 7 is removed, p-type polycrystalline Si film 8 inside of this only the contact hole C ₂ is in a state of being left. Thereafter, a heat treatment for electrically activating impurities is performed in the semiconductor regions 4 and 5 and other semiconductor regions (not shown).

Next, as shown in FIG. 1H, for example, a TiN film 9 and an Al film 10 are sequentially formed on the entire surface by, for example, an evaporation method or a sputtering method. Here, the TiN film 9 is composed of the Al film 10 and the underlying n-type polycrystalline Si.
It is used as a barrier metal for preventing a reaction between the film 7 and the p-type polycrystalline Si film 8.

Next, the Al film 10, the TiN film 9, and the n-type polycrystalline Si film 7 are patterned into a predetermined shape by sequentially performing anisotropic etching at least until the interlayer insulating film 6 is exposed, for example, by RIE. Thereby, as shown in FIG. 1 I,
It is composed of an Al film 10, a TiN film 9, and an n-type polycrystalline Si film 7, and composed of a wiring 11 connected to the n ⁺ type semiconductor region 4, and an Al film 10, a TiN film 9, and an n-type polycrystalline Si film 7. , P ⁺ type semiconductor region 5
Is formed. The RIE reaction gas for forming these wirings 11 and 12 includes:
When etching the Al film 10 and the TiN film 9, for example, a BCl ₃ -based gas is used, and when etching the polycrystalline Si film 7, for example,
CHF _3- based gas is used.

As described above, according to this embodiment, n ⁺ -type n formed inside by CVD respective semiconductor regions 4 of the contact holes C ₁ and p ⁺ -type on the semiconductor region 5 of the contact hole C ₂ Since the polycrystalline Si film 7 and the p-type polycrystalline Si film 8 are buried, the polycrystalline Si film is buried in the inside of the contact hole as in the prior art, and a resist pattern is masked on the polycrystalline Si film to remove impurities. Does not need to be made n-type or p-type.
This eliminates the need for lithography and ion implantation for forming the resist pattern, and simplifies the manufacturing process accordingly.

Further, according to this embodiment, the wirings 11 and 12 are made of the Al film 10 and the T film.
Since it has a three-layer structure composed of the iN film 9 and the n-type polycrystalline Si film 7, it has the following advantages. FIG. 2 shows a state in which the Al film 10 is disconnected due to electromigration or stress migration, and FIG. 3 shows a plan shape of the wiring 12 in that state. As shown in FIGS. 2 and 3, even when the Al film 10 is disconnected,
In addition, even when the TiN film 9 is disconnected in the same manner, a current can flow through the lower n-type polycrystalline Si film 7 as shown by the arrow in the figure, and as a result, the wiring 12 is disconnected. It turns out that it does not reach. This is the same for the wiring 11. As a result, these wirings 11 and 12 have high reliability with excellent electromigration resistance and stress migration resistance, and as a result, the reliability of the LSI can be improved. The stress migration resistance of the Al film 10 is such that the Al film 10 is a polycrystalline Si film.
Since the Al film 10 is formed on the layers 7 and 8, the stress generated in the Al film 10 is also reduced.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible.

For example, in the above embodiment, the present invention
Although the description has been given of the case where the present invention is applied to the production of
For example, it can be applied to the manufacture of a bipolar CMOS LSI, of course, and more generally, it can be applied to all cases where a semiconductor film is embedded in a contact hole formed on a semiconductor region of a different conductivity type. Is possible.

〔The invention's effect〕

As described above, according to the present invention, the manufacturing process can be simplified and the reliability of the wiring can be improved.

[Brief description of the drawings]

1A to 1I are CMOS LSIs according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view for explaining a manufacturing method in the order of steps, FIG.
FIG. 3 is a plan view of the wiring in the state shown in FIG. Explanation of main reference numerals in the drawings 1: semiconductor substrate, 2: p well, 3: field insulating film, 4, 5:
Semiconductor region, 6: interlayer insulating film, 7: n-type polycrystalline Si film, 8: p-type polycrystalline Si film, 9: TiN film, 10: Al film, 11, 12: wiring.

Claims (1)

(57) [Claims] A step of forming an insulating film on a semiconductor substrate on which a first conductive type semiconductor region and a second conductive type semiconductor region are formed; and the first conductive type semiconductor region of the insulating film. Forming a first opening in a portion corresponding to the following; forming a first conductive type semiconductor film; and forming the second conductive type semiconductor of the first conductive type semiconductor film and the insulating film. Forming a second opening in a portion corresponding to the region; forming a second conductive type semiconductor film; and forming the second conductive type semiconductor film at least until the first conductive type semiconductor film is exposed. Etching back the semiconductor film; forming a conductive film; and patterning the conductive film and the semiconductor film of the first conductivity type by etching at least until the insulating film is exposed. Characterized by A method for manufacturing a semiconductor device.