JP2760565B2 - Time shift detection circuit - Google Patents

Description

The present invention relates to a technique for detecting a time lag used in a Y / C separation circuit of an IDTV or an EDTV having at least a large capacity memory having a frame capacity.

(B) Conventional technology In recent years, memories have become inexpensive, and it has become possible to provide inexpensively a television receiver (TV) with improved image quality using a field memory and a frame memory.

These TVs use these field / frame memories to perform inter-field processing or inter-frame processing.

As the inter-frame processing, the frame type Y / C separation is famous. When performing the above Y / C separation on these TVs, the frame type Y / C separation processing output and the in-field Y / C separation processing output are switched according to the magnitude of the motion of the image (or
The mixing ratio is variable). These signal processings are described in the following documents.

(A) “IDTV and Home Video Technology” on pages 62 to 74 of the magazine “Electronic Life, July 1988” published by The Japan Broadcasting Publishing Association. (B) “Nikkei Electronics, published by Nikkei McGraw-Hill, September 4, 1988. "High-definition television using digital technology, which is expected to become a pillar of next home appliances" on pages 123 to 143 of Nikkei, No. 403. (c) Magazine "TV Technology, June 1988" published by Electronic Technology Publishing Co., Ltd. "P.19-P32" Next-generation high-quality digital color television (NEC, IDTV system high-quality S digital television "C-29D70") (Toshiba, frame double scan system, digital television "30ID1").

These TVs control the frame memory by using a clock signal (mainly 4 · fsc) synchronized with the color subcarrier (fsc). These TVs operate normally when a standard color television signal conforming to a broadcasting standard is input.

For this reason, when a non-standard color television signal having no frame correlation in synchronization is input, inter-frame signal processing is stopped and only intra-field processing is performed.

This stop is performed, for example, when a time lag between frames occurs even for one clock (when the clock signal is 4 fsc), and the inter-frame processing is stopped.

For this reason, a Y / C separation circuit including a time axis correction circuit for correcting a time shift between frames can be considered.

(C) Problems to be Solved by the Invention The present invention provides a circuit for detecting an accurate time lag.

(D) Means for Solving the Problems The present invention provides a time lag detecting circuit (14) for detecting a time lag between two video signals, wherein a horizontal lag component of the two video signals is compared to determine a time lag. , A burst phase comparison circuit (66) for comparing the burst components of the two video signals to detect a phase shift, and an output of the synchronization phase comparison circuit (48) And a burst phase correction circuit (68) for correcting the output from the phase comparison circuit (66) and outputting the time lag data.

(E) Function According to the present invention, it is possible to detect even a slight time axis shift by comparing burst phases.

(F) Embodiment An embodiment of the present invention will be described with reference to FIGS. In FIG. 1, (10), (12) and (14) are circuits showing the features of the present invention, (10) is a variable delay circuit, and (1)
2) is a fixed delay circuit of 0.5H. (14) is a time axis shift detecting circuit which detects a time shift between frames and varies the delay time in the variable delay circuit (10) in order to correct the time shift. The circuits (10), (12) and (14) will be described later in detail.

Next, a conventional circuit will be described. (16) is a composite video signal input terminal. (18) is a PLL oscillation circuit which oscillates in synchronization with the burst signal in the composite video signal and outputs a clock signal four times (4fsc) the color subcarrier (fsc). The clock signal of the PLL circuit (18) is supplied to each circuit in the figure, but is not shown. (20) An A / D converter. (22) is a one-frame delay circuit composed of a frame memory.

(24) is a motion detection circuit. (26) is a non-standard / standard detection circuit. (28) and (30) are offset delay circuits having the same delay time, which are used to adjust the timing of controlling the signal in the Y / C separation circuit (32) by the signal indicating the amount of motion from the motion detection circuit (24). used.

(32) is a motion adaptive Y / C separation circuit. As is well known, the Y / C separation circuit (32) is controlled by a signal indicating the amount of motion from the motion detection circuit (26). When the signal indicating the standard / non-standard indicates the non-standard, the processing is fixed to the Y / C separation in the field.

 The operation of the above circuit will be briefly described.

The composite video signal input from the input terminal (16) is converted to an 8-bit digital signal by the A / D converter (20).

When a standard signal is input, the delay time of the variable delay circuit (10) is set at the same time as that of the fixed delay circuit (12) by the output of the time axis deviation detection circuit (14).

Therefore, one input of the Y / C separation circuit (32) is connected to the circuit (1
2) Input through (22) and (28), the other input is the circuit (1
0) Input through (30). And, as mentioned above,
The delay times of the fixed delay circuit (12) and the variable delay circuit (10) are the same, and two offset delay circuits (2
8) The delay time of (30) is the same.

Therefore, a composite video signal having a one-frame time difference is input to the Y / C separation circuit. Then, a motion-adaptive Y / C separation operation is performed in the same manner as in the related art using a signal indicating the amount of motion from the motion detection circuit.

Next, when a non-standard signal is input, the following operation is performed. The standard / non-standard detection circuit (26) outputs a signal indicating non-standard. If the time axis shift at this time is too large to be corrected, the time axis shift detection circuit (14) outputs a signal indicating non-standard to the Y / C separation circuit (32). The delay time of the variable delay circuit (10) at this time remains the same as that of the circuit (12). Then, the Y / C separation circuit (32) stops the motion adaptive Y / C separation as in the related art, and performs the Y / C separation by the intra-field processing.

If the time axis deviation is large enough to be corrected, the time axis deviation detection circuit (14) is replaced with the standard / non-standard detection circuit (26).
From the non-standard signal from the Y / C separation circuit (3
2) Output a signal indicating the standard.

The time axis deviation detecting circuit (14) detects the deviation of the time axis and corrects the delay time of the variable delay circuit (10) to correct the deviation.

 FIG. 3 shows the variable delay circuit (10).

(34) ... (34) are 909 delay elements, which delay one clock signal. The clock signal is 4f as described above.
sc, and this delay element group is a delay circuit for about one horizontal scanning period. (38) is a multiplex. (36)…
(36) is 910 gate circuits. That is, by turning on one of the gate circuits (36) by a signal from the time axis deviation detecting circuit (14), the composite digital video signal is delayed for a desired period.

This variable delay circuit (10) is used when a standard signal is input and when a non-standard signal is input so that time axis correction cannot be performed.
The delay acts as 455 clocks, that is, a 0.5H delay circuit.

FIG. 2 shows the time axis deviation detection circuit (14). First,
After explaining the main circuit of the time axis deviation detecting circuit, each circuit will be described.

(54) is a horizontal synchronization counter, and an input terminal (14b)
(14a) is a circuit for determining whether the signal is advanced or delayed with respect to one frame delay.

Reference numeral (48) denotes a synchronous phase comparison circuit that detects a deviation of an inter-axis by comparing phases of synchronous signals (particularly, horizontal synchronous signal components).

Reference numeral (66) denotes a burst phase comparison circuit that detects a phase difference between the burst signals of the signals at the input terminals (14b) and (14a) and detects a very small time-axis deviation.

(48) is a burst phase correction circuit that outputs an accurate time axis deviation detection signal based on the outputs of the synchronous phase comparison circuit (48) and the burst phase comparison circuit (66).

The synchronous phase comparison circuit (48) determines whether or not the time lag can be corrected. If not, a signal is output from the terminal (48a), the AND gate (74) is turned on, and the non- Pass the standard detection signal. The multiplexer (7
Select 0) to output a fixed delay value.

 Next, each circuit will be described.

(40) and (42) are low-pass filters that remove burst signals, color signals, and high-frequency noise. (44) (46)
Is a synchronization separation circuit, which performs separation detection by slicing an input signal.

The synchronous phase comparison circuit (48) detects the phase difference by comparing the phases of the two signals. (50) outputs a horizontal synchronization signal separation circuit, and (52) outputs a frame synchronization signal provided with a vertical synchronization signal separation circuit.

The horizontal synchronization counter circuit (54) compares the two signals. The horizontal synchronization counter circuit (54) is reset by the output of the vertical synchronization signal separation circuit (60) every frame period. Then, the horizontal synchronization signal is counted. In other words, if "525" is counted before being reset by the frame signal, the phase of (14a) viewed from (14b) is better than the one-frame delay, and if the count value is "524", it is delayed. . That is, the horizontal synchronization counter circuit (54) detects the delay and advance of the phase, and the synchronization phase comparison circuit (48)
Inform It should be noted that such phase advance / delay is unique to the signal source, and once determined, it hardly changes, and detection for each frame is sufficient.
Note that the phase comparison is performed every horizontal period.

(50) and (52) are burst gate pulse generation circuits. (54) and (56) are bandpass filters for separating burst signals. (58) and (60) are burst gate circuits. (62) and (64) are chrominance subcarrier generation circuits for making the burst signal continuous in time.

The burst phase comparison circuit (66) compares the phases of the burst signal components. This is because a highly accurate time axis deviation cannot be detected only by comparing the phases of the synchronization signals.
In this embodiment, since the clock signal is 4fsc, this circuit (66) outputs -1, 0, +
Either of 1, +2 is output.

The burst phase correction circuit (68) corrects the output of the synchronous phase comparison circuit (48) based on the output of the burst phase comparison circuit (66), and outputs accurate time lag information data.

The multiplexer (70) switches and derives the data from the burst phase correction circuit (68) and the data "455" from the fixed delay value setting circuit (72). (74) is an AND gate.

The synchronous phase comparison circuit (48) outputs a signal from the terminal (48a) when the correction fee for the time lag is within ± 455 clocks, closes the AND gate (74), and detects the non-standard signal. Stop output and use multiplexer (70)
And outputs the output data of the burst phase correction circuit (68) to the variable delay circuit (10).

 The operation of the above circuit will be briefly described.

The horizontal synchronization component from the input terminal (14a) and the input terminal (1
By comparing the vertical synchronization component from 4b) with the horizontal synchronization counter (54) to detect the advance or delay of the phase, and comparing the horizontal synchronization components of both signals with the synchronization phase comparison circuit (48), the approximate time lag is obtained. Is detected.

Then, the phase difference between the bursts of both signals is detected by a burst phase comparison circuit (66). The burst phase correction / comparison circuit (68) corrects and outputs the output of the synchronous phase comparison circuit (48) with the burst phase comparison circuit (66), and controls the variable delay circuit (10) with this data. .

(G) Effect of the Invention As described above, according to the present invention, accurate time lag data can be created.

[Brief description of the drawings]

FIG. 1, FIG. 2, and FIG. 3 are views showing an embodiment of the present invention. (14)… time lag detection circuit, (48)… synchronous phase comparison circuit, (66)… burst phase comparison circuit, (68)… burst phase correction circuit.

Claims (1)

(57) [Claims] A time lag detecting circuit (1) for detecting a time lag between two video signals before and after a predetermined frame delay inputted.
In 4), a synchronization phase comparison circuit (48) for detecting a time lag by comparing horizontal synchronization components of two video signals before and after the input predetermined frame delay, and A burst phase comparison circuit (66) for comparing the burst components of the burst signals of the two video signals to detect a phase shift; and correcting the output of the synchronous phase comparison circuit (48) with the output of the burst phase comparison circuit (66). And a burst phase correction circuit (68) for outputting a time lag data.