JPH01268292A - Time base correcting device for reproducing composite video signal - Google Patents

Abstract

PURPOSE:To prevent the dynamic range of a phase comparator from being dislocated at the operating point of a burst signal loop by detecting the allowing operation range over of the operating point in the burst signal loop, controlling the gain of the burst signal loop and setting the operating point in the allowing operation range. CONSTITUTION:During a high level period on the logic of a level detecting means 13 output, a gain control means 14 causes the gain of the burst signal loop to go up by several dB higher than the regular gain and fluctuates the operating point with slightly generating oscillation. Then, when the output of the level detecting means 13 goes to be a low level on the logic, the gain is returned to be the regular gain. When the output of the level detecting means 13 goes to be the high level, the regular gain of the burst signal loop is momentaneously decreased by tens dB. Then, when a constant time passes after such a condition is obtained, the gain is gradually increased so as to be the regular gain. Thus, the allowing operation range over of the operating point in the burst signal loop is detected and the gain of the loop is controlled by a detecting signal. Then, the operating point can be set in the allowing operation range.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time axis correction device for a reproduced composite video signal used in a video disc player or the like.

[Conventional technology]

In a video disc player or the like, if the disc is eccentric or distorted, the time axis of the reproduced video signal differs from that at the time of recording, causing image blur or the like on the reproduced screen. Therefore, the amount of time axis fluctuation of this reproduced video signal is detected,
It is necessary to correct the amount of time-axis fluctuation of the reproduced video signal using a time-axis correction device so that this value falls within a permissible value.

An outline of such a conventional time axis correction device will be explained using FIG. In FIG. 6, the disk 31 is the morph 32.
It is driven by and rotates. Reference numeral 33 denotes an optical head for information detection, which generally includes a focus and tracking servo system and detects information recorded on the disk 31. Recorded information is generally information recorded in the form of a video FM signal,
The signal is passed through an M demodulator 34 and converted into a reproduced video signal 35.

The reproduced video signal 35 is accompanied by time axis fluctuations due to eccentricity of the disk and the like. The reproduced video signal 35 is corrected for the amount of time base variation by a time base correction circuit system 36, and the video signal is reproduced.

The time axis correction means in this time axis correction circuit system 36 is as follows:
A method of correcting the irradiation spot by changing it in the track tangential direction using an actuator, a method of using a CCD (charge-coupled device) as a variable delay element and performing time axis correction according to the variable delay amount, or a method of using a random access memory. There are methods of correcting the time axis by controlling the write and read timings.

Further, there are the following methods for detecting the amount of time axis variation and controlling the time axis correction means.

That is, a reproduced horizontal synchronization signal and a reproduced burst signal are each extracted from the reproduced video signal, and the phase of each extracted signal is compared with a reference signal to detect the amount of time axis variation. and a feedback servo system that adds the time axis variation amount for the horizontal synchronization signal and the time axis variation amount for the burst signal, and controls the time axis correction means so that the added sum output signal becomes zero. There is.

In this time axis correction control system, the time axis correction means is controlled so that the addition output signal is always approximately zero. Furthermore, in the phase comparison of the reproduced horizontal synchronizing signal with respect to the reference signal and the phase comparison of the reproduced burst signal with respect to the reference signal, the phase comparison of the reproduced burst signal generally has higher comparison sensitivity, but the comparison period is narrower at about 280 n5ec. Therefore, even a slight change in the phase comparison output of the reproduced horizontal synchronization signal appears as a large fluctuation in the phase comparison output of the reproduced burst signal. Especially in double-speed playback where a track jump is performed every time a vertical synchronization signal is detected, the playback horizontal synchronization signal loop is held at the previous value for several H periods (IHil horizontal signal period) after the track jump, and when the previous value hold is released. The small fluctuations observed may accumulate at each track jump, and the system may become locked in a state in which the dynamic range of the phase comparison means for the reference signal of the reproduced burst signal is exceeded. However, in such a case, only the reproduction horizontal synchronization signal loop is operating, so accurate time axis correction cannot be performed.

As a countermeasure against this problem, conventionally, as shown in Japanese Patent Application Laid-open No. 102182/1982, PLL (P ja, se Lock
edL oop ) circuit is used, and the PLL circuit eliminates large fluctuations in the reproduced burst phase comparison output in response to small fluctuations in the reproduced horizontal synchronization signal, thereby eliminating over-dynamic range of the burst signal phase comparison means.

[Problem to be solved by the invention]

However, as mentioned above, the above conventional technology uses a PLL circuit to detect the time axis error of the reproduced burst signal, so the response characteristics of the PLL loop and the error detection ability are closely related to each other, and the circuit design There were many difficult aspects. Furthermore, in order to configure a PLL circuit, a high-precision voltage-controlled crystal oscillator is required, which makes the circuit complicated.
It also has the disadvantage of high cost.

An object of the present invention is to eliminate the drawbacks of the prior art as described above, and to prevent malfunctions caused by disturbances that cause the operating point of a burst signal loop to exceed the allowable operating range, and to achieve this with a simple configuration. An object of the present invention is to provide a time axis correction device for a composite video signal.

[Means to solve the problem]

In order to achieve the above object, the gain of the burst signal loop is determined by a level detecting means for detecting the absolute value level of a phase error output obtained by performing a phase comparison of a reproduced burst signal with a reference signal, and an output of the level detecting means. A simple configuration was adopted that included a gain control means for controlling the .

[Effect]

The level detection means is centered at zero volts as the phase error output of the reproduced burst signal, and from there the absolute value level is approximately just before saturation of the dynamic range of the phase comparator, or equivalent to several tens of percent or more of the dynamic range. Detects the absolute value level, and at the time of detection, the logical H4gh
level, and outputs a logical low level when no detection is detected. The gain control means increases the gain of the burst signal loop several dB higher than its normal gain during the logical high level period of the output of the level detection means, and changes the operating point to almost oscillate. When the output of the means reaches a logical low level, the gain is returned to the normal gain. Alternatively, when the output of the level detection means reaches a logical high level, the normal gain of the burst signal loop is instantly reduced by several tens of dB, and then the gain is gradually increased so that the normal gain is reached after a certain period of time has elapsed. to rise.

Thereby, it is possible to detect whether the operating point of the burst signal loop exceeds the allowable operating range, and to control the gain of the loop using the detection signal to set the operating point within the allowable operating range.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

The figure shows an embodiment using a random access memory as a time axis correction means, and the configuration is an A/D converter 1, a memory 2, a D/A converter 3, a write clock generator 4, a write address controller 5. , a read clock generator 6, and a read address controller 7.

The A/D converter 1 receives a reproduced video signal 35 from a video disc (not shown), converts the analog quantity into a digital quantity, and supplies the digital quantity to the memory 2. The write clock generating section 4 detects the amount of time axis fluctuation of the reproduced video signal 35, and generates a clock whose frequency is changed according to the detected amount.
/D converter 1 and memory? supply to. The write address control unit 5 generates a signal for controlling the write address of the memory 2 based on the clock from the write clock generation unit 4 and a signal frequency-divided by 910 (for one horizontal period). The memory 2 captures and records the reproduced video signal 35 according to each signal supplied to the memory 2 described above.

The read clock generating section 6 is configured with a high-precision crystal oscillator, etc., and generates a read clock signal, and the memory 2. A clock signal is supplied to the D/A converter 3 and the read address control section 7. The read address control unit 7 is
Generates a memory read address signal for memory 2. The memory 2 reads recorded information based on the reproduced video signal 35 using the read clock signal and the read address signal described above, and supplies the read information to the D/A converter 3. The D/A converter 3 converts the digital amount of the reproduced video signal 35 into an analog amount and outputs it. The signal output in this way is written using a clock signal that reflects the amount of time axis variation and then read out using a highly accurate clock signal, so it becomes the video signal 36 with the amount of time axis variation corrected. .

Furthermore, the write clock generating section 4 will be described in detail. A reproduced video signal 35 from a disk (not shown) is supplied to a reproduced horizontal synchronizing signal separation circuit 8 and a reproduced burst signal separation circuit 9. The reproduced horizontal synchronization signal separation circuit 8 extracts only the reproduced horizontal synchronization signal from the reproduced video signal 35 and supplies it to one input side of the phase comparator IO. The phase comparator 10 is
For example, it is a travel-type phase comparator, and the other input side is supplied with signals f and I (fH-15,75 KHz), which are frequency-divided (1/910) of the output of a voltage-controlled oscillator 16, which will be described later. The phase error between the two inputs is converted into a voltage and appears on the output side, which is supplied to one ' input side of the adder circuit 12. The reproduced burst signal separation circuit 9 extracts only the reproduced burst signal and supplies it to one input side of the phase comparator 11. The phase comparator 11 is, for example, a logic circuit EX-O.
The other input side of the phase comparator is a phase comparator consisting of R, and the other input side receives a signal f sc (f
scζ3.58 MHz) is supplied. Then, the phase error between the re-inputs is converted into a voltage and appears on the output side, which is supplied to the level detection section 13 and the gain control section 14.

When the output level of the phase comparator 11 is centered around zero and exceeds a level of several tens of percent of the dynamic range of the phase comparator 11, the level detector 13 detects a logical high level.
If the level is lower than that, a logical low level is output, and the output signal is supplied to the control input terminal of the gain control section 14. The gain control section 14 includes the level detection section 1
3 controls the gain of the output signal of the phase comparator 11 and supplies it to the other input side of the adder circuit 12. Addition circuit 12 adds the output signal of phase comparator 10 and the output signal of gain control section 14, and supplies the resulting output signal to voltage controlled oscillator 16 through phase compensation circuit 15 as a control voltage. According to the supplied control voltage, the voltage controlled oscillator 16 changes its oscillation frequency and outputs it, and the l/910 frequency divider 17 and the 1/4 frequency divider 18
supply to.

The output of the 1/910 divider 17 is fed to the other input of the phase comparator 10, and the output of the 1/4 divider 18 is a feedback feed to the other input of the phase comparator 11. It has a control system configuration.

FIG. 2 shows the level detection section 13 and gain control section 14 described above.
FIG. 2 is a configuration diagram showing a more detailed example. In the figure, a comparator 19 detects a voltage level of +x (V) or more as the signal level from the phase comparator 11,
A comparator 20 detects a voltage level below -x (V). The respective outputs are supplied to the OR circuit 0R21. The analog switch 22 is controlled by the logical output signal of the OR circuit 0R21, and the operational amplifier OP-AM
Switch the input resistance value of IR25. Since the gain of the OP-AMP25 can be set by the ratio of the input resistor R6 or R1 and the parallel resistor R2, the gain is controlled by the logical output signal of the OR circuit 0R21.

That is, when the logic output of the OR circuit 0R21 is at a low level, the OP-AMP25 is connected to the input resistance R0 and the parallel resistance R.
2 is obtained, and the OR circuit 0R2 is obtained.
When the logic output of 1 is at a high level, the switch 22 switches and the OP-AMP 25 connects the input resistance R and the parallel resistance R.
A gain G2 determined by the ratio with 2 is obtained.

Next, the operation of the circuit shown in FIG. 1 will be explained in more detail using FIGS. 4 and 2. Incidentally, FIG. 4 is an operational waveform diagram of signals of various parts that occur when the specific circuit shown in FIG. 2 is used in FIG. 1.

In FIG. 4, when the waveform of the output signal of the phase comparator 10 moves slightly in the positive direction due to a track jump a performed during double-speed playback, etc., the phase comparator 1
The waveform of the output signal C of No. 1 fluctuates by the amount of the phase of the aforementioned waveform, but since the phase comparison sensitivity is several tens of times higher than that of the phase comparator 10, the waveform of the output signal C fluctuates more than the waveform C. When this amount of variation reaches a voltage level of, for example, 20% or more of the dynamic range of the phase comparator 11 (±x (V)), the level detection unit 13 operates and outputs a logical high level as the level detection output d. do. As a result, the analog switch 22 switches the input resistance of the OP-AMP 25 from Ro to R, so the gain of the OP-AMP 25 becomes as shown in waveform e, and the gain of the burst signal loop is stepped up from 01 to 02. let This reduces the phase margin of the burst signal loop, increases the instability of the system, and causes the operating point of the phase comparator 11 to fluctuate. When the level of the output C waveform of the phase comparator 11 becomes equal to or less than ±x (V) of the level detector 13, the output of the level detector 13 becomes logically LO- level, and the gain returns to G1, making the system stable. Become.

The above operation is an instantaneous event that is completed within several tens of m5ec. Therefore, even if the dynamic range of the burst signal phase comparator 11 is exceeded, the state can be returned to normal instantly without continuing.

FIG. 3 is a block diagram showing yet another specific example of the level detection section 13 and gain control section 14, in which gain control is performed by a method different from that of FIG. 2.

In Fig. 3, FET24 (voltage control element) is newly added in place of human resistors R6 and R1 of OP-AMP25.
A gate voltage setting unit 23 is provided to control the gate voltage of the FET 24. First, only the operation of the gate voltage setting section 23 will be explained. Constant current source I constantly supplies current to capacitor C. analog switch 22
turns on when the output from the OR circuit 0R21 is logically at a high level, and discharges the charge in the capacitor C.

At this time, the voltage across the capacitor C becomes zero V, and the same voltage is applied to the FET 24 through the operational amplifier OP-AMP30.
supply to the gate.

Next, when the output of the OR circuit 0R21 becomes a logical Low level, the analog switch 22 is opened and the current from the constant current source I flows into the capacitor C. The voltage across the capacitor C increases in proportion to time, but when it reaches the Zener voltage of the Zener diode D, the current from the constant current source I flows through the Zener diode, so it does not increase beyond that.

The internal resistance value of the FET 24 can be changed by changing the gate voltage in this manner. Therefore FET2
The gain of the OP-AMP 25 can be changed by changing the gate voltage of 4. That is, by setting the gain of the OP-AMP 25 to 00 when the voltage across the capacitor C is zero and setting the gain to G1 when the Zener voltage is applied, the gain becomes G,
It can be changed gradually from to G.

FIG. 5 is an operational waveform diagram of various signals generated when the specific circuit shown in FIG. 3 is used in FIG. 1.

In FIG. 5, the operation from the occurrence of the track jump a until the output d of the level detection section 13 becomes a logical high level is the same as the operation shown in FIG. Thereby the gain of the burst signal loop is G.

From G. set so that the burst signal loop is mostly off.

Therefore, the PLL system essentially consists of only the horizontal synchronizing signal loop, and since there is no disturbance from the burst signal loop, the PLL system instantly tries to return to the normal state.

In conjunction with this, the output of the phase comparator 11 also tries to return to zero, so the waveform of the level detection output d has a shorter pulse width than that shown in FIG.

When the waveform of the level detection output d reaches the logical LO- level, the gain slowly increases as described above in the explanation of FIG. 3, and finally returns to the normal gain G+. Due to this slow operation, the waveform of the output C of the phase comparator 11 is
Since the level fluctuation is within the permissible operating range, the burst signal loop will not malfunction.

From the above, it is possible to detect that the operating point of the burst signal loop exceeds the allowable operating range, and control the gain of the loop using the detection signal to set the operating point within the allowable operating range. Moreover, its configuration is simple.

Although the level detection range is set to several tens of percent or more of the dynamic range of the phase comparator 11, it is not limited to this.
It's fine to be just around the edge of the dynamic range.

Further, although this embodiment uses a comparator, there is no problem in operation even if this comparator is replaced with a comparator with hysteresis.

〔Effect of the invention〕

According to the present invention, it is possible to detect that the operating point of the burst signal loop exceeds the allowable operating range, and use the detection signal to control the gain of the burst signal loop to set the operating point within the allowable operating range. This has the effect of preventing the dynamic range of the phase comparator at the operating point of the burst signal loop from shifting due to disturbance of the reproduced horizontal synchronizing signal loop at the time of a track jump, and also has the effect of being able to do this with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a time axis correction device as an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of the level detection section and control gain section in FIG. 1, and FIG. 4 is a circuit diagram showing a specific example of the circuit shown in FIG.
FIG. 6 is a schematic block diagram of a conventional time axis correction device. Explanation of symbols 10.11... Phase comparator, 12... Adder, 13
... Level detection section, 14... Gain control section, 19.2
0... Comparator, 22... Analog switch,
23...Gate voltage setting section, 24...FET agent Patent attorney Akio Namiki

Claims (1)

[Scope of Claims] 1. Horizontal synchronization signal extraction means for extracting a horizontal synchronization signal in a reproduced composite video signal, burst signal extraction means for extracting a burst signal in the reproduced composite video signal, and the horizontal synchronization signal extraction means a first phase comparing means for comparing the horizontal synchronizing signal extracted by the means with a reference phase to detect and output a phase error; a second phase comparison means for detecting and outputting a phase error; a level detection means for detecting an output level from the second phase comparison means;
gain control means for controlling the gain of the output of the second phase comparison means based on the output of the level detection means; and addition means for adding the output of the first phase comparison means and the output of the gain control means. , and time axis correction means for correcting the time axis of the reproduced composite video signal under the control of the output from the adding means. 2. In the time axis correction device for a reproduced composite video signal as set forth in claim 1, the gain control means comprises a circuit that switches the gain between high and low according to the logic level taken by the output of the level detection means. A time axis correction device for a reproduced composite video signal, characterized in that: 3. In the time axis correction device for a reproduced composite video signal as set forth in claim 1, the gain control means instantaneously reduces the gain using the output of the level detection means as a trigger, and then gradually decreases the gain. 1. A time axis correction device for a reproduced composite video signal, comprising a gain control circuit that restores the original gain.