JP2755842B2 - Superheterodyne receiver and its adjusting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superheterodyne receiver in which a voltage variable capacitance element such as a variable capacitance diode is included as a component of a tuning circuit, and an adjustment device therefor.

[0002]

2. Description of the Related Art A schematic configuration of a conventional superheterodyne receiver is shown in FIG. This receiver has a known configuration suitable for being configured by an integrated circuit. In the figure, the input from the antenna 31 is the antenna tuning circuit 3
2. The signal passes through a high-frequency amplifier circuit 33 and a high-frequency tuning circuit 34 and is supplied to a mixing circuit 35. On the other hand, the local oscillation circuit 4
The output from 1 is supplied to a frequency dividing circuit 42, which divides the frequency up to a certain reference frequency based on the frequency dividing data supplied from the system controller 43. The signal of the reference frequency is generated by a reference oscillation circuit 44 which is constituted by a crystal oscillation circuit and generates a signal of an accurate and stable frequency, and is obtained by frequency division by a frequency division circuit 45. Outputs of the frequency dividers 42 and 45 are input to a phase comparator 46.
The phase comparator 46 derives a DC output proportional to the phase difference between the two signals and supplies the DC output to the resonance circuit 40. Resonance circuit 40
Operates as a tank circuit of the local oscillation circuit 41 and includes a variable capacitance diode that is a variable voltage capacitance element. The resonance circuit 40 and the local oscillation circuit 41 operate as a variable voltage oscillator, so-called VCO. The local oscillation circuit 41 configured as described above controls a so-called phase-locked loop (abbreviated as “PLL”) by forming a feedback loop that attempts to match the phases of the outputs from the frequency dividers 42 and 45. Is performed, and the stability of the oscillation frequency of the local oscillation circuit 41 becomes equivalent to the crystal oscillator of the reference oscillation circuit 47. The system controller 43 arbitrarily specifies the oscillation frequency of the local oscillation circuit 41 by arbitrarily changing the frequency division ratio of the frequency division circuit 42, and is in a reception frequency band specified as a radio broadcast receiver. It is well known that a broadcast station of an arbitrary frequency can be received with high accuracy. This frequency is displayed by the display means 47.

The mixing circuit 35 mixes the output from the local oscillation circuit 41 and the received signal, generates an intermediate frequency signal, and amplifies the signal by the intermediate frequency amplifier circuit 36. The amplified intermediate frequency signal is further demodulated as an acoustic signal by the demodulation circuit 37, and the speaker 39 is driven by the low frequency amplification circuit 38 to be acoustic.

On the other hand, the tuning circuits 32 and 34 for the antenna (abbreviated as "ANT") and the high frequency (abbreviated as "RF") need to be tuned accurately to the desired receiving frequency. Within the required reception band, tracking is adjusted with a fixed frequency difference between the tuning frequency of the tuning circuits 32 and 34 and the oscillation frequency of the local oscillation circuit 41. For this reason, similarly to the resonance circuit 40, it is configured to include a voltage variable capacitance element, and the DC voltage from the phase comparison circuit 46 is applied. In the receiver having such a configuration, the channel selecting means can be constituted by digitizing without using a so-called variable condenser, which is a mechanical variable capacitor. It is widely used because of its good frequency stability.

The tuning circuits 32 and 34 shown in FIG. 8 generally have a circuit configuration as shown in FIG. That is, based on a resonance circuit composed of an inductor 101, a variable capacitance diode 102, and a bypass capacitor 103, a temperature correction capacitor 104 and a variable capacitance capacitor 105 called a trimmer are added. The DC voltage for setting the capacitance of the variable capacitance diode 102 is
6 through a terminal 107. The input to the resonance circuit is provided to terminals 108 and 109, and the selected frequency component is extracted from terminals 110 and 111. Although the resonance circuit 40 shown in FIG. 8 is also basically constituted by the resonance circuit shown in FIG. 9, the oscillation frequency must always be shifted by the intermediate frequency from the desired reception frequency. , A so-called putting capacitor. This difference in operation depends on the capacitance value of the capacitor 103. When the capacitance value is sufficiently larger than the capacitance value of the variable capacitance diode 102, the capacitance value of the series circuit of the variable capacitance diode 102 and the capacitor 103 is determined by the capacitance of the variable capacitance diode 102, but the capacitance of the capacitor 103 is too small. This is because when it is not large, it also affects the capacitance value of the series circuit. In this way, the tuning circuits 32, 34
And the resonance frequency of the tuning circuit 40 changes in a state in which tracking is performed so as to maintain a constant intermediate frequency difference,
Perform tuning operation.

[0006]

A conventional superheterodyne receiver constructed as shown in FIG. 8 has a problem in that when the mass production is to be carried out, the electrical characteristics of the individual components vary from the rated values. In order to obtain the optimum performance, adjustment is required.

First, a variable capacitance diode used as a channel selecting means has a large variation in DC voltage-capacitance characteristics. In general, a method is used in which a tracking error is prevented as much as possible by selecting and using a variable-capacitance diode having desired characteristics as much as possible as a variable-capacitance diode for desired frequency tuning and a local oscillation circuit. The variable capacitance diodes selected in this way have a characteristic difference that cannot be ignored from the variable capacitance diodes of the other selected combinations, and a variable capacitance capacitor 105 is provided to absorb this difference. It is necessary to correct the capacitance. In addition, when wiring and mounting individual components, stray capacitance always occurs, and this capacitance varies among individual receivers. Therefore, it is necessary to absorb this capacitance together with the variable capacitor 105.

On the other hand, it is very difficult to produce the inductor 101 with the inductance fixed at a constant value. Also, even if a high-precision inductor can be realized, there is a variation in stray inductance that occurs at the stage of mounting the inductor.After all, after the wiring assembly of each receiver is completed, the optimum receiving performance is obtained. It is necessary to move a core or the like provided on the inductor 101 to adjust the inductance to an optimum value.

The resonance circuit shown in FIG. 9 has a variable capacitance and a variable inductor, and these variable means are mechanically realized. Therefore, there is a limit to downsizing these. In particular, when almost all the active elements constituting the receiver are integrated circuits, the presence of the mechanically variable structure of inductors and capacitors becomes a major obstacle in miniaturizing and mass-producing the receiver.

As a method for automatically correcting the variation in the electrical characteristics of the tuning circuit element to obtain an optimum tracking state, there is a prior art disclosed in Japanese Patent Publication No. 62-34177. In this prior art, the automatic tracking adjustment function is operated every time the reception frequency is set, so that it is possible to absorb variations in the tuning circuit elements. There is a problem that it takes time to adjust until it becomes a state, and it is difficult to use. Also, a D / A circuit as a DC voltage generator to be given to the voltage variable capacitance diode
Since only the optimum DC voltage for each tuning circuit obtained by the D / A circuit is provided as an analog voltage by the sample and hold circuit, there is a problem that the circuit configuration becomes complicated.

An object of the present invention is to provide a superheterodyne receiver which does not include any mechanical variable means, has a simple circuit configuration, and can be easily miniaturized. The purpose of the present invention is to provide an adjusting device which can be adjusted by the above.

[0012]

[0013]

[0014]

[0015]

SUMMARY OF THE INVENTION The present invention provides a superheterodyne receiver that mixes a received signal with a signal from a local oscillator, converts the signal to an intermediate frequency, and then demodulates the signal. Signal generation control means for generating a digital signal representing the received signal and demodulating the received signal, and generating a signal having a frequency different from the frequency to be received by an intermediate frequency in response to the digital signal from the signal generation control means. A local oscillation unit for performing the operation, and each of the tuning circuits includes an inductor and a voltage variable capacitance element, and is configured to vary a voltage applied to the voltage variable capacitance element to select a reception signal. A tuning circuit capable of changing the resonance frequency, and an electrically rewritable read-only memory, wherein each of the tuning circuits is provided at the predetermined frequency interval. Digital data representing a voltage to be applied to the voltage variable capacitance element of the adjustment circuit is stored in advance. Such a read-only memory and a read-only memory which responds to a digital signal from the signal generation control means and is read-only based on a frequency to be received. Voltage conversion means for reading the stored contents of the memory, applying an analog voltage converted from the read digital data to the voltage variable capacitance element of each tuning circuit, electric field intensity detection means for detecting the electric field intensity of the received signal, Counting means for counting the converted intermediate frequency signal, the signal generation control means has a search function to sequentially change the frequency within a predetermined frequency range, during the search operation, the voltage conversion means, The contents of the store read from the read-only memory are changed at a predetermined ratio and then converted to the analog voltage, and the signal generation control is performed. The means responds to the output from the electric field strength detecting means and the counting means, and when the received signal has an electric field strength equal to or greater than a predetermined value, and the count value of the converted intermediate frequency signal is within a predetermined allowable range. A superheterodyne receiver which cancels a search operation and receives and demodulates a signal of the frequency.

[0016]

The present invention also provides a superheterodyne receiver which mixes a received signal with a signal from a local oscillator, converts the signal into an intermediate frequency, and then demodulates the signal, generating a digital signal representing a frequency to be received at a predetermined frequency interval. And signal generation control means for performing control for demodulating the received signal, and responding to the digital signal from the signal generation control means,
Local oscillation means for generating a signal having a frequency different from the frequency to be received by an intermediate frequency, and one or more tuning circuits, wherein each tuning circuit includes an inductor and a voltage variable capacitance element; Such a tuning circuit and an electrically rewritable read-only memory that can vary the resonance frequency for selecting a reception signal by varying the voltage applied to the read-only memory. Digital data representing a voltage to be applied to the voltage variable capacitance element of the tuning circuit is stored in advance. Such a read-only memory and a read-only memory which responds to a digital signal from the signal generation control means and reads based on a frequency to be received. A voltage converter that reads stored contents of a memory and applies an analog voltage converted from the read digital data to a voltage variable element of each tuning circuit. The signal generation control means can also generate a digital signal representing a frequency different from the frequency at which the digital data is stored in the read-only memory, the voltage conversion means, the frequency represented by the digital signal Correspondingly, when digital data is not stored in the read-only memory, the stored contents before and after the frequency are read, digital data for the frequency is estimated, and the estimation result is converted to the analog voltage. This is a superheterodyne receiver.

Further, according to the present invention, a local oscillation frequency is determined based on a digital signal representing a frequency to be received, an analog voltage obtained by converting digital data read from a read-only memory is applied, and the resonance frequency of the tuning circuit is adjusted. An adjustment device for a superheterodyne receiver tuned to a reception frequency, comprising: frequency indication means for indicating a plurality of frequencies to be received by a superheterodyne receiver to be adjusted; and Signal generating means for generating a signal having a frequency obtained by the superheterodyne receiver, and sensitivity determining means for responding to a reception output from the superheterodyne receiver to determine the receiving sensitivity of the superheterodyne receiver; Response to the output from the means and sensitivity judgment means, and tunes within a predetermined range for each reception frequency. Writing means for changing and deriving digital data converted to an analog voltage applied to a path, and writing digital data having the highest reception sensitivity to the read-only memory, wherein the initial value of the digital data derived by the writing means is included. The present invention provides a superheterodyne receiver adjusting device characterized in that digital data which is closest to each reception frequency and has already been written is used for each tuning circuit.

Further, according to the present invention, a local oscillation frequency is determined based on a digital signal representing a frequency to be received, an analog voltage obtained by converting digital data read from a read-only memory is applied, and the resonance frequency of the tuning circuit is adjusted. An adjustment device for a superheterodyne receiver tuned to a reception frequency, comprising: frequency indication means for indicating a plurality of frequencies to be received by a superheterodyne receiver to be adjusted; and Signal generating means for generating a signal having a frequency obtained by the superheterodyne receiver, and sensitivity determining means for responding to a reception output from the superheterodyne receiver to determine the receiving sensitivity of the superheterodyne receiver; Response to the output from the means and sensitivity judgment means, and tunes within a predetermined range for each reception frequency. Writing means for changing and deriving digital data converted to an analog voltage applied to a path, and writing digital data having the highest reception sensitivity to the read-only memory, wherein the initial value of the digital data derived by the writing means is included. An adjustment device for a superheterodyne receiver characterized by using an average value experimentally obtained in advance for each reception frequency.

[0020]

According to the present invention, the tuning circuit includes a voltage variable capacitance element, and is tuned to the frequency to be received by the analog voltage from the voltage conversion means. This analog voltage is read and converted in advance in a read-only memory as digital data for each frequency to be received. The local oscillator generates a signal having a frequency different from the frequency to be received by an intermediate frequency, mixes the signal with the received signal, converts the signal to an intermediate frequency, and demodulates the signal. Therefore, even if there is a variation in the voltage variable capacitance element or inductor of the tuning circuit, by storing in advance the digital data corresponding to the analog voltage tuned to the frequency to be received in the electrically rewritable read-only memory, Tuning to the frequency to be received is easy. For this reason, the sorting operation of the voltage variable capacitance element or the like becomes unnecessary.

[0021]

[0022]

In particular, according to the present invention, during a search operation,
The analog voltage applied to the voltage variable capacitance element of each tuning circuit is data obtained by changing digital data stored in a read-only memory in advance at a fixed ratio. For this reason, the resonance frequency of the tuning circuit is shifted from the frequency of the received signal, and the received signal is attenuated and received.
It is easy to determine whether the received signal has an electric field strength equal to or higher than a predetermined value. In addition, this search function counts the intermediate frequency signal obtained by converting the received signal, and is released when the counted value is within a predetermined allowable range, and receives and demodulates the signal of that frequency. Can be done.

[0024]

According to the present invention, even when digital data of a frequency corresponding to a read-only memory is not stored, an analog voltage to be applied to a tuning circuit by estimating from digital data of preceding and following frequencies is generated. Can be. Thus, signals of many frequencies can be received even if the capacity of the read-only memory is small.

Further, according to the present invention, digital data for obtaining the highest reception sensitivity can be stored in an electrically rewritable read-only memory for each frequency to be received. At the time of this adjustment, since the already written digital data closest to each reception frequency is used as an initial value for each tuning circuit, the state is already close to the maximum reception sensitivity at the initial value stage, and the maximum reception state is quickly reached. , And the adjustment time can be shortened.

According to the present invention, since the average value experimentally obtained in advance is used as the initial value of the adjustment, the maximum receiving sensitivity can be quickly obtained within the range of variation of the tuning circuit, and the adjustment time is shortened. be able to.

[0028]

FIG. 1 shows the overall configuration of a superheterodyne receiver according to an embodiment of the present invention. A signal having a desired frequency input from the antenna 1 is transmitted to the antenna tuning circuit 2,
Mixing circuit 5 via high frequency amplification circuit 3 and high frequency tuning circuit 4
Is input to On the other hand, local oscillation circuit 6 oscillating a signal having a frequency higher than the desired frequency by an intermediate frequency gives the signal to mixing circuit 5. The mixing circuit 5 converts the input signal into an intermediate frequency signal and supplies the intermediate signal to the intermediate frequency amplifier circuit 7. The intermediate frequency signal amplified by the intermediate frequency amplifier 7 is
The audio signal is demodulated by the demodulation circuit 8 and becomes an audio signal. The audio signal is amplified by the low frequency amplifier 9 and the speaker 10 is driven.
It is sounded.

In contrast to these analog signal processing systems, system controllers 11 and
Digital / analog conversion (hereinafter abbreviated as "D / A")
Circuits 12 and 13 are provided. A digital signal corresponding to the frequency to be oscillated is supplied from the control terminal 14 of the system controller 11 to the local oscillation circuit 6. Local oscillation circuit 6
Is a phase-locked loop (hereinafter abbreviated as "PLL") type oscillator, the details of which are shown in FIG.

In FIG. 2, a stable reference frequency signal is obtained by the crystal oscillator 6E and the oscillation circuit 6F. This reference frequency signal is frequency-divided by the frequency dividing circuit 6G and supplied to the phase comparing circuit 6H. The reference frequency from the frequency dividing circuit 6G is selected to be a frequency corresponding to a frequency interval to be received by the superheterodyne receiver, for example, 9 kHz. On the other hand, the frequency dividing circuit 6D is configured as a programmable frequency dividing circuit, and the frequency dividing ratio is set by a digital signal from the control terminal 14 of the system controller 11 input from the control line 6B. The frequency dividing circuit 6D frequency-divides the output of the voltage controlled oscillator (hereinafter referred to as “VCO”) 6C at the set frequency dividing ratio. The divided output is also applied to the phase comparison circuit 6H. The phase comparison circuit 6H constitutes a PLL circuit by supplying a DC voltage proportional to the phase difference between the outputs from the two frequency division circuits 6D and 6G to the VCO 6C. By this PLL operation, the VCO 6C has the same stability as that of the oscillator 6F.
By changing the frequency division ratio of D, it is possible to oscillate a frequency that is the reciprocal multiple of the frequency division ratio of 9 kHz, which is the output frequency of the frequency dividing circuit 6G.

Returning to FIG. 1, a signal is supplied from the local oscillation circuit 6 to the mixing circuit 5 from the terminal 6A. On the other hand, the antenna tuning circuit 2 and the high-frequency tuning circuit 4 constitute a variable frequency tuning circuit using a variable capacitance diode, so-called varicap, whose capacitance can be varied by a DC voltage. Is shown.

In FIG. 3, a tuning coil 51 is a fixed inductance, that is, a coil whose inductance cannot be varied, and forms a resonance circuit by a closed loop circuit with a varicap 52 and a bypass capacitor 53. The capacitance of the varicap 52 is changed by a DC voltage provided by the terminal 18 or 19 shown in FIG. The capacitor 55 is a capacitor for compensating the temperature characteristics of the entire tuning circuit. An input signal of a desired frequency is input from a terminal 56 and output from a terminal 57.

The master controller 17 shown in FIG. 1 is a control device necessary for manufacturing this receiver, is connected to the system controller 11, and loosely couples the output of the built-in oscillator to the antenna 1. . The necessity and function of the master controller 17 will be described later.

FIG. 4 shows the details of the configuration of the D / A circuits 12, 13 and the system controller 11 shown in FIG. In FIG. 4, parts corresponding to FIG. 1 are denoted by the same reference numerals. The system controller 11 is realized by a microcomputer of a program control type. A central processing unit (hereinafter abbreviated as “CPU”) 21 to a data bus 2
7. Two buses of the address bus 28 are output, and the following circuits are connected to these buses. That is, a control program storage mask ROM 22, an electrically rewritable read-only memory EEPROM 23, a RAM 24 for temporarily storing operation data, a D / A circuit 1
2, 13; an SiO 14 for outputting a digital signal as serial data to the local oscillation circuit 6, a counter 30 for counting an intermediate frequency signal, and an analog / digital conversion (hereinafter referred to as "A / D") for converting a carrier output level of a demodulation circuit into a digital signal. A) a circuit 29, a SiO 28 for transmitting and receiving signals to and from the master controller 17, a key 26 for operating the receiver, and a display 25 for displaying the state of the receiver.

For convenience of description, a medium-wave (abbreviated "MW") band receiver that receives 522 kHz to 1620 kHz at 9 kHz intervals will be described.

When the master controller 17 starts the automatic adjustment program, it first oscillates a frequency of 522 kHz, and gives a reception instruction of 522 kHz from the data bus 27 via the SiO 28. When receiving the reception instruction, the system controller 11 sets the oscillation frequency of the local oscillation circuit 6 to 972 kHz, which is higher by the intermediate frequency of 450 kHz.
Frequency division data oscillating at z is given to the local oscillation circuit 6 via the SiO 14. The D / A circuits 12 and 13 are preset with average digital data which is to be tuned to 522 kHz and which is stored in the master controller 17 in advance by experimentally obtained data. Next, the A / D circuit 29
Converts a DC signal proportional to the strength of the received carrier from the terminal 16 into digital data. In this state, first, D
The digital data of the / A circuit 13 is incremented or decremented, and the point at which the carrier output reaches the maximum voltage is obtained under the control of the system controller 11. As the high-frequency tuning circuit 4 tunes accurately to 522 kHz, the carrier output also rises, making it difficult to determine the true tuning point. Therefore, the system controller 11 adjusts the output level of the oscillator to the master controller 17 as necessary. Also give instructions to lower. After the repetition, when the maximum output state is determined, the digital data in the D / A circuit 13 is changed to E.
The data is written into the first address of the EPROM 23.

Similarly, for the next antenna tuning circuit, D
When the maximum output state is determined, the digital data is stored in an EEPROM.
Write to the second address of 23. 522kHz by the above operation
Only the reception state is adjusted to a state where the optimum tracking is obtained.

Next, the system controller 11 gives a report of the completion of the adjustment to the master controller 17, and the master controller 17 increases the frequency by 9 kHz and increases the frequency by 531 kHz.
An instruction to receive z is given to the system controller 11.

In a practical varicap, if it is desired to obtain a tuning frequency resolution to such an extent that its tracking error can be ignored, the D / A circuit 12,
The 13 digitized digital data are experimentally 11-
12 bits are required. In the operation step for searching for the optimum tuning point, the digital data supplied to the D / A circuits 12 and 13 is incremented (+1) or decremented (-
1) Since the data comparison of the A / D circuit 29 is repeated thereafter, the number of steps for searching for the optimum tuning point can be reduced as the first digital data given to the D / A circuit is closer to the final value. Therefore, if the user wants to quickly find the optimum tuning point of 531 kHz, the digital data determined at the time of the previous reception of 522 kHz is used as an initial value for the D / A circuit 1.
It is reasonable to give 2,13. Even at this frequency, after searching for the optimum tuning point, the D / A circuit 13,
The twelve optimal digital data are stored in the third and fourth addresses of the EEPROM 23, respectively. By repeating the operation up to 1620 kHz in the same manner, all the DC voltage data for the antenna and the high-frequency tuning circuit with respect to the reception frequency is written in the EEPROM 23. The receiver adjusted in this way can accurately obtain true tuning even if there are variations in the electrical characteristics of inductors and varicaps constituting the tuning circuit, and can achieve D / D
The output accuracy of the A circuits 12 and 13 is not required, and when a large number of receivers are to be manufactured, there is no need for a sorting operation for each component element and a management operation for combining and using only elements having matching characteristics. In addition, since an inductor or a capacitor that does not require a mechanical variable function is used, there is an advantage that the shape can be reduced, and the economic effect is great.

When a desired frequency is to be received by this receiver, a channel selection button or the like in the key 26 is pressed.
Alternatively, the reception frequency is determined by reading a reception frequency preset in advance, the frequency division data corresponding to the frequency is provided to the local oscillation circuit 6 from the SiO 14, and the digital data of the address corresponding to the reception frequency is provided. It goes without saying that data is read from the EEPROM 23 and output to the D / A circuits 12 and 14, respectively.

The A / D circuit 29 is generally realized by a multi-bit A / D circuit. Even if the A / D circuit 29 is a 1-bit A / D circuit, the A / D circuit 29 confirms a level change and receives a signal. Since the sensitivity can be measured, it is needless to say that the optimum tuning state can be obtained.

An EEPROM which is a read-only memory in which digital data for each D / A circuit can be electrically rewritten.
In this configuration, the writing operation performed in the manufacturing process can be performed purely and high-speed operation can be performed. On the other hand, the written digital data can be stored in a power failure or other abnormalities in the power supply means. There is an effect that it does not disappear easily even when such a problem occurs. In particular, in the case of a receiver having such a configuration, when this digital data is lost, a serious defect of inoperability in a normal use state occurs, but since the digital data is not lost, it is stored in a memory backed up by a battery. In this case, it is possible to secure much higher reliability than in the case of causing such a situation.

The superheterodyne receiver according to the embodiment shown in FIG. 1 can also be applied as follows. In the present embodiment, a so-called auto search function can be realized in which when a broadcast station scattered in a reception band is searched for and the broadcast station is received, the search is stopped at the frequency and the reception state is set. This function can be realized by a combination of an auto search on / off button and a channel selection button in the key 26. The system controller 11 in the auto search state first raises or lowers the reception frequency by one step and determines whether or not there is a broadcasting station, that is, a reception carrier at that frequency. This determination is made by the A / D circuit 2
9 is performed by detecting the input data, and when the input data is not higher than the predetermined reception carrier strength,
The frequency is further increased or decreased until the signal having the required reception carrier strength or more is obtained. When the signal is obtained, the search operation is stopped and the reception state is set. That is,
The A / D circuit 29 can be used as an output detector for tracking adjustment when manufacturing a receiver, and can be used as a carrier detector at the time of an automatic search when actually used as a receiver, so that it is very economical. .

In the auto search state, the A / D circuit 29
When the carrier intensity is detected by the intermediate frequency amplifying circuit 7
If the carrier is not detected through a filter having a narrower selectivity, the search operation may be stopped at a frequency immediately before or after the target frequency, and a reception state may be entered. This is more likely to occur as the electric field strength of the broadcasting station to be received increases. A counter 30 is provided to prevent the automatic search error, and the control program is configured so that the intermediate frequency signal is counted by the counter 30 and the automatic search operation is stopped only when the frequency of approximately 450 kHz is counted. That is, the condition for stopping the auto search state is that the auto search operation is accurately performed at the online reception frequency by setting that the detection level of the A / D circuit 29 is equal to or higher than a specified value and the measured value of the counter 30 is approximately 450 kHz. Can be canceled.

In the receiver having such a configuration, the carrier detection DC voltage from the demodulation circuit 8 generally has characteristics as shown in FIG. In FIG. 5, curve A represents the demodulated signal output of the modulated wave when the electric field strength of the received signal is gradually increased. The intermediate frequency amplifying circuit 7 is often provided with an automatic gain adjustment function in order to obtain a wide dynamic range, and the demodulation output does not increase when the input level exceeds a certain level. On the other hand, a special circuit system is used for the carrier detection output so as to obtain an output voltage proportional to the input level over a considerably wide range of the received signal, as shown by the curve B. This circuit system is configured to process and produce a carrier output level and a control voltage for automatic gain control, and has disadvantages that its absolute output level changes depending on temperature and that there is large variation due to circuit elements.

It is possible to secure a certain level of S / N for signals of many broadcasting stations within the reception band, that is, to cancel the auto search function only when a broadcast wave having a large electric field strength is received. It is practical to do so, and even if there are disadvantages as described above, the variation is adjusted with a semi-fixed resistor or the like to maintain the characteristics shown in curve B.

In order to easily solve such a problem, the sensitivity of the receiver is reduced only during the auto search operation.
What is necessary is just to make the output characteristic of the demodulated signal be as shown by the curve E. In a range where the demodulated signal changes according to the input level, the received carrier level is also changing in proportion, and it is easy to extract this as a DC voltage. In this embodiment, the means for lowering the sensitivity only at the time of the automatic search can be realized only by a program control method without preparing a special circuit element. That is, the antenna and the high-frequency tuning circuits 2 and 4 are detuned at a certain ratio only in the auto search state. A method of detuning is to multiply the digital data of the D / A circuits 12 and 13 at the time of true tuning by an experimentally obtained detuning coefficient, and to multiply the multiplied digital data by the D / A circuits 12 and 13.
13.

Although the received carrier output signal is not maximized at the true tuning point and slightly shifted due to the deviation from the desired frequency, the count value is 450 kHz in this embodiment when used together with the counter 30. Check the
The auto search state can be canceled at the correct reception frequency. After canceling the auto search state, the D / A circuits 12 and 13 are, of course, provided with digital data for real tuning.

As still another application, in a receiver of this kind, a frequency which is particularly frequently received is stored in advance in a preset channel, and the number of the preset channel is designated as required, thereby making one behavior. There is a function to receive the target frequency. Usually, an address corresponding to the preset channel number is arranged on the memory of the RAM 24, and is rewritten or read as required. In the conventional receiver, as long as the system controller 11 of the program control system is used, the RAM 24 as a work area is always necessary, and it is very difficult to use a part of the RAM 24 as a frequency data storage area of this preset channel. It is economical and widely used. However, since the RAM 24 is used as a memory, when the power of the receiver is cut off, a method of backing up only the RAM area with a battery or a large-capacity capacitor so that the stored data is not lost is adopted. In addition, since it is necessary to detect a power shutdown and quickly bring it into a backup state, it is necessary to pay close attention to the design of a reset circuit as a system controller. According to the present embodiment, these problems can be solved at once by specifying an address in the EEPROM 23 as a storage area for the preset channel. The bits used in the EEPROM 23 in the present embodiment are the D / A circuits 12, 1
Each of the three data requires 12 bits, and 522 kHz.
If all the frequencies from 9 to 1620 kHz at every 9 kHz are to be stored, 2952 bits are required. On the other hand, there are 20 preset channels,
Even if one station needs 20 bits of data,
The storage area for the preset channel may be 400 bits. The EEPROM is manufactured by an integrated circuit technology. However, due to the manufacturing process, a capacity of about 3000 bits and a capacity of about 3
There is little economic difference between the 400-bit capacity. That is, in the case of the receiver having the configuration of the present embodiment, the storage area for the preset channel is stored in the EEPROM 23.
In this case, a reasonable effect of being economical and having no troublesome design for system reset is produced.

In order to further pursue economy, it is sufficiently possible to realize the system controller 11 and the D / A circuits 12 and 13 by one integrated circuit as shown in FIG. Here, when the present invention is applied to a multi-band receiver, a large capacity of the EEPROM is required to store the D / A circuit data of all reception frequencies. Therefore, a method of reducing stored data within a range where a tracking error can be ignored will be described. For the sake of simplicity, a description will be given of the receiver capable of receiving at 9 kHz intervals from 522 kHz to 1620 kHz shown in the above embodiment.

FIG. 6 is a graph of digital data to be given to the D / A circuit for reception frequencies from 522 kHz to 720 kHz. That is, since 522 kHz is the lowest frequency, the varicap voltage at this time also has the lowest value. Assuming that there is no D / A circuit data B of 612 kHz, an average value ((A + C) / 2 in this example) is obtained from the digital data before and after that, A for 603 kHz, and C for 621 kHz. When this is B1, the difference between the true values B and B1 is very small. Similarly, when digital data D and G exist and E and F are estimated,

[0052]

E1 = (GD) / 3 + D

[0053]

## EQU2 ## F1 = G- (GD) / 3, and data of H and L exist.
It is also possible to estimate the data of I1, J1, and K1.

As another estimation method, there is the following method. FIG. 7 shows an example of a DC voltage versus capacitance characteristic of a voltage variable capacitance diode (varicap). Assuming that the DC voltage applied to the varicap is V and the capacitance at that time is C, C is proportional to V minus the power of K2.
That is,

[0055]

C = K1 (V) ^-k2 where K1 and K2 are constants. In order to experimentally match the characteristic of FIG. 7 with the equation of equation 3, the following equation 4
It is more convenient to express by the formula.

[0056]

C = K1 (V + K3) ^{-K2 where} K1, K2 and K3 are constants. From this equation, if the inductance of the inductor forming the tuning circuit is L, the stray capacitance of the tuning circuit is C0, and the resonance frequency of the tuning circuit is f, the DC voltage V to be applied is

[0057]

(Equation 5)

Is represented by There are five unknown constants in Equation 5,
That is, since they are K1, K2, K3, L and C0,
If the determined digital data for the D / A circuit is known at at least five frequencies, these unknown constants can be solved by equations, and consequently D at any frequency.
/ A circuit digital data can be estimated.

However, no matter what estimation method is used, the greater the missing frequency of data, the greater the amount of tracking error when tuned by the digital data at the time of estimation, the more practically the degree of missing data depends on the antenna and Because it is also affected by the Q value of the high-frequency tuning circuit,
Must be determined experimentally. According to the experiment, it was confirmed that the tracking error was practically negligible in the circuit configuration of the present embodiment even when the gap between data was set to two frequencies. Further, when the high-frequency tuning circuit 4 and the D / A circuit 13 are abolished from the embodiment of FIG. 1, the loss can be tolerated up to four frequencies.

When trying to obtain a more economical receiver,
A slight tracking error is often not a problem in practical use of the receiver. The frequency at which the digital data for the D / A circuit is stored in the EEPROM is determined by the characteristics and economy of the whole receiver. For example, in the case of a receiver that stores digital data at every fourth frequency interval and has a control program for estimating digital data of three frequencies in between using the above-described method, the required capacity of the EEPROM is reduced by about 1 /. 4 can be reduced.

Further, in the manufacturing process of the receiver according to the present embodiment, the tuning digital data can be determined in a short time as follows. The method of shortening the adjustment time by previously setting the fixed data of the adjacent reception frequency in advance and starting the increment or decrement from this digital data has already been described, but the frequency interval between the fixed data and the fixed data is large. In such a case, there is a possibility that the effect of shortening the time in the manufacturing process is reduced in the above method. Under such conditions, the time can be reduced by the following method.

That is, the variation in the electrical characteristics of each circuit element is not unlimited and is within a range that can be economically produced.
It is possible to keep it within a limited range. Only the elements having the center value within the limited range are combined, digital data for the frequency versus A / D circuit in the combined receiver is measured in advance, and the digital data is stored in a memory in the master controller 17. Should be memorized. Then, when the frequency is set in the tuning digital data adjustment operation, first, the digital data stored in the master controller 17 is supplied to the system controller 11 and the D / A circuits 12 and 13 are provided.
Initialize each. As a result, the number of steps at the time of adjustment can be reduced, and the adjustment time can be significantly reduced.

In the embodiment shown in FIG. 1, the local oscillator circuit 6 uses a so-called direct synthesizer type oscillator which uses a PLL type oscillator but generates a target frequency by giving oscillation frequency data. Of course, it may be used.

In this embodiment, the D / A circuit 12,
Although the method of the thirteenth method is not specifically described, it is needless to say that any method that can be realized at present, that is, any method such as a combination of a PWM wave and a filter or a ladder resistance method is possible.

Although the case where two sets of the desired frequency tuning circuit, the tuning circuit 2 for the antenna and the tuning circuit 4 for the high frequency amplifier circuit, are described, one of them is abolished and the corresponding D / A circuit is eliminated. Needless to say, the receiver may have a simple configuration in which the receiver is eliminated. Also, it goes without saying that the number of tuning circuits can be increased and the selectivity of high frequencies can be improved.

[0066]

As described above, according to the present invention, the tuning circuit can be miniaturized with a simple circuit configuration, and the optimum receiving state can be achieved at each receiving frequency. Therefore, the tuning circuit does not need to be provided with a variable capacitor for adjustment or the like, and it is not necessary to select the characteristics of the voltage variable capacitor. Therefore, a compact, inexpensive superheterodyne receiver can be obtained. .

[0067]

[0068]

In particular, according to the present invention, since the tuning of the tuning circuit is shifted during the search operation, the signal is attenuated, and whether or not the received signal has an electric field strength equal to or higher than a predetermined value by the output from the electric field strength detecting means is determined. Is easy to determine,
The search operation can be performed reliably.

[0070]

According to the present invention, the digital data stored in the read-only memory can be complemented and converted into an analog voltage and applied to the voltage variable capacitance element of the tuning circuit. Can be used to receive many frequencies.

Further, according to the present invention, in the step of storing digital data in the read-only memory, the frequency is set to the initial value using the data of the closest frequency already stored at each frequency for each tuning circuit. By changing the digital data, the digital data that provides the highest reception sensitivity can be stored in the read-only memory, so that the adjustment for each frequency can be performed quickly.

According to the present invention, an average value experimentally obtained in advance is used as an initial value for each frequency.
Digital data that can obtain the highest reception sensitivity can be quickly determined.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a superheterodyne receiver according to one embodiment of the present invention.

FIG. 2 is a block diagram showing an electrical configuration of a local oscillation circuit 6 shown in FIG.

FIG. 3 is an electric circuit diagram of the tuning circuits 2 and 4 shown in FIG. 1;

FIG. 4 is a block diagram showing an electrical configuration of the system controller 11 shown in FIG.

FIG. 5 is a graph showing a relationship between an input signal and an output of the superheterodyne receiver shown in FIG. 1;

FIG. 6 is a graph showing characteristics of the tuning circuit shown in FIG. 3;

FIG. 7 is a graph showing characteristics of the voltage variable capacitance diode 52 shown in FIG. 3;

FIG. 8 is a block diagram showing an electrical configuration of a conventional superheterodyne receiver.

9 is an electric circuit diagram of the tuning circuits 32 and 34 and the resonance circuit 40 shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Antenna 2 Antenna tuning circuit 3 High frequency amplifier circuit 4 High frequency tuning circuit 5 Mixing circuit 6 Local oscillation circuit 7 Intermediate frequency amplifier circuit 8 Demodulation circuit 11 System controller 12, 13 D / A circuit 17 Master controller 21 CPU 23 EEPROM 26 Key 29 A / D circuit 30 Counter 51 Inductor 52 Variable capacitance diode 53, 55 Capacitor 54 Resistance

Claims (4)

(57) [Claims] 1. A superheterodyne receiver which mixes a received signal with a signal from a local oscillator, converts the signal into an intermediate frequency, and then demodulates the signal, generates a digital signal representing a frequency to be received at a predetermined frequency interval, and Signal generation control means for performing control for demodulating the received signal; local oscillation means for generating a signal having a frequency different from the frequency to be received by an intermediate frequency in response to a digital signal from the signal generation control means; A plurality of tuning circuits, each of which includes an inductor and a voltage variable capacitance element, and can vary a voltage applied to the voltage variable capacitance element to vary a resonance frequency for selecting a reception signal. , Such a tuning circuit, and an electrically rewritable read-only memory, wherein a voltage variable capacitor of each tuning circuit is provided at the predetermined frequency interval. A read-only memory in which digital data representing a voltage to be applied to the element is stored in advance, and a read-only memory read in response to a digital signal from the signal generation control means and based on a frequency to be received. Voltage converting means for applying an analog voltage converted from the read digital data to the voltage variable capacitance element of each tuning circuit, electric field intensity detecting means for detecting the electric field intensity of the received signal, and an intermediate frequency signal obtained by converting the received signal. Counting means for counting, wherein the signal generation control means has a search function of sequentially changing the frequency within a predetermined frequency range, and during the search operation, the voltage conversion means reads from the read-only memory. The stored contents are changed at a predetermined ratio and then converted to the analog voltage. In response to the output from the detecting means and the counting means, the search operation is canceled when the received signal has an electric field strength equal to or higher than a predetermined value and the count value of the converted intermediate frequency signal is within a predetermined allowable range. And receiving and demodulating a signal of the frequency. 2. A superheterodyne receiver which mixes a received signal with a signal from a local oscillator, converts the signal into an intermediate frequency, and demodulates the signal, generates a digital signal representing a frequency to be received at a predetermined frequency interval, and Signal generation control means for performing control for demodulating the received signal; local oscillation means for generating a signal having a frequency different from the frequency to be received by an intermediate frequency in response to a digital signal from the signal generation control means; A plurality of tuning circuits, each of which includes an inductor and a voltage variable capacitance element, and can vary a voltage applied to the voltage variable capacitance element to vary a resonance frequency for selecting a reception signal. , Such a tuning circuit, and an electrically rewritable read-only memory, wherein a voltage variable capacitor of each tuning circuit is provided at the predetermined frequency interval. A read-only memory in which digital data representing a voltage to be applied to the element is stored in advance, and a read-only memory read in response to a digital signal from the signal generation control means and based on a frequency to be received. Voltage conversion means for applying an analog voltage converted from the read digital data to a voltage variable element of each tuning circuit, wherein the signal generation control means includes a frequency at which digital data is stored in the read-only memory. A digital signal representing a different frequency can also be generated.When the digital data is not stored in the read-only memory corresponding to the frequency represented by the digital signal, the voltage conversion unit reads out the stored contents before and after the frequency. , Estimating digital data for the frequency, and applying the estimation result to the analog voltage. A superheterodyne receiver characterized by converting. 3. A local oscillation frequency is determined based on a digital signal representing a frequency to be received, an analog voltage obtained by converting digital data read from a read-only memory is applied, and a resonance frequency of the tuning circuit becomes a reception frequency. An adjusting device for a superheterodyne receiver to be tuned, comprising: frequency instructing means for instructing a plurality of frequencies to be received by a superheterodyne receiver to be adjusted; and responding to an output from the frequency instructing means to adjust the designated frequency. Signal generating means for generating a signal and providing the signal to the superheterodyne receiver; sensitivity determining means responsive to a reception output from the superheterodyne receiver to determine the receiving sensitivity of the superheterodyne receiver; frequency indicating means and sensitivity Responds to the output from the determination means and gives it to the tuning circuit within a predetermined range for each reception frequency. Derived by changing the digital data is converted into an analog voltage, and a writing writing means digital data maximum receiving sensitivity can be obtained in the read-only memory, as an initial value of the digital data writing means for deriving,
An apparatus for adjusting a superheterodyne receiver, wherein digital data already written and closest to each reception frequency is used for each tuning circuit. 4. A local oscillation frequency is determined based on a digital signal representing a frequency to be received, an analog voltage obtained by converting digital data read from a read-only memory is applied, and a resonance frequency of the tuning circuit is set to a reception frequency. An adjusting device for a superheterodyne receiver to be tuned, comprising: frequency instructing means for instructing a plurality of frequencies to be received by a superheterodyne receiver to be adjusted; and responding to an output from the frequency instructing means to adjust the designated frequency. Signal generating means for generating a signal and providing the signal to the superheterodyne receiver; sensitivity determining means responsive to a reception output from the superheterodyne receiver to determine the receiving sensitivity of the superheterodyne receiver; frequency indicating means and sensitivity Responds to the output from the determination means and gives it to the tuning circuit within a predetermined range for each reception frequency. Derived by changing the digital data is converted into an analog voltage, and a writing writing means digital data maximum receiving sensitivity can be obtained in the read-only memory, as an initial value of the digital data writing means for deriving,
An adjusting device for a superheterodyne receiver, wherein an average value experimentally obtained in advance is used for each reception frequency.