JP2747123B2 - Driving device for DC plasma display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus for a DC plasma display panel, and more particularly to a driving apparatus for a pulse memory driving system.
The present invention relates to a driving device .

[0002]

2. Description of the Related Art FIG. 6 is a partial perspective view of a main part of a conventional DC plasma display panel (hereinafter referred to as a DC-PDP or simply a panel), in particular, a DC-PDP driven by a pulse memory. It is.

The panel 10 includes a display anode 12 and an auxiliary anode 1.
Front plate (second panel substrate) composed of phosphors 4 and 3 colors
18 and a back plate (first panel substrate) 24 composed of a cathode 20 and a bank 22.

A display cell 30 is arranged on both sides of an auxiliary cell 26 with a bank having priming holes 28 therebetween. One pixel is composed of one R phosphor cell, one B phosphor cell, and two G phosphor cells.

FIG. 9 is a block diagram of a television display drive system showing the outline of the drive method in both FIGS.
Will be described with reference to the timing chart of FIG. Note that the connection between FIG. 7 and FIG.

[0006] First, in FIG.
Is input to the R, G, and B parallel PCM (pulse PCM) by the decoder 32 and the A / D converter 34.
The signal is converted into a signal (code modulation) signal and sent to the line interpolation circuit 36. The R / G and G corresponding to the color dot arrangement on the display panel are provided by the line interpolation circuit 36.
/ B are generated, the two signals are subjected to intra-field interpolation, and then time-compressed by a time compression circuit 38 to obtain a sequential scanning signal. Next, the processor 40 performs γ (gamma) correction and APL (Average Picture).
Level), and performs arithmetic processing such as gain adjustment, and writes the result to the frame memory 42. A write signal is generated from a write pulse circuit 50 in response to a signal from the frame memory 42 and a clock signal described later, and the level of this signal is converted by a level converter 52 into a voltage V _w (peak value of a write pulse), A write pulse is generated by switching the reference level, that is, the display anode voltage to the OFF level (usually ground potential), and these are passed through a diode to the display anode DA _j (j = 1, 2,.
n).

On the other hand, the synchronizing signal converted separately from the color signal by the decoder 32 is converted by a vertical / horizontal synchronizing separation circuit 44 into a vertical synchronizing signal and a horizontal synchronizing signal. Based on the vertical and horizontal synchronizing signals, the control signal generator 46 transmits a clock signal for extracting a color signal (display data) according to the size of the display screen of the display panel. The drive pulse generator 48 transmits various signals for driving the panel based on the vertical synchronizing signal, that is, signals serving as sources of a sustain pulse, a scan pulse, and an erase pulse.

The signal from the drive pulse generator 48 passes through a sustain pulse circuit 54 and a level converter (switching between a peak value _Vsp and an OFF level (normally, ground potential) 56 of the anode voltage). the sustain pulse is formed, and supplies the constant display anode DA _j through the diode it. An anode drive signal is formed by the sustain pulse and the above-described write pulse. The signal from the driving pulse generator 48 is also supplied to a scanning pulse circuit 58 and an erasing pulse circuit 60. The signals from the respective circuits 58 and 60 are passed through a level converter 62 and a mixer 64 to each cathode of the panel 10. A cathode drive signal including a scan pulse and an erase pulse is supplied. The level converter 62 determines the peak value (-V _k ) and the OFF level (-
V _k0 ) to form a scanning pulse, and the erasing pulse is switched between this OFF level (−V _k0 ) and the cathode 0 level (peak value) (usually ground potential). To form an erase pulse. The mixer mixes the scan pulse and the erase pulse at a required timing to form a cathode drive signal.

Next, the driving method will be described with reference to the timing chart of FIG.

A cathode C _i (i = 1, 2,..., M), a display anode DA _j (j = 1, 2,..., N), and an auxiliary anode S
A display cell and an auxiliary cell formed by A _h (h = 1, 2,..., L) are D _ij and S _ih , respectively. Display anode D
A _j (j = 1, 2,..., N) has a width τ _sp , a period T, and an amplitude V _sp (between the anode 0 level and the OFF (off) level) so as to maintain the pulse memory discharge. Is always applied. On the other hand, a scanning pulse (width τ _k , voltage V _k ) is sequentially applied to the cathode from above. The auxiliary anode SA _h
It applies a constant positive potential V _SA through the resistor R _s to. By doing so, the auxiliary cells are sequentially discharged from the top as shown in FIG. The resistance R _s due to this discharge current
, The potential of the auxiliary anode decreases in a pulsed manner as shown in FIG. If the scan pulse is applied so as not to overlap with the sustain pulse, it does not affect the pulse discharge of the display cell at all. When writing to the display cell D ₂₂ of intersection of the cathode C ₂ of the display anode DA ₂ and the second row, the DA ₂ write pulse (width tau _w, voltage V _w (amplitude from the OFF level))
At approximately the same timing as the discharge of the auxiliary cells in the second row. At this time, charged particles, metastable particles, and the like due to the discharge of the auxiliary cell diffuse into the display cell through the priming hole of the cathode, thereby lowering the discharge starting voltage of the display cell in the second row. Calling). As a result, it is possible to generate discharge only the display cells D ₂₂ by the write pulse. Due to this priming effect, the delay time of the discharge is also reduced, and the variation is greatly reduced. Therefore, stable writing can be obtained even with a narrow writing pulse, and information can be written to all cells in one row for each period of the sustain pulse (this period is called access time). In this way, high-speed write scanning with a fast access time has become possible.

[0011] To stop the discharge of the discharge cell D ₂₂ generally display discharge cell D ₂₂ anode - sustain pulse discharge applied to the cathode may be as not occur more than once. As a result, the charge currents and the like remaining in the cell disappear, so that even if the sustain pulse is applied again, no discharge occurs. Since the pulse memory driving method employs a method of forcibly erasing all display cells in the same row, the cathode has a sufficiently large large amplitude (width from V _k0 level to cathode 0 level) as shown in FIG. ) Can be applied. Due to this erase pulse, the voltage between the anode and the cathode of the display cells in the same row is sufficiently reduced even when the sustain pulse is applied to the display anode, so that the pulse discharge is stopped simultaneously with the application of the erase pulse.

FIG. 10 is a high-voltage power supply connection diagram of a conventional panel drive system. Reference level and a reference level of the anode of the cathode are the same voltage value, the anode side, V _sp supply, V _w power, there are auxiliary anode voltage power source, the cathode side, -V _k power,
-V _k0 power supply is connected. The same reference level means that the cathode 0 level of the erase pulse as the cathode voltage shown in FIG. 9 is equal to the OFF level as the display anode voltage.

[0013]

However, in the above-mentioned pulse memory driving method, the driving (driver) section is integrated with an IC.
However, there is a disadvantage that the total power consumption of the drive system power supply circuit is high and the cost is high. Further, in particular, a spike current flows in the drive system power supply circuit due to the voltage level fluctuation at the time of ON (ON) and OFF (OFF) of the constantly applied sustain pulse, which leads to the generation of noise in the circuit, abnormal light emission, lifetime There was a problem that it also became a factor of shortening.

An object of the present invention is to provide the above-described driver I.
In order to eliminate the problem that C is expensive and the noise, abnormal light emission, and shortening of the life due to the switching of the high-voltage power supply, a driving apparatus for the DC plasma display panel that can reduce the total power of the power supply circuit of the driving system is provided. To provide.

[0015]

According to the present invention, a first panel substrate having a plurality of parallel cathodes and a second panel substrate having a plurality of parallel anodes are provided. A driving device for a plasma display panel, which is disposed to face each other with a predetermined gap, wherein an anode driving signal including a high- frequency sustain pulse and a writing pulse based on emission and non-emission data is applied to the anode. Means for applying;
It is applied to the cathode drive signal including an erasing pulse generated in accordance with the timing of erasing the sequential scan pulse to the cathode
And an anode base which is a reference level of the anode drive signal.
Generates sustain pulse peak voltage based on sub-level
And a sustain pulse power source based on the anode reference level.
Write pulse that generates the peak voltage of the write pulse
A power supply and a cathode reference which is a reference level of the cathode drive signal;
Generate scan pulse peak voltage based on level
A scan pulse power supply and a scan based on the cathode reference level.
An off-level power supply that generates an off-level voltage
In the driving device <br/> the DC type plasma display panel comprising a Ru give an intermediate bias voltage between the two reference level of the anode drive signal and the cathode drive signal, the intermediate by
It is characterized by further comprising a power supply .

[0016]

SUMMARY OF] According to this inventions described above, the order given a potential difference of the intermediate bias voltage between the reference level of the reference level and the cathode drive signal of the anode drive signal, i.e., anode - an intermediate potential between the cathode an intermediate bias power supply to make, a device configuration comprising a circuit capable of driving incorporating the intermediate potential.

By providing the intermediate bias power supply and applying the intermediate bias voltage as described above, the high voltage of the intermediate bias can be obtained.
Side voltage level is the reference level voltage of the anode drive signal.
(Anode reference level). In addition, low voltage of intermediate bias
Side voltage level is the reference level voltage of the cathode drive signal.
(Cathode reference level). Therefore, the anode reference level
And the cathode reference level are equal
The anode reference level shifts to the peak side of the displayed anode voltage.
Also, the cathode reference level shifts to the peak side of the cathode voltage.
To As a result, if the panel drive is performed with the voltage difference between the peak value of the anode drive signal, that is, the peak value of the anode voltage, and the peak value of the cathode drive signal, that is, the peak value of the cathode voltage being the same as the conventional voltage difference, , the voltage difference between the peak value and the shifted positive Gokumoto reference level table示陽pole decreases, Similarly, were the peak value and the shift in the cathode voltage negative
Voltage difference between Gokumoto reference level is also reduced. Therefore, the voltage applied to the voltage power supply circuit of the driving system is lower than the conventional voltage.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a panel driving apparatus according to the present invention. In the drawings, the same components as those shown in FIGS. 6 to 10 are denoted by the same reference numerals, and detailed description thereof will be omitted unless otherwise specified. .

FIGS. 1 and 2 are timing charts for explaining an embodiment of the present invention. In both figures, the horizontal axis is a time axis, and the vertical axis is a voltage axis. now,
It is assumed that the application method of each pulse is the same as the conventional method. In the present invention, by providing the intermediate bias power supply, the width between the OFF levels of the individual anode-side and cathode-side pulses (that is, the anode 0 level and the cathode 0 level) has a width corresponding to the intermediate bias voltage (intermediate potential) _Vmv. It features a certain point. In this way, the power supply voltage required to obtain the ON level of each pulse in the related art can be subtracted on average by half of the intermediate potential _{Vmv in} the present invention (FIG. 1). In this case, the maximum voltage applied to the anode power supply circuit of the drive system is a voltage corresponding to the potential difference between the anode 0 level of the anode voltage and the peak voltage _Vsp of the sustain pulse, and is applied to the cathode power supply circuit. The maximum voltage is a voltage corresponding to the potential difference between the cathode 0 level of the cathode voltage and the peak voltage (−V _k ). The intermediate potential _Vmv may be set to a value according to the design.

FIG. 2 shows a timing chart when the intermediate potential _VmV is used equally on the anode side and the cathode side. In the figure,
The conventional reference level indicated by the broken line is the cathode 0 level (immediately
That is, the cathode reference level) and the anode 0 level (that is, the anode reference level)
Level) . In addition, * voltage showed marked ^{_{V sp *, V w *,}} -V k0 *, -V k * is, follow
The voltage with respect to the current reference level.
Person, unmarked voltage _{V sp, V w, -V k0} , -V k is, anode 0
Shown relative to the level or cathode 0 level, the voltage to be used in this invention. From FIG. 2, it can be seen that the voltages from both the anode side and the cathode side OFF levels (anode 0 level, cathode 0 level) are lower by half of the intermediate potential _Vmv than in the prior art. That is, the anode 0 level and the cathode 0
The voltage of each level is based on the conventional reference level.
With that, the V _mv / 2 and -V _mv / 2. Thus, in this embodiment, the maximum voltage applied to the drive system power supply circuit on the anode side
Is V1 ( = _Vsp = _Vsp ^* _−Vmv / 2) , and the maximum voltage applied to the driving power supply circuit on the cathode side is V2 ( = | V
^{_{k | = | V k * |}} - | a) | V _mv / 2.

FIG. 3 is a block diagram showing an example of a drive circuit for implementing the embodiment of the present invention. In the figure, ~
Are connection points to the corresponding to in FIG. In addition, portions that overlap with the conventional description are omitted here. The write signal generated by the write pulse circuit 50 is converted to a high voltage by the level converter 52. Although the conventional circuit has been converted to a peak value V _w of the reference level or the write pulse, in the case of the embodiment of the present invention is converted into anode reference level (anode 0 level) or the peak value V _w. Similarly, the sustain pulse is also the anode reference level (anode 0 level)
Or the peak value _Vsp of the sustain pulse. Further, the scanning pulse signal on the cathode side is the OFF level of the scanning pulse (−
V _k0 ), the peak value of the scanning pulse (−V _k ), and the erasing pulse signal are converted to the cathode reference level (cathode 0 level) or the (erasing pulse OFF level) (−V _k0 ). In the case of the auxiliary anode, although there is no signal level conversion, the reference level of the auxiliary anode high voltage power supply _VSA is set to the anode reference level, that is, the anode 0
Changing to level.

[0022] To facilitate understanding of the invention described above, shows a high-voltage power supply circuit connection diagram according to an embodiment of the present invention in FIG. As shown in FIG. 4, in the present invention, an intermediate via is provided.
A high bias power supply _Vmv ( _Vmv power supply) is used as an intermediate bias to create an intermediate bias, and the positive side is set at the reference level of the anode drive signal.
Certain anode reference level, minus side is the reference of cathode drive signal
The level is defined as the cathode reference level. And this
In the invention of the present invention, the sustain pulse
Sustain pulse power supply that generates peak voltage _Vsp ( _Vsp power supply)
And the write pulse peak based on the anode reference level.
Write pulse power supply for generating a click voltage V _w (V _w power supply)
With Further, in this embodiment, the anode reference laser is used.
Generates voltage V _SA applied to auxiliary anode based on bell
Equipped with auxiliary anode voltage power supply. In the present invention,
Peak voltage of scan pulse with reference to cathode reference level-
A scanning pulse power supply (−V _k power supply) for generating V _k and a cathode
Off-level voltage of scan pulse based on reference level-
An off-level power supply for generating V _k0 (−V _k0 power supply)
ing.

FIG. 5 is experimental data showing the relationship between the intermediate bias voltage when the intermediate bias is actually taken in and driven, and the total power consumption obtained by summing the power consumed by the power supply circuits of the panel and circuit driving system. . The horizontal axis of FIG. 5 shows the intermediate bias voltage V _mv (volt), and the vertical axis shows the total power consumption (watt). In the figure, a curve I shows a case where all the light-emitting members forming one pixel emit light and the maximum gradation of the three primary colors (screen duty (duty) is 100%), and a curve II shows all the light-emitting members. Shows a case where no light is emitted (screen duty 0%).

The state where the intermediate bias is set to 0 volt corresponds to the driving method in the case of the conventional circuit. In this example,
Although the intermediate bias is set to a voltage other than 0 volt, the intermediate bias has a maximum value and cannot be applied more than the sustaining voltage.
By the way, when V _mv = 100 V, the power supply voltage is reduced by 50 V assuming that the anode side and the cathode side are divided into two, and the power consumption can be understood from the experimental data in FIG.
It can be reduced by about 35 to 50% with respect to y0 to 100%. In the figure, RI is the reduction rate when the screen duty is 100%, RI
I indicates the reduction rate when the screen duty is 0%, respectively.
RI = 35% and RII = 50%.

The advantages of using the intermediate bias include noise reduction, suppression of abnormal light emission, and extension of life.

In a plasma display, it is necessary to convert a logic signal into a high voltage capable of emitting light. Generally, during high voltage conversion, overshoot and downshoot noise occurs. The amplitude of the noise is high voltage ON, OF
Although it is proportional to the amplitude at the time of F, the use of the intermediate bias obviously reduces the amplitude of the high voltage at the time of switching, that is, the amplitude of the noise. In addition, when the high voltage is turned on and off, particularly when the cell is turned on, that is, when the cell starts to emit light, an excessive current flows through the cell due to overshoot noise, and a mode different from normal light emission, for example, a cathode and a pilot anode in a display cell. Intermittent light emission occurs. Once such an abnormal mode emission occurs, it is maintained by the sustain pulse. The light emission in the abnormal mode is clearly understood from the display screen, and is seen as a color different from the normal phosphor emission color. The cell in which the abnormal light emission has occurred has a considerably shortened life, and if the abnormal light emission continues to occur, the life of the cell is reduced to about one hour. However, when the intermediate bias is used this time, the overshoot noise is reduced as described above, and therefore, the abnormal light emission is also eliminated.

[0027]

As described above in detail, according to the present invention, an intermediate bias is introduced into the pulse memory drive by using the intermediate bias power supply, and as a result, the peak values of the anode drive signal and the cathode drive signal are reduced. Even if the same voltage value is used, the power supply voltage for supply to each drive circuit can be greatly reduced, so that a reduction in the total power consumption of the drive device can be expected, and therefore, the cost of the driver IC can be reduced. Can be expected. Further, since the voltage applied to the high-voltage power supply circuit of the driving system is reduced, noise generation in the circuit due to spike current at the time of high-voltage switching, suppression of abnormal light emission of cells , and extension of life can be expected.

[Brief description of the drawings]

FIG. 1 is a timing chart showing a state in which an intermediate bias voltage is applied between a display anode voltage and a cathode voltage for explanation of a method of the present invention.

FIG. 2 is a timing chart showing a state in which the intermediate bias voltage shown in FIG. 1 is equally divided and applied to an anode side and a cathode side.

FIG. 3 shows a DC-PDP for implementing the method of the present invention.
FIG. 2 is a block diagram showing one configuration example of a part of the drive circuit of FIG.

FIG. 4 is a connection diagram showing a connection state of a high-voltage power supply circuit of a drive system when the method of the present invention is performed.

FIG. 5 is a graph showing the relationship between the intermediate bias voltage and the total power consumption, showing comparative experimental data of the total power consumption in the high-voltage power supply circuit of the drive system according to the method according to the present invention and the conventional method.

FIG. 6 is a partial perspective view of a main part of the structure of the DC-PDP.

FIG. 7 is a block diagram showing a half part of a driving system of a conventional DC-PDP.

FIG. 8 is a block diagram showing another part of the drive system of the conventional DC-PDP, which shows the other half of the DC-PDP integrated with the part of FIG.

FIG. 9 is a timing chart for explaining a conventional driving method.

FIG. 10 is a connection diagram showing a connection state of a high-voltage power supply circuit of a drive system for implementing a conventional method.

[Explanation of symbols]

 10: panel 32: NTSC decoder 34: A / D converter 36: line interpolation circuit 38: time compression circuit 40: processor 42: frame memory 44: vertical / horizontal synchronization separation circuit 46: control signal generator 48: drive pulse Generator 50: Write pulse circuit 52, 56, 62: Level converter 54: Sustain pulse circuit 58: Scan pulse circuit 60: Erase pulse circuit 64: Mixer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Hiroshi Toyama 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Hiroshi Furuya 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-4-221199 (JP, A)

Claims (1)

(57) [Claims] 1. A first panel substrate comprising a plurality of parallel anodes and a second panel substrate comprising a plurality of parallel anodes,
With a predetermined gap, an apparatus for driving a plasma display panel comprising opposite disposed, means for applying an anode driving signal including the sustain pulses of the high frequency to the anode and the write pulse based on light emission and non-emission data, the cathode
Means for applying a cathode drive signal including an erasing pulse generated in accordance with the timing of erasing the sequential scan pulse to the
And an anode reference level which is a reference level of the anode drive signal.
To generate the peak voltage of the sustain pulse based on the
Pulse power supply and write based on the anode reference level
Write pulse power supply that generates peak voltage of pulse
And a cathode reference level which is a reference level of the cathode drive signal.
Scan that generates the peak voltage of the scan pulse based on the
A pulse power supply and a scanning power source based on the cathode reference level.
Off-level power supply that generates
And has it <br/> to drive the DC type plasma display panel to obtain, both a reference level of the anode drive signal and the cathode drive signal
Ru gives intermediate bias voltage between Le, the intermediate bias power
A driving device for a DC plasma display panel, further comprising: