JP2745662B2 - Moving state detection device for moving objects - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving state detection device for a moving body suitable for detecting the speed and acceleration of the moving body.

Conventional technology Conventionally, the speed of a moving object is detected by an analog speed sensor or by measuring a cycle of a displacement signal output from the moving object and having a constant displacement of the moving object as one cycle. I was In addition, the acceleration of the moving body has been detected by measuring a driving current of an actuator that drives the moving body.

[Problem to be Solved by the Invention] In the above-described conventional moving state detecting device, a plurality of sensors are required to detect the speed and the acceleration, and there has been a problem that a circuit configuration is complicated. Also,
The moving state detecting device that detects the speed based on only the cycle of the displacement signal has a problem that the speed detection accuracy is extremely coarse when the moving body is moving at a low speed.

The present invention has been made in view of the above problems,
It is an object of the present invention to provide a moving body moving state detecting device capable of detecting a high-precision speed or acceleration irrespective of the speed of a moving body without complicating a circuit configuration.

"Means for Solving the Problem" In order to solve such a problem, in the present invention, a value of a displacement signal having a constant displacement of the moving object as one cycle is sampled at a predetermined sampling frequency, and the displacement signal is 2
Sampling means for converting the serialized pulse train into a serialized pulse train, holding means for sequentially taking in the serial pulse train, and holding a pulse train for a certain period from the past to present, and moving based on the pulse train held by the holding means Computing means for detecting the speed or acceleration of the body.

[Operation] A value of a displacement signal having a constant displacement of the moving object as one cycle is sampled by a sampling means at a predetermined sampling frequency and converted into a serialized pulse train of a binary signal. Then, the serial pulse train is sequentially taken in by the holding unit, and the pulse train for a certain period from the past to the present is held. The speed or acceleration of the moving object is detected by the calculating means based on the pulse train.

"Example" Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the embodiment. In this figure, a signal S1 is a displacement signal having a constant displacement of a moving body (not shown) as one cycle, and is, for example, an output from a linear encoder. The frequency of this signal S1 is proportional to the speed of the moving object. The signal S1 is supplied to the sampling circuit 1 after amplitude adjustment or the like is performed as necessary. In the sampling circuit 1, the signal S1
Is converted into a signal S2 of a serial pulse train of a binary signal. The signal S2 output from the sampling circuit 1 is supplied to the shift register 2. Further, the sampling circuit 1 and the shift register 2 are supplied with a clock signal CL having a frequency twice or more as high as the frequency of the signal S1. The shift register 2 is composed of 8 bits, and employs a FIFO (first in first out) system in which data stored earlier comes out first. That is, in accordance with the edge change of the clock signal CL, the contents are sequentially shifted from the lower bits to the upper bits, the MSB (most significant bit) is discarded, and the signal S2 is taken into the LSB (least significant bit) of the shift register 2. It has become. The contents of the shift register 2 are supplied to a CPU (microprocessor) 3 as parallel data PD. The CPU 3 calculates a speed and an acceleration of the moving object by performing a predetermined operation described later based on the bit pattern of the supplied parallel data PD.

Next, the operation of this embodiment having the above configuration will be described.

When the moving body moves, a repetitive waveform signal having a constant displacement as one cycle, that is, a displacement signal S1, is supplied to the sampling circuit 1 in accordance with the position change of the moving body (see FIG. 2A). The sampling circuit 1 receives the clock signal CL
(See FIG. 2 (b))
The signal S1 is converted into a serial pulse train signal S2 (see FIG. 2 (c)). Signal converted to serial pulse train
S2 is supplied to the shift register 2 (see FIG. 2 (d)).

The operation of the shift register 2 will be specifically described. At time t ₁ the shift register 2 is shown in FIG. 2 (c), the holding pulse train shown in FIG. (D). Next, at time t ₁ shown in FIG. 2 (c), the shift register 2 in synchronization with the edge of the clock signal CL, the lower bits to the upper bits sequentially discard the MSB bit to move the contents ( (See FIG. 2 (e)). Then, the signal S2 at the time when the edge of the clock signal CL changes is fetched and set as a new LSB bit (see FIG. 2 (f)).

Thus, each time the edge of the clock signal CL changes, the signal S1 is sampled by the sampling circuit 1, and the sampled signal S2 is taken in as the LSB of the shift register 2. That is, the shift register 2 always has a bit (LS) representing the current state of the moving object.
The state of the signal S2 from B) to the bit (MSB) representing the past state of the moving object by the number of bits (8 bits) of the shift register 2 is held. The pulse train of the signal S2 held in the shift register 2 is supplied to the CPU 3 as parallel data PD. CP supplied with parallel data PD
U3 performs the operation described below.

In the bit pattern of the parallel data PD described above, as shown in FIG. 3, "1" to "0" or "0"
K is the number of points changing from “1” to “1”, T is the sampling period,
Assuming that the number of bits of the shift register 2 is n and the amount of movement corresponding to one cycle of the displacement signal is λ, the distance moved during sampling n times is λ · k / 2. Therefore, the average speed v during this time is And is proportional to k, so the number of bit transition points is
By counting by the CPU 3, the average speed v of the moving object is detected.

Also, as shown in FIG. 4 (a), when the above-mentioned bit change points are gathered on the MSB side (past),
This indicates that the moving object is decelerating (Fig. 4 (b)
5), the bit change point is LS as shown in FIG.
When it is gathered on the B side (current), it indicates that the moving body is accelerating (see FIG. 5 (b)). Therefore, the center of gravity of the distribution of bit change points in the bit pattern of the shift register 2 corresponds to acceleration and deceleration of the moving object. Therefore, the acceleration a is Becomes By calculating this equation (2) by the CPU 3, the acceleration a of the moving body is detected. However, in this case,
Pi is the position of the i-th change point (i is counted from the MSB side),
m is the number of change points. The correspondence between the center of gravity of the bit change point distribution and the acceleration and deceleration of the moving object is limited to the case where the acceleration and deceleration change sufficiently slowly with respect to the sampling cycle.

As described above, by calculating the bit pattern of the parallel data PD output from the shift register 2 by the CPU 3, the speed and acceleration of the moving object can be detected.

The signal S1 supplied to the sampling circuit 1 is not limited to a sine wave having a constant amplitude, but may be a binary pulse signal that has been binarized in advance.

[Effects of the Invention] As described above, according to the present invention, a displacement signal having one cycle of a constant displacement of a moving body is converted into a serial pulse train by a sampling unit, and the serial pulse train is sequentially captured by a holding unit. By holding the pulse train for a certain period from the current time to the present and processing this pulse train by the arithmetic means, there is an advantage that the speed or acceleration of the moving body can be detected without complicating the circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the operation of the embodiment, and FIG.
FIG. 4, FIG. 4 and FIG. 5 are explanatory diagrams for explaining the bit pattern of the shift register according to the embodiment. 1 ... sampling circuit (sampling means) 2 ...
Shift register (holding means), 3... CPU (arithmetic means).

Claims (1)

(57) [Claims] A sampling means for sampling a value of a displacement signal having a constant displacement of a moving object as one cycle at a predetermined sampling frequency and converting the displacement signal into a serial pulse train of a binary signal; It is characterized by comprising a holding means for sequentially taking in and holding a pulse train for a certain period from the past to the present, and a calculating means for detecting the speed or acceleration of the moving body based on the pulse train held in the holding means. A moving state detection device for a moving object.