JP2742955B2 - Synchronous switch mode power supply - Google Patents

Description

The present invention relates to a switch mode power supply.

BACKGROUND OF THE INVENTION Certain television receivers include an input signal terminal for receiving an external video input signal, such as an R, G, B color video input signal, generated on a common ground conductor of the receiver. Have. Such an input signal terminal and a common conductor of the receiver are coupled to a corresponding signal terminal and a common conductor of an external device such as a VCR or a teletext decoder.

To simplify the coupling of signals between the external device and the television receiver, the receiver and the common ground conductor of the external device are interconnected so that all of these conductors are at the same potential. Is done. The signal line of each external device is coupled to a corresponding input signal terminal of the receiver. In such an arrangement, the common conductor of each device, e.g., the television receiver's common conductor, is "floating" with respect to the corresponding AC mains power that energizes the device, i.e., is conductively isolated Is held. If the common conductor is kept floating, even if the user touches the terminal at the potential of the common conductor, the user will not receive an electric shock.

The floating common ground conductor is generally isolated from the potential at the terminals of the AC mains power supply which supplies power to the television receiver by means of a transformer. Floating, or isolated, common conductors are sometimes referred to as "cold" ground conductors.

In a typical switch mode power supply for a television receiver, the AC mains voltage is coupled directly to the bridge rectifier without using transformer coupling. An unregulated direct current (DC) input supply voltage is generated with respect to a common conductor, referred to as "hot" ground, which is conductively separated from the cold ground conductor. A pulse width modulator controls the duty cycle of the jumper transistor switch that provides an unregulated supply voltage across the primary winding of the separating flyback transformer. A flyback voltage at a frequency determined by the modulator is generated on the secondary winding of the transformer,
This is rectified to produce a DC output supply voltage, such as the B + voltage that energizes the horizontal deflection circuit of the television receiver. The primary winding of the flyback transformer is, for example,
It is conductively coupled to the hot ground conductor. The secondary winding and the B + voltage of the flyback transformer are conductively separated from the hot ground conductor by a hot-cold barrier formed by the transformer.

In order to prevent unnecessary visible patterns and artifacts (unintentional display) from appearing in the image displayed on the television receiver, it is desirable to synchronize the operation of the chopping transistor with the horizontal scanning frequency. .

In addition, it may be desirable to couple the horizontal sync signal referenced to cold ground to a pulse width modulator referenced to hot ground so that separation can be maintained.

<Summary of the Invention> The invention described in claims 1 and 2 has a main object of realizing a configuration of a switch mode power supply that operates in synchronization with horizontal deflection with an advantageous configuration. According to the first and second aspects of the present invention, the above-described switch mode power supply can be realized with an advantageous configuration.

A synchronous switch mode power supply according to claim 1, comprising a transformer (T1) having first and second windings (W1, W3), a first switching means (Q1), and a synchronous input signal (V _H ). Signal source,
And second switching means (Q4), and generating means for generating a periodic control signal (V ₃₀₎ (Q30), detecting means (U3)
And an input supply voltage source (V _UR ) and output supply voltage generating means (Q2, W5). The first switching means (Q1) is coupled to the first winding (W1) and generates a switching current (i ₁ ) in the first winding to generate a second winding (W3). Energize periodically. The second switching means (Q4) is coupled to the second winding (W3) and is responsive to a synchronization input signal (V _H ) across the energized second winding. , Periodically coupling the low impedance, which causes a large increase in the switching current (i ₁ ) by the transformer action. The detecting means (U3) responds to the switching current and generates a control signal (V ₃₀ ).
30) to detect an increase in the switching current and synchronize the control signal with the synchronization input signal. The output supply voltage generating means (Q2, W5) is coupled to the input supply voltage in response to the control signal, and generates an output supply voltage (B +) from the input supply voltage in response to the control signal.

The switch mode power supply according to claim 2 further comprises a voltage source (100) of an input supply voltage (V _UR ), output supply voltage generating means (Q2, W5, W6, Q2), and first and second windings. Transformer (T1) having (W1, W4) and first switching means (Q1)
, A capacitor (C3), and a second switching means (D
3) and control means (Q) for controlling the first control voltage (V ₃ )
5, Q3), rectifying means (D _W2 ), and sawtooth signal generator (R1
20, R121, C12, D12, U2) and control signal generating means (U4)
And, it is equipped. Its output supply voltage generating means (Q2, W
5, W6, Q2) is biased by the input supply voltage, in response to the modulated control signal (V _7), the modulated timing regulated output supply voltage according to the modulation of the control signal (B +) Derived from the input supply voltage. The first switching means (Q1) is coupled to the first winding;
Operating at a predetermined frequency, a switching current (i ₁ ) is generated in the first winding to energize the second winding (W4). The second switching means (D3) is coupled to the second winding and the capacitor (C3), rectifies the current flowing in the second winding, and rectifies this current from the flyback period (V _H ) To generate a rectified current which flows through the capacitor to generate a first control voltage (V ₃ ) in the capacitor. The capacitor (C3), when a rectified current is generated, is coupled to the second winding via the second switching means to supply a first control voltage to the second winding, , A second control voltage is generated in the windings. The control means (Q5, Q3) is responsive to the output supply voltage and is coupled to the capacitor, and a second change in the magnitude of the output supply voltage from a normal value is generated in the second winding. The first control voltage (V ₃ ) is controlled to cause an amplified change in the magnitude of the control voltage. The rectifying means (D _W2 ) is coupled to the transformer, the second control voltage being coupled via the transformer when a rectified current is being generated during flyback, and the transformer coupled second 2
Is rectified to generate a third control voltage (V ₆ ) at a level determined by the second control voltage. Its saw-tooth signal generator (R120, R121, C12, D12 , U2) , in response to the third control voltage, generates a sawtooth signal (V ₁₂₀₎ in accordance with a second control voltage. The sawtooth signal is generated partially outside the flyback period. Further, the control signal generating means (U4), in response to the saw-tooth signal, adjusting a first modulated control signal (V ₇₎ output supply voltage to generate having Tamiingu modulation which varies in accordance with the control voltage I do.

A synchronous switch mode power supply embodying one aspect of the present invention includes a transformer having first and second windings. First
A first switching arrangement is coupled to the first winding to generate a first switching current in the first winding that periodically energizes the second winding. In addition, a signal source of a synchronous input signal having a frequency related to the deflection frequency is provided. In response to the input signal, a second switching arrangement coupled to the second winding causes the activated second switching current to cause a substantial increase in the first switching current by transformer action.
Periodically supplies a low impedance across the windings. A periodic first control signal is generated, and an increase in the first switching current is detected to synchronize the second control signal with the input signal. An output supply voltage is generated from the input supply voltage according to a first control signal.

<Description of Embodiment> FIG. 1 shows a switch mode power supply (SMPS) 300 embodying one embodiment of the present invention. Switch mode power supply 300 powers a regulated B + output supply voltage of +145 V, for example, used to power the deflection circuitry of a television receiver (not shown), and a remote control receiver of the television receiver. To generate an adjusted output supply voltage V +.

Main power voltage V _AC is rectified in Buritsuji rectifier 100, voltage V _UR unregulated is generated. The primary winding W5 of the chip flyback transformer T2 is coupled between terminal 100a and the drain electrode of a power MOS field effect transistor (MOSFET) Q2. The source electrode of transistor Q2 is connected to a common conductor, which is referred to herein as hot ground. Transistor Q2 pulse width modulated control signal generated by the pulse width modulator 101, i.e., is switched Te voltage V ₇ Niyotsu.

The primary winding W1 of the flyback transformer T1 is coupled between the terminal 100a at which the voltage V _UR appears and the collector electrode of the switching transistor Q1 included in the pulse width modulator 101. Emitter of the transistor Q1 is coupled to Hotsuto ground through the emitter current sampling resistor R10, across resistor R10, the voltage V ₅ which is proportional to the collector current i ₁ of the transistor Q1 is generated.

2a to 2j show waveforms for explaining the normal steady-state operation of the switch mode power supply of FIG. 1 and 2, the same reference numerals and numbers indicate the same elements or functions.

A given cycle of switching operation, i.e.
In a period t ₁ ~t ₄ in FIG. 2 f of period, the base voltage V ₁₀ of the transistor Q30 in FIG. 1 a is a 0V, whereby the positive pulse voltage V ₃₀ to the collector of the transistor Q30 is generated. Voltage V ₃₀ is coupled to the base of transistor Q1 via the network 81, time t ₁ the transistor Q1 in FIG. 2 d
Turned in ~t _4. The diode D20 in FIG. 1b is connected between the collector of the transistor Q30 and the gate electrode of the transistor Q2. Positive pulse voltage V ₃₀ is reverse biased diode D20.

In the period t ₂ ~t ₄ in FIG. 2 h, the transistor Q40 in FIG. 1 a becomes non-conductive, in conjunction with diode D20, voltage V _6a that is coupled via a resistor R30 to the gate electrode of the transistor Q2 the positive voltage V ₇ to be produced. The positive voltage V ₇ so that the transistor Q2 is turned on in the period t ₂ ~t ₄ in Figure 2 j. As a result, the corresponding FIG.
And the current i ₁ increasing (jumping) above
i ₂ flows into each of the windings W1 and W5 in FIG. 1 b, transformer T1
And store inductive energy in T2.

According to one aspect of the invention, switching transistor Q4 is coupled across secondary winding W3 of transformer T1 via diode D400 and low resistance current limiting resistor R400. When transistors Q1 and Q2 are conducting, transistor Q4 is turned on. Transistor Q4 is Yotsute turn fly-back pulse V _H of horizontal frequency is taken from the horizontal deflection circuit. The pulse _VH is supplied to the base of the transistor Q4. As a result, at time t ₃ in FIG. 2 d that occur during the horizontal retrace period of the signal V _H in Figure 2 a, the transistors Q4 in FIG. 1 b is wound a low impedance burden the transformer T1 W3 given across, thereby, by the transformer action connexion, as a result of the transformer coupled low impedance, causing step-like increase in the collector current i ₁ of the transistor Q1.

The collector current i ₁ of the transistor Q1, a sense voltage V shown in FIG. 2 d across the sampling resistor R10 in Figure 1 b
₅ cause, the voltage V ₅ via the Kiyapashita C11 terminal
11 are joined to form a voltage V ₁₁ on. Step-like increase of the current i ₁ in Figure 2 d at time t ₃ causes an increase in the step-like voltage V ₁₁ shown in FIG. 2 e at the terminals 11 of Figure 1 a. After step-like increase in the time t _3, the current i ₁ in Figure 2 d each voltage V ₁₁ in FIG. 2 e is
It continues to increase in an asymmetric manner at a rate determined by the inductance of the winding W1. Voltage V ₁₁ appears at the inverting input terminal of the comparator or amplifier U3,. Amplifier U3 is switching-signal is coupled to the base of the transistor Q30, that is, an output terminal for generating the voltage V _10.

Emitter current sampling resistor R10 of transistor Q1
Amplifier U3, transistor Q30, and transistor Q1 form an oscillator due to a positive feedback path through capacitor C11 coupled between the terminal and terminal 11. Terminal 11 is coupled to the inverting input terminal of comparator U3 and the amplifier, ie, the inverting input terminal of comparator U2.

According to one feature of the present invention, the signal V _H which is coupled to the oscillator via a low impedance formed by the transistor Q4 is synchronized with the horizontal scanning frequency timing switching-in Suitsuchimodo power supply 300. This synchronization is desirable so as not to cause unwanted disturbances in the displayed image.

The voltage V ₁₁₁ from the voltage V _6a is generated via a voltage divider had it occurred in forming the resistor R200 and R201. Diode D202 forward to the output terminal of amplifier U2 from the non-inverting input terminal of amplifier U2 the voltage V ₁₁₁ is generated is coupled. The output terminal of amplifier U2 is coupled to terminal 11 via a relatively small resistor R112 and to one pole of capacitor C12 via a diode D12. The other plate of capacitor C12 is coupled to hot ground.

The time t _{4 in} FIG. 2d is followed by an up-slope ramping of the current i ₁ between times t ₃ and t ₄ , which
followed step-like increase described above in t _3. At time t _4, the voltage V ₁₁ of FIG. 2 e is greater than the voltage V _111. As a result, the voltage at the output terminal of amplifier U2 is zero with respect to hot ground. Accordance connexion, voltage V ₁₁ is clamped to 0V through a resistor R112 from the output terminal of the amplifier U2, which in Yotsute, to rapidly discharge the Kiyapashita C11. at the same time,
It sawtooth voltage V ₁₂ across the Kiyapashita C12 being filled from the voltage V _6a via a resistor R120 and R121 until is clamped to 0V through the diode D12. Conductive to have the diode D202 is a voltage V _111, to be clamped considerably small value causes Shiyumitsutotoriga operation in the amplifier U2.

DC voltage V ₁₁₀ appears at the non-inverting input terminal of the comparator U3.
Voltage V ₁₁₀ is produced from O connexion voltage V _6a to the resistance voltage divider. At time t ₀ or t ₄ in FIG.
₁₁ as a result of the clamping operation by the resistance 220 of FIG. 1, is smaller than the voltage V _110. Accordance connexion, the output signal V ₁₀ in FIG. 2 f at the output of the comparator U3 of Figure 1, the binding of the result of the voltage V _6a by Puruatsupu resistor R _PU, increases. Second
At time t ₄ in FIG f, the signal V ₁₀ that is coupled to the base of the drive when to quenching transistor Q30 of Figure 1 turns on the transistor Q30.

When transistor Q30 turns on, transistor Q
Both 1 and Q2 are turned off. As a result, during flyback operation, the inductive energy stored in the transformer T2 is transmitted through the secondary winding W6 and through the diode D6.
Transferred to capacitor C66 to generate output supply voltage B +. Similarly, a voltage V + is generated through winding W7.

Similarly, the energy stored in the transformer T1 turns on the diode D3 and causes the flyback switching current to continue to flow through the capacitor C3, thereby reducing the secondary winding of the transformer T1.
W4. Accordance connexion, Kiyapashita C3, after the time t ₀ in FIG. 2 b, winding through the scan Germany quenching diode D3 W4
Is connected between both ends. As a result, the DC control voltage shown in FIG.
V ₃ is generated in the Kiyapashita C3. The magnitude of the voltage V _3, as described below, can be controlled. Control voltage V ₃ in Kiyapashita C3 is coupled to the secondary winding W2 of transformer T2 by transformer action, it is by connexion rectifier diode D _W2 generates a control voltage V ₆ to filter wire carrier path Sita C6.

During normal operation, the transistor Q8 in FIG. 1 a operates as a conductive switch combines the voltage V ₆ to filter wire carrier path Sita C _6a, to form a voltage V ₆ is substantially equal to the control voltage V _6a. The ratio of the voltage V _6a for the voltage V _3'm connexion determined winding ratio of the winding W4 and W2.

After a time t ₀ or t ₄ in Figure 2 e, the Kiyapashita C ₁₁ in Figure 1 a is discharged, the output terminal of the amplifier U2 of FIG. 1 to form a high impedance. Accordance connexion, for example, during the period t ₀ ~t ₄ in Figure 2 e, a current flowing through the resistor R111 and R112 in FIG. 1 a is charged Kiyapashita C11, the current flowing through the resistor R120 and R121 is charged Kiyapashita C12 I do.

At time t _0, the resistance R120 and the voltage V ₁₂₀ of the interconnection point of R121 is level V _DC (second is by connexion control voltage V _6a in Figure 1 a
Figure g). After a time t _0, the voltage V ₁₁ and V in FIG. 2 e and g
Each ₁₂₀ Atsupuranpu to increase in by connexion determined change rate of the voltage V ₃ of Kiyapashita C3. As apparent from FIG. 2 g, the long portion ones of Atsupuranpu portion of the sawtooth voltage V ₁₂₀ is generated outside the horizontal flyback period (Figure 2 a).

At time t ₁ in Figure 2 e, the voltage V ₁₁ is the first diagram amplifier U3
It exceeds the voltage V ₁₁₀ that is generated in the non-inverting input terminal. Accordance connexion, at time t ₁ in Figure 2 e, the transistor of Figure 1
Q30 is turned off, turning on transistor Q1 as previously described.

Time later in the cycle, at time t ₂ in FIG. 2 g, voltage Atsupuranpu the inverting input terminal of amplifier U4
V ₁₂₀ exceeds the reference voltage REF at the non-inverting input terminal. As a result, the transistor Q40 becomes nonconductive, due it connexion, a positive voltage V ₇ to the base of the transistor Q2 is generated. Thus, as previously described, and as shown in FIGS. 2h-j, transistor Q2 begins to conduct. As described below, the transistor Q2 of FIG. 1 is non-conducting, the length of time t ₀ ~t ₂ in FIG. 2 j becomes longer as the voltage V ₃ decreases, shorter with increasing.

Diode D20 protects transistor Q2 by preventing the duty cycle of transistor Q2 from becoming greater than the duty cycle of transistor Q1. When such protection is not performed, for example, the voltage V shown in FIG.
_If the level _{VDC of 120} rises above the voltage REF, the transistor Q2 of FIG. 1 will be destroyed.

Resistance R301 of the network 81 so that the gate voltage V ₇ can become higher than the gate threshold voltage. When transistor Q30 conducts, diode D10 bypasses resistor R301, which speeds up the switch-off time of transistor Q1.

When the horizontal fly-back pulses V _H at time t ₃ in FIG. 2 C occurs, transistor Q4 is saturated, as previously mentioned, to short-circuit the winding W3 of transformer T1. Therefore, the current i _{1 of the} transformer T1
There rapidly increases at time t ₃ in Figure 2 d. The resulting how the increase in current as the current i _1, which is described in 1989 September 13 Yorotsupa Patent Application No. 0,332,095 published.

At time t ₄ in Figure 2 e, the voltage V ₁₁ is higher than V _111, triggers an oscillator formed by amplifier U2 and U3, as described above. Thus, transistors Q1 and Q2 are both switched off and a new cycle begins.

Cold ground control circuit of Figure 1 b where the reference is placed on conductor 120, by varying the control voltage V ₃ across the Kiyapashita C3, the voltage at the base of V ₇ of the transistor Q2
Control the duty cycle. Transistor Q5 of circuit 120 is coupled to a common base amplifier configuration. The base voltage of the transistor Q5 can be obtained via the temperature compensated voltage + 12V. A resistor R3 is connected between the emitter of the transistor Q5 and the voltage B +. Common base operation results, the current i ₈ in resistor R3 is proportional to the voltage B +. An adjustable resistor R4 used to adjust the level of the emitter voltage is connected between the cold ground conductor and the emitter of transistor Q5. Resistor R4 is used to adjust the level of current flowing through transistor Q5. Accordance connexion, a preset portion of the adjustable current i ₈ flows to the cold ground conductor through resistor R4, an error component of current i ₈ flows through the emitter of transistor Q5.

The collector current of transistor Q5 is coupled to the base of transistor Q3 to control the collector current of transistor Q3. Transistor forming high output impedance
The collector of Q3 is coupled to the interconnection point of capacitor C3 and diode D3.

When transistor Q1 is turned off, the stored energy in transformer T1 causes the switching current to charge capacitor C3 to flow through diode D3, as previously described. Adjustment of the power is done by controlling the control voltage V ₃ of Kiyapashita C3. Voltage V ₃ is Yotsute the transistors Q3, is controlled by controlling both ends load applied between the winding W ₄ of the transformer T1. For example, as the supply current load across capacitor C66 decreases, voltage B + tends to increase.

Figure 3 a~f, when the voltage of FIG. 1 B + is increased, for example, is a waveform diagram for explaining the operation of the circuit of FIG. 1 after time t ₄₀ of FIG. 3 a~f . 1, 2 and 3, like numerals and numbers indicate like elements or functions.

Figure 1 b the voltage B + of the above-mentioned results of such temporary excessive levels, large base current and resistor R3 and the transistor Q5 to passing connexion transistor Q3 flows, the voltage V ₃ of Kiyapashita C3 decreases. Accordingly, the voltage V ₆ generated as a result of voltage rectification during flyback operation in winding W2 of transformer T1
And V _6a also become smaller. As a result, the level V _DC of the voltage V ₁₂₀ at the start of the predetermined up-pump portion of the voltage V _{120 in} FIG. 3c is reduced. Such a decrease in the level V _DC of the voltage V ₁₂₀ is shown in FIG. _3c as a change from the level V _DC1 to the level V _DC2 . Thus, the voltage V ₁₂₀ in FIG. 1a will exceed the voltage REF at a later time during a given cycle, thereby, as shown in FIGS. The duty cycle is reduced. The transformer shown in Fig. 1
Less energy is stored in T2 from which it is transferred to the load at the terminal where the voltage B + is generated. Thus, the adjustment of the voltage B + is performed.

In the steady state, voltage V ₃ is stabilized at a level as given equilibrium between charging and discharging of Kiyapashita C3. Voltage B
Increase from normal (+) value, as a result of amplification and current integration of the collector current in transistors Q3, greater than proportional to the voltage V ₃ to increase the voltage B +, i.e., can produce an amplified change .

Processing of the voltage B + for producing control voltage V _3, in order to improve the detection of an error is carried out in the signal path is DC coupled. Proportional given change with voltage B + is capable of producing more proportional thereto a large change in voltage V _3. Accordingly, error sensitivity is improved. Only after the voltage B + error of the amplified, the amplified error contained in the voltage V ₃ that is DC coupling transformer coupled to winding W2,
Alternatively, AC coupling is performed. The combination of these features improves the regulation of voltage B +.

Another method of using a configuration similar to control circuit 120 for adjustment purposes is shown in U.S. Patent Application No. 424,354, filed October 19, 1989.

According to another feature of the invention, the transformer T1 has the synchronization signal V _H
And a control voltage V ₃ which is derived from the voltage B + to bind to the separation barrier over. This coupling both signals V _H and the voltage B + is with respect to electric Shiyotsuku effected as separated from the mains voltage V _AC.

Switching of the television receiver to the standby operation mode is performed by turning off the transistor switch Q6. The collector of the transistor switch Q6 is composed of a Zener diode Z9.1, a resistor R60 and a diode D.
It is coupled into a current path formed by 60 series connected configurations. This series configuration is coupled between the collector and base of transistor Q3.

When the transistor Q6 is turned off, the Zener diode Z9.1, a negative feedback current through resistor R60 and diode D60 to the base of the through connexion transistor Q3 sets the voltage V ₃ to a low of about + 12V from the normal operation. As a result, the voltage V ₆ is maintained at + 15V, the level of the voltage V ₁₂₀ at the inverting input terminal of the amplifier unit U4 is maintained at about + 7V. As a result, the peak voltage of the sawtooth voltage V ₁₂₀ can not exceed the voltage REF. Therefore, transistor Q2 is kept off during the entire standby operation.

Throughout normal operation, the voltage V _6a generates a base current to the transistor Q7 through the Zener diode Z18B. When conducting, transistor Q7 couples the anode of diode D110 to hot ground. Therefore, diode D1
Voltage V ₁₁ at the cathode of 10 to maintain the diode D110 to the non-conductive state.

The free running frequency of the oscillator formed by amplifiers U2 and U3 is set lower than the horizontal frequency to enable synchronization. Standby operation because the voltage V ₆ decreases, the transistor Q7 is turned off. Therefore, Capashita
C11 is charged by the additional current flowing through collector pull-up resistor R110 and diode D110. As a result, the free-running frequency of the oscillator increases beyond the audible range, so that audible interference can be prevented.

During standby operation, the voltage V + used to power the infrared remote control receiver (not shown) is a switch diode.
By the voltage V ₃ through D200 is connexion supply. On the other hand, during normal operation, the diode D200 is reverse-biased and the voltage V +
Is generated from the rectified voltage generated by transformer T2 and coupled through switch diode D201. Because of the switching mode operation of the transistor Q1, the power loss during the standby operation is reduced.

Switching of the receiver to the normal operation is performed by turning on the transistor Q6. Yotsute thereto, the DC level V _DC voltage V _3, V ₆ and the voltage V ₁₂₀ increases, it is possible that the transistor Q2 conductive.

If a fault occurs, for example, in the example, when Kiyapashita C66 is shorted, Suitsuchimodo power supply 300, for example, as shown in FIG. 4 a to c, a relatively long stationary (Detsudo) period t ₅₁ ~t ₅₂ starts the operation of the intermittent mode during the time that follows t ₅₀ and t _51. In FIG. 1 and FIGS. 4a to 4c showing the above-mentioned failure states, the same reference numerals and numbers indicate the same elements or functions.

If a short circuit as described above has occurred, a larger current i ₆ flows through the winding W6 of transformer T2 of FIG. 1, the resistor is coupled between the lower end and the cold ground of the winding W6 R66 , A larger negative voltage _V66 is generated. This allows
For example, at time t ₅₁ in FIG. 4 a to c, coupled with that diode D62 and D63 between the base and the resistor R66 of the first view of the transistor Q6 becomes conductive, the transistor Q6 becomes cut-off, the transistor Q3 is clamping the voltage V ₃ to about + 12V. As a result, transistor Q2 is switched off, as described above for the standby operation.

After the fourth Figure a~c time t _51, the transistor Q6 becomes conductive again, disconnecting the Zener diode Z9.1 and the resistor R60 from the base of the transistor Q3. Thus, as shown in FIG. 4 a, it rises to the voltage V ₃ Gayu made. as a result,
At time t _52, transistor Q2 of FIG. 1 is turned on. However, due to a short circuit on the secondary side of transformer T2, FIG.
In the time t _53, as mentioned before, transistor Q2 of FIG. 1 is again Suitsuchiofu.

Power, i.e., after the voltage V _AC is supplied immediately Kiyapashita C300 is charged with part of the cycle of voltage V _AC. Accordingly, the voltage V _UR appears on the capacitor C300. Voltage V _UR is coupled to capacitor C6 through resistor R300 to charge it prior to normal operation.

Amplifier U1 is an inverting input terminal coupled to the voltage V ₆ and the voltage RE
A non-inverting input terminal coupled to F. Voltage V _AC
After There was first applied, the voltage V ₆ of Kiyapashita C6 voltage
After being large enough to exceed a predetermined minimum level determined by REF, the output voltage of amplifier U1 is pulled down to hot ground. As a result, the transistor switch Q8
Is turned on to the saturation state, and the voltage V ₆ is transferred to the capacitor C _6a.
To join. Thus, the switch mode power supply 300
Starts operating at a voltage V ₆ of the appropriate level.

Figure 5 a~c is a waveform diagram for explaining the above-described start up-operation of the circuit of FIG. 1 after the voltage V _AC in Figure 1 is initially added. Like numbers and numbers in FIGS. 1 and 5 indicate like elements or functions.

At time t ₆₀ of FIG. 5 c, the voltage V ₆ of FIG. 1 is sufficiently high, transistor Q2 begins to conduct. Fifth
In the first period t ₆₀ ~t ₆₁ in FIG. A to c, Kiyapashita C66 is in the discharged state. Therefore, the switch mode power supply shown in FIG.
The 300 operates in the intermittent mode similarly to the case of the secondary side short circuit described above. However, the energy supplied slowly charges the capacitor C66 on the secondary side of the transformer T2 in FIG. 1 to increase the voltage B +. At time t ₆₁ in FIG. 5 a, voltage B + is sufficiently high connexion, transistor Q2 of FIG. 1 b
Will now receive the appropriate base drive. Turn of the process, as indicated at time t ₆₂ in FIG. 5 a, and ends with + voltage B reaches the value of its normal.

[Brief description of the drawings]

FIG. 1 is a diagram showing a power supply embodying one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining a run mode operation of the circuit of FIG. 1 when the load is constant, and FIG. FIG. 4 is a waveform diagram for explaining the run mode operation of the circuit of FIG. 1 when the load fluctuates. FIG. 4 is a waveform diagram of the circuit of FIG. 1 under an overload condition. FIG. 3 is a diagram showing transient waveforms for explaining the operation of the circuit of FIG. 1 at the time of start-up. In claim 1, T1 ... transformer, W1, W3 ... first and second windings, Q1 ... first switching means, _VH ... synchronous input signal, Q4 ... second switching Means, U2, U3 ... means for generating a first control signal, R10 ... means for detecting an increase in the first switching current, V _UR ... input supply voltage, Q2 ... output supply voltage generation means.

Claims (2)

(57) [Claims] A transformer having first and second windings, coupled to the first winding, generating a switching current in the first winding to produce a second winding; A first switching means for periodically energizing a signal; a signal source of a synchronization input signal having a frequency related to the deflection frequency; and a second winding coupled to the second winding, and responsive to the synchronization input signal, A second switching means for periodically coupling a low impedance across the energized second winding, which causes a large increase in the switching current by transformer action; Means for generating the control signal in response to the switching current, the means for detecting the increase in the switching current and synchronizing the control signal with the synchronization input signal; Supply voltage Source and, in response to said control signal, being coupled to the input supply voltage, synchronous switch mode power supply and means for generating an output supply voltage from the input supply voltage in response to said control signal. 2. A voltage source for an input supply voltage, and an output supply voltage regulated by a timing modulation of the modulated control signal in response to a modulated control signal energized by the input supply voltage. Means for generating from an input supply voltage, a transformer having first and second windings, coupled to the first winding, operating at a predetermined frequency, A first switching means for generating a switching current to energize the second winding; a capacitor; coupled to the second winding and the capacitor;
The current flowing through the second winding is rectified, and from this current,
Second switching means for generating a rectified current flowing through the capacitor during the flyback period to generate a first control voltage at the capacitor, wherein the capacitor generates the rectified current. Is connected to the second winding via the second switching means, supplies the first control voltage to the second winding, and applies the second control voltage to the second winding. And responsive to the output supply voltage and coupled to the capacitor, wherein a change in the magnitude of the output supply voltage from a normal value is applied to the second winding. Control means for controlling the first control voltage to cause an amplified change in the magnitude of the generated second control voltage; coupled to the transformer; and The rectified current The second control voltage is coupled through the transformer as it is being generated, and the transformer coupled second control voltage is rectified to provide a third control at a level determined by the second control voltage. Means for generating a voltage, and a sawtooth signal generator for generating a sawtooth signal in accordance with the second control voltage in response to the third control voltage, wherein the sawtooth signal has a part thereof. Generating a modulated control signal having a timing modulation that varies in accordance with the first control voltage in response to the sawtooth signal and generating the modulated control signal in response to the sawtooth signal. Means for regulating the switch mode power supply.