JP2739843B2 - Automatic layout method for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic layout method for a semiconductor device, and more particularly to a semiconductor device in which a buffer is arranged at an optimum insertion position of a critical net when improving the delay characteristics of a critical net existing between functional cells. Automatic layout method.

[0002]

2. Description of the Related Art Conventionally, as an automatic layout method in a semiconductor device, in order to reduce a delay amount in a critical net on a wiring, a wiring method for inserting a buffer into the critical net and optimizing an insertion position of the buffer is adopted. Has been proposed. For example, Japanese Patent Application Laid-Open No. 4-233
No. 47, Japanese Unexamined Patent Publication No. 4-282772, etc. disclose the wiring method. Hereinafter, with reference to FIG. 3, the gist of the contents of the above-mentioned Japanese Patent Application Laid-Open No. Hei 4-23347 will be described.

In FIGS. 4 (a) and 4 (b), after automatic placement or wiring in the layout of a semiconductor device, a buffer 3 is inserted between the functional cells 1 and 2 assuming that it is a critical net. Shall be. In this case, the delay caused by the wiring increases in proportion to the square of the wiring length.
According to the proposal of JP-A-47-47, assuming that the wiring length L between the functional cell 1 and the functional cell 2 is constant, the wiring length L ₁ of the critical net between the functional cell 1 and the buffer 3 is assumed. Is within a certain length range, the buffer 3 is inserted between the functional cells 1 and 2 so that the critical net between the functional cells 1 and 2 Is sometimes reduced. In other words, the wiring length L ₁₀ between FIGS. 4 (a) definitive functional cell 1 and the buffer 3, appropriately selecting the wiring length L ₁₁ between the functional cell 1 and the buffer 3 shown in FIG. 4 (b) , The buffer 3 and the wiring lengths L ₁₀ and L ₁₁
When the delay amount of the critical net is reduced, the optimum insertion position of the buffer 3 can be obtained by inserting the buffer 3 at a position corresponding to the wiring length within the range.

FIG. 3 shows a delay characteristic 4 when a buffer is not inserted between critical nets, and a delay characteristic 5 when a buffer is inserted. In FIG. 3, the horizontal axis represents the wiring length and the vertical axis represents the delay amount, and points A and B in the delay characteristic 5 when a buffer is inserted.
The difference between the delay amounts is due to the internal delay amount of the buffer 3.

[0005]

In the above-described conventional layout method for a semiconductor device, a buffer is inserted at a position within a certain range between critical nets to reduce the amount of delay between the critical nets. According to this wiring method, the buffer insertion position has a certain width, and the output resistance and input capacitance of the functional cell and the buffer, the internal delay amount of the buffer, and the wiring per unit length Due to the influence of the resistance and the capacitance, there is a disadvantage that the buffer is not always arranged at the optimum insertion position between the critical nets. The disadvantage that the optimum insertion position of the buffer cannot always be obtained is the same as in the case of the proposal of Japanese Patent Application Laid-Open No. 4-282772.

An object of the present invention is to reduce the amount of delay in a critical net when a buffer is inserted into a critical net after placement and routing in a semiconductor device. It is an object of the present invention to realize an automatic layout method of a semiconductor device which can set and optimally insert the buffer and take place and wire in consideration of real circuit factors.

[0007]

An automatic layout method for a semiconductor device according to the present invention is an automatic layout method for automatically arranging and wiring functional cells in a semiconductor device. when inserting at least one or more buffers critical nets between cells, the functional cell, the delay circuit elements due to the critical nets and buffer as a parameter, the
Mathematical analysis of the optimal buffer insertion position using the following procedure
Is calculated .

(1) a wiring resistance value and a wiring capacitance value of the critical net, an output resistance value of the functional cell and the buffer, an input capacitance value of the functional cell and the buffer,
The delay amount T of the critical net is calculated using the actual circuit variation constant value including the internal delay amount inherent to the buffer as a parameter. (2) The wiring length L _i (i
Is to equality a differential coefficient by inserting the number of buffers) to 0, determining the insertion position of the buffer corresponding to the minimum value of the delay amount T as the wiring length L _i from the functional cells. (3) seek delay amount T _min of the critical nets corresponding to the line length L _i, the delay amount of the critical nets when no values for the T _min Insert the buffer T _a
Against values and comparison, when T _a -T _min> 0, placing a buffer at the position of the L _i.

[0009]

Next, the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing a state in which a buffer 3 is arranged in a critical net between a functional cell 1 and a functional cell 2 in a semiconductor device to which one embodiment of the present invention is applied. Hereinafter, a method of obtaining the optimum insertion position of the buffer 3 will be described with reference to FIG.

In FIG. 2, the functional cell 1 and the functional cell 2
In the case where the wiring between these is a critical net, a state where one buffer 3 is inserted into the critical net is shown. Here, assuming that the delay from the output of the functional cell 1 to the input of the functional cell 2 via the buffer 3 is T, the wiring length L of the critical net is L _1.
And L−L ₁ , the delay amount T is given by the following equation.

[0012] _{T = R 1 · (C 0} · L 1/2 + C 3) + R 0 · C 0 · L 1 2/2 + T 3 + R 2 · {C 0 · (L-L 1) / 2 + C 2} + R 0 · C ₀ · (L−L ₁ ) ² (1) In the above equation, R ₁ and R ₂ are the output resistances of the function cell 1 and the buffer 3, respectively, and C ₂ and C ₃ are the functions The input capacitance of the cell 2 and the buffer 3, T ₃ is the internal delay amount of the buffer 3, and C ₀ and R ₀ are the capacitance and resistance per unit length of the wiring, respectively. Delay amount T according to the above equation
Is differentiated by the wiring length L ₁ and is equal to 0, the delay amount T
Wiring length L ₁ to a minimum value is obtained by the following equation.

L ₁ = L / 2− (R ₁ −R ₂ ) / 4R ₀ (2) Therefore, assuming that the buffer 3 is inserted into the critical net, (2) ) buffer position or its vicinity of the wiring length L ₁ obtained by expression 3
Is inserted, the minimum value of the delay amount T in the critical net can be obtained. put it here,
Assuming that the delay amount when the buffer 3 is not inserted is T ′,
The delay amount T 'is given by the following equation.

[0014] _{T '= R 1 (C 0} L / 2 + C 2) + C 0 · R 0 · L 2/2 ............... (3) above (1), (2) and (3) Therefore, the difference between the delay amount T when the buffer 3 is inserted and the delay amount T 'when the buffer 3 is not inserted, when the value of ΔT = T′−T is larger than 0, that is, the following equation (4) is obtained. In the case where it is satisfied, the delay time in the critical net can be improved by inserting the buffer 3.

ΔT = T′−T> 0 (4) In this case, the value of the output resistance R ₃ of the buffer 3 is made smaller. Thus, the delay amount in the critical net can be further improved. Further, even when the wiring length between the functional cells is long and the delay time is further improved by inserting two or more buffers corresponding to this, even if the delay time is further improved, It is possible to insert a buffer at a position where T is minimized.

Next, an automatic layout method for a semiconductor device according to the present invention will be described. FIG. 1 is a flowchart showing an arrangement / wiring procedure of an embodiment of an automatic layout method according to the present invention after initial arrangement or wiring of a semiconductor device. After the initial arrangement or wiring of the semiconductor device is performed, first, a critical net between functional cells is extracted (step 11). Calculation of the optimal insertion position of the buffer, including the size, the number of stages, the driving capacity (output resistance), etc., when the buffer is inserted into the extracted critical net (Eqs. (1) to (3)) (Step 12). Next, it is determined whether or not inserting a buffer into the critical net is effective for improving the delay time of the critical net (see the above equation (4)). Proceeds to step 14, and if it is determined that the data is not valid, proceeds to step 16 (step 13). If it is determined in step 13 that the buffer insertion is effective for improving the delay time of the critical net, the buffer is inserted and arranged at the optimum insertion position in the critical net calculated in step 12 (step 14). Then, wiring between the corresponding function cells is performed (step 15). Next, it is checked whether or not a path corresponding to another critical net exists in the semiconductor device (step 16). The procedure in step 16 is that in step 13, it is necessary to insert a buffer in the critical net. The same is true when it is determined that the delay time is not effective in improving the delay time. If another critical net exists and is extracted in step 16, the process returns to step 12, and the additional buffer placement and wiring procedure after step 12 is repeatedly performed on the critical net. If there is no other critical net in step 16, wiring of the remaining parts other than the critical net is performed (step 17), and the layout processing of the semiconductor device is completed.

As described above, in the automatic layout method including placement and wiring in a semiconductor device, a critical net existing between functional cells is extracted, and an optimum insertion position for inserting a buffer into the critical net is determined. By checking the validity according to the insertion position and then inserting the buffer, the delay characteristics of all the critical nets in the semiconductor device are significantly improved.

[0018]

As described above, according to the present invention, the initial placement or wiring after the layout of a semiconductor device is performed.
After extracting the critical net existing between the functional cells and confirming the validity of the buffer to be inserted into the critical net, determining the optimal insertion position of the critical net, and confirming the validity of the insertion position, By arranging the buffer at the position, there is an effect that the delay characteristics in all the critical nets existing in the semiconductor device can be remarkably improved as compared with the conventional method.

[Brief description of the drawings]

FIG. 1 shows an automatic layout method for a semiconductor device according to the present invention.
FIG. 4 is a diagram illustrating a flowchart in the embodiment.

FIG. 2 is a block diagram between functional cells showing a buffer insertion position of the semiconductor device;

FIG. 3 is a diagram illustrating delay characteristics when a buffer is inserted and when a buffer is not inserted in a critical net of a semiconductor device.

FIG. 4 is a block diagram between functional cells showing a buffer insertion position of a conventional semiconductor device.

[Explanation of symbols]

1, 2 functional cell 3 buffer 4 delay characteristic when buffer is not inserted 5 delay characteristic when buffer is inserted 11 to 17 steps L, L ₁ , L ₁₀ , L ₁₁ Wiring length

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-23347 (JP, A) JP-A-1-292472 (JP, A) JP-A-7-56976 (JP, A) JP-A-59-1979 JP-A-65995 (JP, A) JP-A-4-111341 (JP, A) JP-A-6-21221 (JP, A) JP-A-2-259882 (JP, A) JP-A-4-165647 (JP, A) JP-A-4-184960 (JP, A)

Claims (1)

(57) [Claims] A function cell is automatically arranged in a semiconductor device.
In the automatic layout method of placing and wiring, after the placement or wiring of the functional cells, the clearance between the functional cells is cleared.
Insert at least one buffer into tikal net
In doing so, the functional cells, critical nets and buses
The delay circuit element caused by the buffer
Mathematical analysis of the optimal insertion position of the buffer according to the following procedure
Automatic layer of semiconductor device characterized by dynamic calculation
Out method . (1) a wiring resistance value and a wiring capacitance value of the critical net, an output resistance value of the functional cell and the buffer, an input capacitance value of the functional cell and the buffer,
The delay amount T of the critical net is calculated using the actual circuit variation constant value including the internal delay amount inherent to the buffer as a parameter. (2) The wiring length L _i (i
Is to equality a differential coefficient by inserting the number of buffers) to 0, determining the insertion position of the buffer corresponding to the minimum value of the delay amount T as the wiring length L _i from the functional cells. (3) seek delay amount T _min of the critical nets corresponding to the line length L _i, the delay amount of the critical nets when no values for the T _min Insert the buffer T _a
Against values and comparison, when T _a -T _min> 0, placing a buffer at the position of the L _i.