JP2738357B2 - Test pattern compression apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern compression apparatus and a compression method thereof, and more particularly to a test pattern compression apparatus and a compression method used for increasing a test pattern compression ratio for an LSI tester for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, in a test pattern compression apparatus of this kind, a test pattern used for an LSI tester is:
"0" or "1" and the pattern (PATTERN) section showing the value itself of the pattern in either, or each bit of the test pattern that is the input state "IO = 1", or outputs state "IO = 0 ”, the input / output (I
O) part and a mask (MASK) part indicating whether “MASK = 1” for comparing and collating each bit of the test result by the LSI tester or “MASK = 0” for not comparing and collating the test result. It is constituted by three attributes including, compared to these three attribute values, the pattern, the one before the pattern and the pattern value one bit of the current pattern at the input in order from the first pattern It is usual that the pattern is collated and the corresponding pattern is compressed by changing to the repetitive description of the previous pattern when all the bits match up to the maximum.

FIG. 8 is a block diagram showing a configuration of an embodiment of a conventional test pattern compression apparatus. As shown in FIG. 8, this conventional example employs a repetitive pattern search means 81.
And a pattern looping means 82. The test pattern 801 includes a repetitive pattern searching means 81.
When the repetitive pattern is searched by the repetitive pattern search means 81, the input of the repetitive pattern 802 is received, and the repetitive pattern 802 is looped by the pattern looping means 82. Thus, a compressed test pattern 803 is generated and output.

FIG. 9 shows a conventional test pattern compression apparatus.
Showing the processing procedure of the test pattern compression method in a computer
It is a chart. First, in step 91, the current
patternEnterPerform initializationOf the first pattern number
"P = 1", and in step 92, the current pattern
Is not less than the last pattern number (P ≦ PEND
? ), And in the case of YES, step 93
And initializes bit by bitBit number"I
= 1 ”. Then, in step 94,
Is smaller than the maximum bit number (i ≦ ma
xbit? ), And in the case of YES, step 95
ToTest patternpatternDepartment, Input and outputDepartmentand
maskDepartmentBut all the previousfor testSame bit of pattern
It is determined whether or not the value matches the value of K. In the case of YES,
Moves to step 96 and sets the current bit to the next bit.
To “i = i + 1”, and then
Bit is the largest bitnumberStep to determine whether
Return to step 94. Thereafter, steps 94, 95 and 96
Is repeatedly executed, and in step 94,
If the current bit exceeds the last bit, the pattern
To ensure that all bits match.
At step 97, test patterns are grouped,
In step 98, the pattern is updated to the next pattern and "P
= P + 1 ", and the current pattern is equal to or less than the final pattern.
The process returns to the step 92 for determining whether or not it is possible. Also,
In step 95, the pattern unit, the input / output unit and the mask unit
Do not match the value of the same bit K of the immediately preceding pattern.
In this case, the process proceeds to step 98 and the next
Updates the pattern to “P = P + 1” and sets the current pattern
Is the final patternnumberStep of determining whether or not
Return to 92. In this way, the steps from step 92 are performed.
The procedure of step 98 is repeated, and
If the current pattern exceeds the last pattern number,
All the procedures of the test pattern compression processing are completed.

FIG. 10A is a diagram showing an example of a test pattern to be compressed before application of the pattern compression according to the conventional example, and FIG. 10B is a diagram after the pattern compression processing according to the conventional example is applied. This shows the test pattern. In FIG. 10A, in the fifth pattern and the sixth pattern, the pattern (PATTERN) section, the input / output (IO) section, and the mask (MASK) section all match in all the bits. As shown in FIG. 10B, the sixth pattern is changed to a loop description that repeats the fifth pattern twice. As a result, the six patterns before compression in FIG. 10A are corrected to five patterns in FIG. 10B after compression, and the total number of patterns is reduced by one pattern.

[0006]

[SUMMARY OF THE INVENTION] Oite the conventional test pattern compression equipment described above, pattern portions, three types of data, including the input and output attribute section Contact <br/> preliminary mask attribute portion becomes the same A test pattern is looped as a description of a repetitive pattern, and pattern compression is performed. Therefore, in the case of this compression test pattern, the input / output attribute value is output,
The mask attribute value is regulated in the form of “mask (do not collate) ”, and the pattern value is not compared, so that the pattern value is different, so that two types of data will be stored. In some models, the number of test patterns that can be handled exceeds the maximum value, and this makes it impossible to perform tests using the tester.

[0007]

The test pattern compression apparatus according to the present invention has a configuration in which a test pattern used for a semiconductor integrated circuit tester is provided in a pattern portion of the test pattern itself .
An input / output attribute section indicating an input / output state corresponding to each bit of the pattern section, and an input / output attribute section corresponding to each bit of the pattern section.
A mask attribute part indicating whether or not the test results of
A test pattern which is formed as a pressurizing to 1 data a target pattern compression, the output attribute value of each bit of the test pattern is output, and the mask attribute values irradiation thereof
An attribute value check means for checking whether or not matching the criteria consisting Otherwise if the value of the bit of the condition <br/> matching test pattern of this attribute value check means, uniformly 0 The
A pattern value changing means for changing to 1, the modified test pattern in this pattern value changing means, the
Loop before and after the patterns of the test pattern is a repeating pattern searching means for searching for the presence of repetitive patterns by comparing and collating whether or not the match over all bits, a repetition pattern detected in this repeating pattern searching means (L
And wherein the obtaining at least Bei the pattern loop means for changing the description of the repeated pattern to OOP) of.

The test pattern compression method according to the first aspect of the present invention is characterized in that a test pattern used for a semiconductor integrated circuit tester is provided in a pattern portion of the test pattern itself.
An input / output attribute section indicating the input / output state corresponding to each bit of the pattern section and a mask attribute section indicating whether or not to compare the test result corresponding to each bit of the pattern section. The test pattern formed as data is subjected to pattern compression, and the current test pattern that is the input test pattern
The input / output attribute value of each bit of the
Mask attribute value is a masking pattern that does not match the result
A first step determines conditions, the first step
In a second <br/> step of changing field <br/> If this current pattern is determined to be in the condition, the pattern value of the pattern to 0 or 1, is changed in this second step A third step of determining whether all the bits of the current pattern are the same as the values of the same bit of the previous caret pattern , and in the third step , the current pattern is determined. All of
Bit, when matching the total bits of the previous Karetopatan as pattern repeat the current pattern, this
In the description of the repetition pattern that loops the repetition pattern of
And a fourth step of changing, and executes repeatedly the steps from the beginning of the test pattern to the end
After that, the test pattern compression processing is terminated .
You .

In the fourth step of the test pattern compression method according to the present invention, the repetition once looped
The current pattern including the description of the
If it is determined that there is a pattern, loop processing is performed again.
It may have a fifth step <br/> flop for multiplexing loop processing to pattern compression Te.

Further, according to the test pattern compression method of the second invention, the test pattern used in a tester for a semiconductor integrated circuit is provided in a pattern portion of the test pattern itself.
An input / output attribute portion indicating an input / output state corresponding to each bit of the test pattern, and a test result corresponding to each bit of the pattern portion.
The adds the mask attribute section indicating whether to match 1 a test pattern which is formed as data intended <br/> the pattern compression, enter a plurality of test patterns to be searched as the current pattern groove Of this current pattern groove
The input / output attribute value of each bit is the output side, and the
Article is a pattern to mask click attribute value does not match the results
A first step of determining a case , and the first step
It is determined that the current pattern groove is in the above condition.
If there boss, and a second step of changing the pattern value of the pattern to 0 or 1, all bits of the second <br/> current pattern grooves that have changed in step, all the previous one Karetopatan A third step of determining whether or not the value matches the value of the same bit in the groove; and the third step
Then, when all the bits of the current pattern groove match all the bits of the previous caret pattern groove,
The current pattern groove is a repetitive pattern groove, and the repetitive pattern groove is looped .
And and a fourth step of changing the description of the pattern, this
After repeating these steps from the beginning to the end of the current pattern groove , the test pattern compression processing is terminated.

In the fourth step of the test pattern compression method according to the present invention, the repetition once looped
To the current pattern groove containing the pattern description.
If it is determined that there is a repeated pattern in
Fifth, which performs multi-loop processing by performing compression processing and pattern compression
It may have steps.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a test pattern compression apparatus 1 according to the present invention.
FIG. 2 is a block diagram illustrating a configuration of the embodiment. As shown in FIG. 1, in the present embodiment, an attribute value checking unit 11 includes:
Pattern value changing means 12 and repetitive pattern search means 13
And a pattern looping means 14. Test pattern 101 to be compressed, the configuration described in the conventional example
A test pattern similar to that described above is used.
Corresponds to 1, the attribute value check unit 11, checking for output attribute portion and the mask attribute portion <br/> of the test pattern 101 is performed, input and output attribute value is output "IO
= 0, and the master pattern is in a state of “MASK = 0” in which test results are not compared and collated, the output “IO
Despite = 0 is "not performed test results comparing, pattern unit for storing pattern value itself is not required. Test pattern 102 of the check result, in the pattern-value change means 12, the pattern value The changed pattern 103 is subjected to a search for the presence / absence of a corresponding repeated pattern in the repeated pattern search means 13,
When a repetition pattern is found, the repetition pattern becomes 104
Are looped by the pattern looping means 14 and output as a pattern-compressed test pattern 105.

[0014] Figure 2 is in the test pattern compression device is a flowchart illustrating a processing procedure of the first embodiment of the test pattern compression method. First, in step 21, initialization for inputting a current pattern is performed, and the first pattern is input.
In step 22, it is determined whether the current pattern is equal to or less than the final pattern (P ≦ PE).
ND? ) Is determined, and in the case of YES, the process proceeds to step 23 where initialization is performed for each bit and the bit number
Is set to “i = 1”. In step 24 following step 23, it is determined whether the current bit is equal to or smaller than the maximum bit (i ≦ maxbit?), And YES
If the input / output value is "IO"
= 0 and the mask value is “MASK = 0”
Then, it is determined whether or not the pattern is to be masked without comparing the result. If YES in step 25, it is not necessary to compare the result as a pattern at the time of output, so the process proceeds to step 26 to change the pattern value to "0". Also, in the case of NO in step 25, the process directly passes step 26 and directly proceeds to step 27.
Next, at step 27, it is determined whether or not the pattern value, the input / output value, and the mask value are all equal to the value of the same bit K of the immediately preceding pattern. Then, the current bit is updated to the next bit to make "i = i + 1", and thereafter, it is determined whether or not the current bit is equal to or smaller than the maximum bit (step 24).
Return to Thereafter, the processing procedure of steps 24, 25, 26, 27 and 28 is repeatedly executed, and if the current bit exceeds the last bit in step 24, it is confirmed that all bits match as a pattern. Next, in step 29, the test pattern loop (LO
OP) , and in step 30, the pattern is updated to the next pattern to make “P = P + 1”, and the process returns to step 22 in which it is determined whether the current pattern is equal to or less than the final pattern. In step 27, the pattern value, the input / output value, and the mask value are all the same bit K of the immediately preceding pattern.
Even if the value does not coincide with the value of, the pattern is updated to the next pattern in step 30, "P = P + 1", and the process returns to step 22 in which it is determined whether the current pattern is equal to or less than the final pattern. In this way, the processing procedure from step 22 to step 30 is repeated, and in step 22, when the current pattern exceeds the final pattern number , the processing procedure for the test pattern compression is all ended.

FIG. 3A is a diagram showing an example of a test pattern to be compressed before applying the pattern compression according to the present embodiment, and FIG. 3B is a diagram showing a process in the middle of the pattern compression processing according to the present embodiment. 3 shows the test pattern in FIG.
(C) shows the test pattern after the pattern compression processing. In FIG. 3A, the sixth and eighth bits of the first pattern, and the seventh and eighth bits of the third pattern have input / output (IO) values = 0 (output) and a mask (M
Since the (ASK) value = 0 (mask), as shown in FIG. 3B, the pattern (PATTERN)
Change the value from 1 to 0. As a result of this change, the first to fourth patterns have the same pattern (PATTERN) value, input / output (IO) value, and mask (MASK) value in all the bits, so that as shown in FIG. Then, the second to fourth patterns are changed to a loop (LOOP) description in which the first pattern is repeated four times. As a result, the six patterns before compression in FIG. 3A are corrected to two patterns in FIG. 3C after compression, and the total number of patterns is reduced by four patterns.

FIG. 4 is a flowchart showing a processing procedure of a test pattern compression method according to a second embodiment in the test pattern compression apparatus of the present invention. The test pattern compression method according to the present embodiment is different from the test pattern compression method according to the first embodiment in that the repetitive pattern to be searched is two or more patterns in contrast to the case where the repetitive pattern is searched one by one. There is a difference in that a plurality of patterns can be specified at a time. First, in step 41, a search pattern width (the number of patterns to be searched) is specified, and W = wdef. Next, in step 42, the current pattern groove is initialized, and PG = 1
× W, it is determined in step 43 whether or not the current pattern group does not exceed the final pattern. If YES, the process proceeds to step 44 in which attribute values are determined for all bits by attribute value determination. The pattern value is changed, and it is determined whether or not the current pattern group matches the previous current pattern group, and a loop (LOOP) is performed. Then, in step 45, the current pattern group is updated, and PG = PG + 1 × Then, the process returns to step 43 where it is determined whether the current pattern group does not exceed the final pattern. Thereafter, the processing procedure from step 43 to step 45 is repeated and executed.
In this case, when it is determined that the current pattern group has exceeded the final pattern, the test pattern compression processing is terminated.

FIG. 5 shows a change in the pattern value and a determination as to whether or not it matches the immediately preceding current pattern group by attribute value determination for all bits in step 44 in the test pattern compression method shown in FIG. And determine the loop (L
9 is a flowchart illustrating details of a processing procedure for performing OOP). First, in step 51, the current bit I
And I = 1. Then, step 52
, Whether the bit is less than or equal to the maximum bit (i ≦
maxbit? ), If YES, the input / output value is “output” and MA
It is determined whether the SK value is a “mask” pattern. If YES in step 53, the pattern (PATTERN) value becomes unnecessary for the same reason as in the case of the pattern compression method of the first embodiment, and in this example, the pattern (PATTERN) is used in step 54.
N) Change the value to “0”. If NO in step 53, step 54 is skipped and step 5
Move to 5. Next, in step 55, each video
It is determined whether the pattern (PATTERN) value, the input / output value, and the mask (MASK) value are all the same as the same bit I of the immediately preceding pattern group. Update to the next bit, i = i
The value is set to +1 and the process returns to step 52 for determining whether or not the current bit is smaller than the maximum bit. Step 55
If the answer is NO in step S5, the values do not match, and the process proceeds to step 45 in FIG. As described above, the processing procedure from step 52 to step 56 is repeatedly executed, and if the culet bit exceeds the maximum bit in step 52, all bits match the previous pattern group. At 57, a loop (LOOP) process is performed, and the routine goes to step 45 of FIG.

[0018] FIG. 6 (a) before the pattern compression applied by the test pattern compression method of the second embodiment,
FIG. 6 is a diagram illustrating an example of a test pattern to be compressed;
FIG. 6B shows a test pattern after the pattern (PATTERN) portion is changed by the pattern compression processing according to the present embodiment, and FIG. 6C shows the test pattern after the pattern compression processing with the search pattern width set to 4. Shows the test pattern. In FIG. 6A, a first pattern, a fourth pattern,
In the sixth and eighth bits of the fifth and seventh patterns, the input / output (IO) value = 0 (output) and the mask (MAS
K) Since the value = 0 (masking), FIG.
As shown in (b), the pattern (PATTERN) values of the sixth and eighth bits of the first, fourth, fifth, and seventh patterns are changed from 1 to 0. With this change, the first pattern, the second pattern, the third pattern
A pattern and a fourth pattern, a fifth pattern, a sixth pattern,
The seventh pattern and the eighth pattern are each a pattern (PA
TTERN) value, input / output (IO) value and mask (MA
Since the SK) values are all in the same state, FIG.
As shown in, the first to fourth patterns are:
The description is changed to a LOOP description that repeats twice from the repetition start pattern LOOP_ST to the repetition end pattern LOOP_EN. Thus, eight patterns before compression become four patterns after compression, and the total number of patterns is reduced by four patterns.

As described above, in the conventional test pattern compression method and the first and second embodiments of the present invention, in the test pattern compression method, a loop (LOOP) process is performed. ing. As described above, the test pattern once subjected to the loop (LOOP) processing is again subjected to the loop (LOOP) processing to compress the pattern.
The OP) processing is generally called a multiple loop (LOOP) processing.

FIG. 7A shows this multiple loop (LOO).
FIG. 14 is a diagram showing an example of a test pattern to be compressed before the pattern compression processing is applied by the test pattern compression method according to the third embodiment of the present invention applied in P) processing;
FIG. 7B shows a test pattern after a pattern (PATTERN) value is changed by the pattern compression processing according to the present embodiment, and FIG. 7C shows a loop (LOOP) processing once performed. FIG. 7D shows a test pattern after the multi-loop (LOO).
P) shows the test pattern after the processing.

In FIG. 7A, the first pattern, the third pattern
6th and 8th bits of the pattern, fifth and seventh patterns
The bit has an input / output (IO) value = 0 (output) and a mask (MASK) value = 0 (masks).
As shown in FIG. 7B, the pattern (PATTERN) values of the sixth and eighth bits of the first, third, fifth, and seventh patterns are changed from 1 to 0. With this change, the first pattern and the second pattern,
The third pattern and the fourth pattern, the fifth pattern and the sixth pattern, and the seventh pattern and the eighth pattern are patterns (PATTE), respectively.
RN) value, input / output (IO) value and mask (MASK)
Since the values all match, as shown in FIG. 7C, the first pattern, the third pattern, the fifth pattern, and the seventh pattern are changed to LOOP descriptions that are repeated twice each. Next, by processing the search repetition width to W = 2 once for the LOOPed pattern,
The first pattern and the second pattern, and the third pattern and the fourth pattern
In the pattern, each pattern (PATTERN)
Value, input / output (IO) value and mask (MASK) value
As shown in FIG. 7 (d), since all the states match, the LO from the first pattern to the second pattern is repeated twice.
Change to OP description. As a result, eight patterns before the test pattern compression become two patterns after the pattern compression, and the total number of patterns is reduced by six patterns.

[0022]

As described above, according to the present invention, in the test pattern compression apparatus and method of the tester for a semiconductor integrated circuit, the pattern unit, input-output attribute portion and the mask attribute
Corresponding to the test pattern to form one data by part, input attribute values for each bit of the test pattern is "output", and the mask attribute value is "masked"
Means for determining whether or not there is a condition (not collated); means for uniformly changing a pattern that matches the condition to "0" or "1"; Means for comparing whether or not the pattern is repeated, and means for changing to a description of a repeated pattern for making the pattern LOOP when the pattern matches, thereby improving the compression ratio of the test pattern. It is possible to do. In particular, when the mask pattern is a test pattern exceeding 60% of the entire pattern, the compression ratio of the pattern is about 66%, and the conventional pattern compression ratio is 1%.
It is improved by about 50% compared to 5%. As described above, by improving the compression ratio of the test pattern, it is possible to eliminate a situation in which the test cannot be performed due to exceeding the maximum value of the test pattern depending on the type of the tester.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a flowchart illustrating a test pattern compression method according to a first embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a process of compressing a test pattern according to the first embodiment of the test pattern compression method.

FIG. 4 is a diagram showing a flowchart of a test pattern compression method according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a flowchart of a partial processing procedure in a second embodiment of the test pattern compression method.

FIG. 6 is a diagram showing an example of a process of compressing a test pattern according to a second embodiment of the test pattern compression method.

FIG. 7 is a diagram illustrating an example of a process of compressing a test pattern according to a third embodiment of the test pattern compression method.

FIG. 8 is a block diagram showing a conventional embodiment.

FIG. 9 is a diagram showing a flowchart of a test pattern compression method according to a conventional embodiment.

FIG. 10 is a diagram showing an example of a process of compressing a test pattern by a conventional test pattern compression method.

[Explanation of symbols]

11 Attribute value checking means 12 Pattern value changing means 13, 81 Repetitive pattern searching means 14, 82 Pattern looping means 21-30, 41-45, 51-57, 91-98
Processing steps

Claims (5)

(57) [Claims] As claimed in claim 1] test patterns used in a tester for semiconductor integrated circuit, the pattern of the test pattern itself, this
An input / output attribute portion indicating an input / output state corresponding to each bit of the pattern portion, and an input / output attribute portion corresponding to each bit of the pattern portion.
Added mask attribute part indicating whether to compare test results
To the subject of the test pattern formed pattern compressed as one data, and input and output attribute value is output for each bit of the test pattern, and verification that mask attribute value
An attribute value check means for checking whether matching was not the following condition, the value of the bit in the attribute value check unit test pattern <br/> emissions that matches the conditions, uniform 0 or 1 a pattern value changing means for changing the, for this pattern value modified test pattern <br/> down in changing means, comparison and verification before and after patterns of the test pattern is, whether or not the match over all bits at least obtain Bei repeating pattern searching means for searching for the presence of repetitive patterns, the pattern loop means for changing the detected repeated pattern in the repeated pattern searching means to describe the repeating pattern to loop (lOOP) by being A test pattern compression apparatus characterized by the above. 2. A test pattern used in a tester for a semiconductor integrated circuit, which is provided in a pattern portion of the test pattern itself.
An input / output attribute section indicating the input / output state corresponding to each bit of the pattern section and a mask attribute section indicating whether or not to compare the test result corresponding to each bit of the pattern section are added.
Then, the test pattern formed as one data is subjected to pattern compression, and the input / output attribute value of each bit of the input current pattern is the output side.
One of the first step determines conditions mask attribute value is pattern to mask not match the result that, in the first step, the current pattern is the condition
If it is determined that the, the pattern value of the pattern 0 or
1 and the second pattern of the current pattern changed in the second step.
Tsu metropolitan government, a third step for judging whether or not to match the value of the same bit of all the previous Karetopatan, the first
In third step, all bits of the current pattern is 1
When matching the total bit One previous Karetopatan as pattern repeat the current pattern, repetition pattern of this
The change of the emission in the description of the repeated pattern to be looped 4
Of and a step, when these steps were carried out repeatedly from the beginning of the test pattern to the end, the test pattern compression method which is characterized in that the end of the test pattern compression processing. 3. In addition to <br/> put away step in the test pattern compression method of claim 2, wherein, in the fourth step, one
Containing a description of a repetitive pattern that has been looped
If the top pattern is determined to have more repeated patterns
A test pattern compression method comprising a fifth step of performing loop processing again, pattern compression, and multiple loop processing. 4. A test pattern used for a tester for a semiconductor integrated circuit, which is provided in a pattern portion of the test pattern itself.
An input / output attribute portion indicating an input / output state corresponding to each bit of the pattern portion, and an input / output attribute portion corresponding to each bit of the pattern portion.
Added mask attribute part indicating whether to compare test results
To the test pattern which is formed as a data subject to pattern compression, enter a plurality of test patterns to be searched as Cale <br/> cement pattern grooves, the current pattern
Whether the input / output attribute value of each bit of the groove is the output side,
A first step of determining a condition in which the mask attribute value is a masking pattern that does not match the result; and in the first step , the current pattern groove
If it is determined that the above condition is satisfied, a second step of changing the pattern value of the pattern to 0 or 1 and all bits of the current pattern groove changed in the second step are all the current A third step of determining whether or not the value matches the value of the same bit of the pattern groove, and in the third step , the current pattern groove of the current pattern groove is determined.
If all the bits match all the bits of the previous kareto pattern groove, the current pattern groove is repeated.
As to the pattern groove, and a fourth scan <br/> step of changing the repetition pattern grooves on the description of the repeated pattern to be looped, and executes repeatedly the steps from the beginning of the current pattern groove to the end Thereafter, the test pattern compression method is terminated. 5. In addition to the steps in the test pattern compression method of claim 4, wherein, in the fourth step, one
Containing a description of a repetitive pattern that has been looped
It is determined that there are more repeated patterns in the top pattern groove
A test pattern compression method characterized by comprising a fifth step of performing loop processing, pattern compression, and multiple loop processing again when loop processing is performed.