JP2738134B2 - Electronic balance - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an electronic balance.

<Prior Art> In general, in electronic balances, a load detection output from a load detection unit is guided to an A / D converter, digitized at a predetermined constant cycle, and these are averaged by a moving average, digital filter processing, or the like, and weighed. Determine the display value.

<Problems to be Solved by the Invention> By the way, if the A / D conversion is performed at the sampling period T ₀ , no matter what means is taken as the averaging process, f ₀ =
It is not possible to reduce noise of frequency components that are integral multiples of 1 / T ₀ Hz.

Therefore, when there is disturbance such as vibration of the frequency component in the installation environment of the balance, an error or fluctuation corresponding to the measured display value occurs.

An object of the present invention is to eliminate such a problem.

<Means for Solving the Problems> A configuration for achieving the above object will be described with reference to a basic conceptual diagram shown in FIG. 1. According to the present invention, the output of the load detection unit a is at least two different from each other. Seed period T ₁ , T ₂
And a data sampling means b for digitizing and sampling at a different cycle, and averaging the data groups sampled at mutually different periods by the arithmetic unit c to determine the weighing display value. Can be

<Operation> For example, when data is alternately sampled at two sampling periods of T ₁ = T ₀ , T ₂ > T ₀ , the output of the load detection unit is sampled at points having different phases. By averaging such a data group, it is possible to reduce the influence of frequency components that are integral multiples of f ₀ = 1 / T ₀ Hz from the averaging result.

<Embodiment> FIG. 2 is a block diagram showing a configuration of an embodiment of the present invention.

The load detection unit 1 outputs an analog signal corresponding to the load on the plate 1a, and the output is guided to an AD converter 2 and digitized. The digital output of the A / D converter 2 is taken into the control unit 3.

The control unit 3 mainly includes a microcomputer having a CPU 31, a ROM 32, and a RAM 33.
A timing circuit 34 for determining the timing of digitization of the converter 2 is provided. This timing circuit 34
Has a function of supplying a start signal to the A / D converter 2 according to a command from the CPU 31 and transmitting a completion signal from the A / D converter 2 to the CPU 31. Also, a display 4 for displaying the weighed value is connected to the control unit 3.

In the RAM 33, an area for storing a predetermined number of the latest data taken through the A / D converter 2 based on the program written in the ROM 32 is set. The weighing value to be displayed on the display 4 is determined by averaging the data.

In the above configuration, the data typically constraints on the system, in particular the function of A-D converter 2, there is a limit to the period of the shortest possible sampling data, for example, in a period shorter than T ₀ in this system Cannot be sampled. In the conventional balance, this T ₀ CPU3
1 issues a command for the timing circuit 34 while measuring with, which mean that samples the data at a predetermined period T _0.

In this embodiment, the CPU 31 calculates a cycle T ₁ = T ₀ and a cycle T ₂ = T ₀ (1 + 3/4) in consideration of the delay time, and calculates T ₁
And issues a data sampling command for the timing circuit 24 in an alternating cycle of T _2. As a result, the data taken in at the timing shown in the graph of FIG. 3 is stored in the RAM 33.

Then, the CPU 31 stores the data stored in the RAM 33 as {x _n }
For example, the average value of the latest eight consecutive data Is calculated by

As a result, the phases cancel each other out, and f ₀ = 1 / T ₀
Becomes zero.

The data sampling period is not limited to the above example, and may be, for example, T1 _, T2 _, T2 _, T1 _, T1 _, T2 _, T2 _, T
_The same effect can be obtained by alternately sampling two times _{, 1 and 1 ,} . The sampling period is not limited to two as described above, as for example _{T 4> T 3> T 2} > T 1 = T 0, T 1, T 2, T 3, T 4, T 1, _{T 2, T 3, T 4} , may be ‥‥ sampling.

<Effects of the Invention> As described above, according to the present invention, the load data is sampled at two or more different periods from each other, and the obtained data is subjected to an averaging process to determine the weighing value.
A noise component having a cycle that is an integral multiple of the sampling cycle can be attenuated from a data group for determining a metric value, and a more accurate metric value that is less affected by noise can be obtained.

The concept of the present invention can be applied to other devices using an AD converter other than the balance.

[Brief description of the drawings]

 FIG. 1 is a basic conceptual diagram showing the configuration of the present invention, FIG. 2 is a block diagram showing the configuration of the embodiment of the present invention, and FIG. 1 ... Load detection unit 2 ... A / D converter 3 ... Control unit 31 ... CPU 32 ... ROM 33 ... RAM 34 ... Timing circuit 4 ... Display unit

Claims (1)

(57) [Claims] An output of the load detector is converted into a digital signal at a predetermined cycle, sampled, and a data group is averaged by a calculation unit to obtain a weighing display value. And data sampling means for digitizing the data at at least two different periods and sampling the data. The arithmetic unit is configured to determine the weighing display value by averaging the data groups sampled at the different periods. An electronic balance, characterized in that: