JP2737703B2 - Ultrasonic receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultrasonic receiving apparatus in an ultrasonic diagnostic apparatus, and more particularly, to an ultrasonic receiving apparatus for improving image quality.
Also, the present invention relates to an ultrasonic receiving apparatus provided with a low-cost digital receiving beamformer.

[0002]

2. Description of the Related Art Conventionally, an ultrasonic diagnostic apparatus has been used which transmits an ultrasonic wave into a human body, receives an ultrasonic wave reflected by a tissue in the human body and returns, and diagnoses a disease such as an internal organ of the human body. In this ultrasonic diagnostic apparatus, a so-called dynamic focus technique has been conventionally used.

FIG. 16 is a schematic diagram showing a relationship between a group of transducers for transmitting and receiving ultrasonic waves and a reflection point of the ultrasound in a subject such as a human body, and FIG. 17 shows a relationship between the group of transducers and a delay time. It is a schematic diagram. In these figures, the horizontal direction is the number n (for example, 1) of the vibrator group 1 abutting on the surface of the subject.
28 (1), 1 (2),..., 1 (n), and the vertical axis in FIG. 16 indicates the direction in which the ultrasonic wave transmitted into the subject is reflected. Depth d in the specimen, FIG.
Represents the delay time D in a delay circuit (described later) connected to each of the vibrators 1 (1), 1 (2),..., 1 (n). Here, as shown in FIG. 16, each point P1, P2, P3 on a perpendicular extending from the center O of the vibrator group 1
It is assumed that the ultrasonic wave is reflected by

When an ultrasonic wave is reflected at a point P1 having a depth d1 shown in FIG. 16, the point P1 and each of the vibrators 1 (1), 1
The distance between (2),..., 1 (n) is longer as the vibrator is farther from the center O of the vibrator group 1, so that the ultrasonic wave reflected at the point P1 causes the vibrators 1 (1), When reaching 1 (n), assuming a uniform medium, this ultrasonic wave reaches each point on the arc A1 centered on the point P1. For this reason, when obtaining information of the point P1 based on the received ultrasonic waves, each of the transducers 1 (1), 1 (2),.
Each signal received in (n) needs to be added after being delayed as shown by D1 in FIG. Similarly depth d
2 and d3, when the ultrasonic waves are reflected at the points P2 and P3, the reflected ultrasonic waves are applied to the vibrators 1 (1) and 1 at both ends.
At the point when (n) is reached, the arc A in a uniform medium
2 and A3, the respective signals received by the transducers 1 (1), 1 (2),..., 1 (n) are represented by D2 and D3 in FIG. And is added after being delayed. Since the ultrasonic wave reflected at a deeper position in the subject arrives at each of the transducers 1 (1), 1 (2),..., 1 (n) with a delay, each of the transducers 1 (1) over time. , 1
(2),..., 1 (n), the delay time D of each signal received
Are changed as D1 → D2 → D3, and these signals are added to each other, so that the focal point is set at each point P in the subject.
A dynamic focus that sequentially moves from 1 to P2 to P3 is realized.

FIG. 18 is a diagram showing an example of a circuit block of a conventional ultrasonic diagnostic apparatus in which the dynamic focus is realized by a digital circuit. Clock generation circuit 2
Is a circuit that generates a clock signal CK having a predetermined period T and supplies the clock signal CK to the control circuit 3. Each circuit is controlled by the control circuit 3 so as to operate in synchronization with the clock signal CK.

[0006] Each of the vibrators 1 (1), 1
Each of the transmission drivers 4 (1), 4 (2),..., 4 (n) constituting the transmission driver group 4 is connected to 1 (2),. Each timing pulse is issued from the circuit 3 to each of the transmission drivers 4 (1), 4 (2),..., 4 (n).
(1), 4 (2),..., 4 (n) convert each of these timing pulses into a high-voltage pulse, and
(2),..., 1 (n).
From (1), 1 (2),..., 1 (n), pulsed ultrasonic waves are emitted into the subject (not shown).

Each of the vibrators 1 (1), 1 (2),.
(N) includes A / D (analog / digital) converters 5 (1), 5 (2),... Which constitute the A / D converter group 5.
5 (n) are connected, and each of the vibrators 1 (1), 1
(2),..., 1 (n), the respective analog reception signals SA1, SA2,..., SAn are obtained by the respective A / D converters 5 (1), 5 (2),. , 5 (n)
Are digitally converted into digital received signals SD1, SD2,... Each having d bits (for example, 8 bits).
SDn is generated.

Each of these A / D converters 5 (1), 5
, 5 (n) are connected to the respective delay circuits 6 (1), 6 (2),..., 6 (n) constituting the delay circuit group 6, and each A / D converter 5 (1), 5 (2), ...,
5 (n), each digital reception signal SD1,
, SDn are the corresponding delay circuits 6 (1), 6
(2),..., 6 (n), and each is delayed by a predetermined time in each of the delay circuits 6 (1), 6 (2),. Each delay time in each of the delay circuits 6 (1), 6 (2),..., 6 (n) is controlled by each delay control signal SC1, SC2,. Each of these delay circuits 6 (1), 6 (2),.
(N) each digital reception signal SDD1, S
The DD2,..., SDDn are input to the addition circuit 7 and added to each other, thereby generating a signal SI for image display.

In order to obtain an image display signal SI in the conventional ultrasonic diagnostic apparatus configured as described above, the following control is performed. First, at the time of ultrasonic transmission, for example, FIG.
In order to focus on the point P2 in the subject shown in FIG. 6, the vibrators 1 closer to the center O of the vibrator group 1 have a later timing in accordance with the delay time D indicated by the curve D2 in FIG.
(1), 1 (2),..., 1 (n), the transmitting circuit 4 (1), 4 (4) from the control circuit 3 so that ultrasonic waves are emitted.
Each timing pulse is transmitted toward (2),..., 4 (n).

The transmitted ultrasonic beam is reflected by the acoustic impedance mismatching portion in the subject and returns to the vibrator group 1 again, and this ultrasonic wave is transmitted to each of the vibrators 1 (1), 1
(2),..., 1 (n)
, 5 (n) are converted into digital received signals SD1, SD2,..., SDn, and each of the delay circuits 6 (1), 6 (2),. (N). Each of these delay circuits 6 (1), 6 (2),.
In (n), the focus of reception is the point P1 → P2 → shown in FIG.
The output digital reception signals SDD1 and SDD1 are output after being delayed by a delay amount sequentially changed as shown in FIG. 17 so as to be sequentially changed like P3. .., SDDn are added to each other by the adder circuit 7. Thereby, the above-described dynamic focus is realized, and a high-resolution ultrasonic diagnostic apparatus is realized.

FIG. 19 is an internal block diagram of one delay circuit 6 (1) constituting delay circuit group 6 shown in FIG. Here, the delay circuit 6 (1) is taken as an example, but the same applies to the other delay circuits 6 (2), 6 (3),..., 6 (n). The digital reception signal SD1 composed of d bits (for example, 8 bits) of S0, S1,..., Sd generated by the A / D converter 5 (1) shown in FIG. Is input to the first stage 8 (1) of the shift register 8 having d bits and m stages. This shift register 8
Are driven by the clock signal CK generated by the clock generation circuit 2 shown in FIG. 18, and the digital reception signal SD1 input to the shift register 8 is shifted to the subsequent stage by one stage at each cycle T of the clock signal CK. Is done. Each stage 8 (1), 8 (2),..., 8 of the shift register 8
(M), the d-bit tristate buffers 10 (1),
, 10 (n) are connected, and these tristate buffers 10 (1), 10 (2),.
The output sides of 10 (n) are connected to each other and connected to the adding circuit 7 shown in FIG. Each of these tristate buffers 10 (1), 10 (2),..., 10 (n) is composed of these tristate buffers 10 (1), 10 (2),
.., D consisting of “1” and “0” input to 10 (n)
It has a first mode in which the bit signal pattern is output as it is as a d-bit signal consisting of "1" and "0", and a second mode in which the output side is kept at high impedance. These tristate buffers 10 (1), 10
A decoder 9 is connected to (2),..., 10 (n). The decoder 9 decodes the delay control signal SC1 output from the control circuit 3 shown in FIG.
Tristate buffers 10 (1), 10 (2),
, 10 (n) is switched to the first mode, and all other tristate buffers are switched to the second mode. In this way, the tristate buffers 10 (1), 10 (2),.
10 (n) is a digital reception signal SD delayed by an integral multiple of the period T in accordance with whether to switch to the first mode.
D1 is output from the delay circuit 6 (1),
Is input to Thus, the delay circuit group 6 shown in FIG.
, 6 (1), 6 (2),..., 6
In (n), each of these delay circuits 6 (1), 6
The digital reception signals SD1, SD2,..., SDn input to (2),..., 6 (n) are delayed so that the above-described dynamic focus is realized. Each of the digital reception signals SDD1, SDD2,..., SDDn output from each of the delay circuits 6 (1), 6 (2),.
Are added by the adding circuit 7 as described above, whereby a signal SI corresponding to one scanning line on the monitor screen is output, and the above-described reception processing is repeated while sequentially transmitting ultrasonic beams in different directions. By doing so, 2
A two-dimensional tomographic image is formed.

[0012]

In order to satisfy the demands for cost reduction and high image quality in recent years in an ultrasonic diagnostic apparatus for performing digital processing as described above, a delay time for realizing dynamic focus is required. And the configuration of an adding circuit for adding a large number of digital reception signals to each other.

First, the problem of delay time accuracy will be described. FIG. 20 is a schematic diagram of an ultrasonic reception signal. The ultrasonic waves reflected inside the subject are applied to the transducers 1 (1), 1
(2),..., 1 (n) (see FIG. 18), the analog reception signals SA1, SA2,.
SAn is not a single pulse signal, but a center frequency M having a pulse-shaped envelope as shown in FIG.
5 MHz). In FIG. 20, (a) and (b) denote signals received by the vibrators located at the center and the end of the vibrator group 1, respectively, and the triangles indicate points sampled at time T intervals. And At this time, in the delay circuit group 6 shown in FIG. 18, the signal (a) received by the vibrator located at the center is delayed by several times (here, four times) of the time T, whereby the signal (c) is delayed. Is generated, and the signals of (b) and (c) are added to each other.

Here, in order to add the signals as shown in FIG. 20, it is necessary to make the envelopes EN1 and EN2 of the signals substantially coincide with each other and also to make the phases of the substantially sinusoidal signals SS1 and SS2 coincide. If the addition is performed with the phases shifted from each other, a correct addition result cannot be obtained. It is known experimentally and empirically that the phase accuracy required in this case needs to be within ± 22.5 °. Therefore, each of delay circuits 6 (1) and 6 (1) shown in FIG.
To delay with the above accuracy using (2),..., 6 (n), the A / D converters 5 (1), 5 (2),. / M must be sampled at a time interval of 1/8 or less of the clock signal CK.
Is required to be at least eight times the center frequency M of the signals SS1 and SS2. In recent years, in order to respond to the demand for higher image quality, the frequency of ultrasonic waves used in ultrasonic diagnostic apparatuses is increasing, and for example, 5 MHz.
Ultrasound probes at z, 7.5 MHz have also appeared. In order to realize an ultrasonic diagnostic apparatus using such a probe, the clock signal CK must be 40 MHz each.
A high-frequency signal of z, 60 MHz is required. In addition, since the consultation signal has a dynamic range of at least 40 dB or more depending on the reflectance of each tissue inside the subject, a signal of 8 bits or more is required for each point to obtain a tomographic image. However, such a high-speed and high-resolution A / D converter and a high-speed circuit for delay-adding a digitized received signal are very costly in terms of circuit scale and speed, and are difficult to realize. There is.

In order to solve this problem, the highest frequency of the received signal band (for example, when the center frequency is 5 MHz,
Sampling is performed using a clock signal CK having a repetition frequency of about 7.5 times (7.5 MHz to 10 MHz), and each point in the middle of each sampling point is obtained by interpolating from the signal of each sampling point. A method is also conceivable in which the signal obtained in this way is also regarded as a received signal and delayed and added so that the phase is within the above-mentioned accuracy. But,
If the primary interpolation operation is employed for speeding up the processing, the interpolation accuracy is too low, and if the secondary or higher order interpolation operation is employed, the operation becomes complicated, so that high-speed processing is required and the circuit scale is increased.

As another solution, a clock signal CK having a frequency approximately twice the highest frequency of the band of the received signal is used, and each oscillator 1 (1), 1 (2),. There is a method in which two A / D converters are connected, and sampling is performed by shifting the sampling timings of the two A / D converters by a time corresponding to a phase difference of 90 ° of the center frequency of the received signal. Proposed (Tokuhei 1
-31151). However, if this method is adopted, two systems of an A / D converter, a delay circuit, and an adder are required for each oscillator, and further, an arithmetic circuit such as a multiplier and a square rooter is required, and the circuit scale is more than doubled. Will be lost.

The present invention has been made in view of the above circumstances, and has as its object to provide an ultrasonic receiving apparatus having a clock signal having an appropriate repetition frequency and digital delay means for performing a delay with sufficient accuracy with a circuit configuration of an appropriate scale. The first purpose. Further, regarding the circuit configuration of the adder circuit, in response to the demand for higher image quality in recent years, in addition to adopting high-frequency ultrasonic waves, the diameter of the ultrasonic probe has been increased, and the number of transducers has been reduced to, for example, 12
Eight pieces are also becoming popular, in which case, for example, 128
Attempting to configure a logic circuit that adds digital received signals at a time involves a complicated circuit configuration, which is problematic in terms of circuit size and computation time.

It is a second object of the present invention to solve this problem and to provide an ultrasonic receiving apparatus provided with digital adding means suitable for increasing the diameter of a probe.

[0019]

The first and second ultrasonic receiving apparatuses according to the present invention include: (1) receiving an ultrasonic wave transmitted into a subject and reflected in the subject to receive each analog signal; (2) a clock generation circuit for generating a clock signal having a predetermined period; (3) converting each analog reception signal obtained by each of the plurality of vibrators into A large number of A / D conversion circuits for A / D converting each predetermined period and outputting each digital reception signal; (4) digital reception corresponding to ultrasonic waves reflected substantially simultaneously at substantially the same position in the subject A large number of variable delay means for delaying the digital reception signal so that the signals are output substantially simultaneously; and (5) an addition means for adding the digital reception signals output from the multiple delay means to each other. The present invention relates to an ultrasonic receiving apparatus provided with:

Here, the first ultrasonic receiving apparatus of the present invention comprises:
In order to achieve the first object of the present invention, each of the multiple delay means of the above (4) includes: (6) each of the delay circuits 6 (1), 6 (1), 6 (6) in the above-described conventional example (see FIG. 18). (2),..., 6 (n), together with a delay circuit for delaying the digital reception signal by an integral multiple of one cycle of the clock signal, and (7) (a) the digital reception signal is divided into two systems. A multiplier for generating a multiplied signal by multiplying one digital reception signal by a first predetermined number; (b) multiplying the other digital reception signal obtained by dividing the digital reception signal into two systems by a second predetermined number A multiplication / delay device for generating a multiplication delay signal by delaying the other digital reception signal by a predetermined time, and (c) multiplying the multiplication signal generated by the multiplier (a) with the (b)・ Delay device And a fine delay circuit configured and generated multiplied delayed signal from the signal adder for adding together.

Here, in the first ultrasonic receiving apparatus of the present invention, the clock generating circuit generates a clock signal having a frequency four times the center frequency of the analog received signal, and the multiplying / delaying device includes It is preferable that the second digital signal is multiplied by a second predetermined number and the other digital signal is delayed by one cycle of the clock signal.

Also, the second ultrasonic reception signal of the present invention is:
In order to achieve the second object of the present invention, the adding means of (5) comprises: (8) an adder and an output signal of the adder which are latched and output to the next-stage adder. A sequential addition circuit in which latch circuits are alternately connected in cascade; and (9) each of the digital reception signals so that the digital reception signals simultaneously output from the plurality of delay means of (4) are added to each other. And a plurality of delay circuits for delaying each of the adders by an integer multiple of one cycle of a clock signal and distributing the delayed signals to the respective adders.

Here, each of the adders includes one or a plurality of individual adders for adding two or three or more digital reception signals. Further, the third to fifth ultrasonic reception signals of the present invention include the above (1), (2),
(10) In addition to the large number of transducers, clock generation circuits, and A / D conversion circuits in (3), (10) digital reception signals corresponding to ultrasonic waves reflected almost simultaneously at substantially the same position in the subject are added to each other. As described above, the present invention relates to an ultrasonic receiving apparatus including delay adding means for delaying digital received signals output from a large number of A / D conversion circuits and adding the digital received signals to each other.

[0024] The third ultrasonic receiving apparatus of the present invention has both the configuration of the first ultrasonic receiving apparatus of the present invention and the configuration of the second ultrasonic receiving apparatus of the present invention. The delay adding means of (10) satisfies both the object and the second object, and (11) the delay circuit of (6) in the first ultrasonic receiving apparatus of the present invention. A large number of delay means provided with both the small delay circuit of (7); and (12) an addition means provided with (8) and (9) in the second ultrasonic receiving apparatus of the present invention. Have.

Further, the fourth ultrasonic receiving apparatus of the present invention
The above-mentioned second object is achieved, and the aforementioned (1)
In the ultrasonic receiving apparatus including the number of vibrators of (2), the clock generation circuit of (2), the A / D conversion circuit of (3), and the delay and addition means of (10), the delay and addition means of (10) includes 13) first and second display correction delay circuits for delaying each input signal by an integer multiple of one cycle of a clock signal; (14) adding output signals of the first and second display correction delay circuits to each other (15) provided for each of the plurality of vibrators of the above (1) except for the vibrators at both ends,
(A) an adder to which a digital reception signal is input;
(B) latching the output signal of the adder, and adding the digital reception signals corresponding to the ultrasonic waves reflected almost simultaneously at the same position in the subject at the next adder of the adder; (C) delaying the output signal of the delay device by two times corresponding to two vibrators adjacent to each vibrator.
A large number of unit addition delay circuits comprising a switch for switching the input to one of the two adders; (16) a plurality of unit addition delay circuits provided corresponding to one of the plurality of vibrators of the above (1); Further, (a) an adder to which a digital reception signal is input, and (b) an output signal of the adder is latched, and the adder at the next stage of the adder is located at substantially the same position in the subject. A delay unit for delaying an integer multiple of one cycle of a clock signal so that digital reception signals corresponding to ultrasonic waves reflected substantially simultaneously are added to each other; and (c) an output signal of the delay unit is connected to the one end. (17) A unit addition delay circuit comprising: an adder corresponding to the vibrator adjacent to the vibrator or a switch for switching the input to one of the first display correction delay circuits. Above many transducers (A) an adder that is provided corresponding to the vibrator at the other end opposite to the vibrator at one end and to which a digital reception signal is input;
(B) latching the output signal of the adder so that the digital receive signal corresponding to the ultrasonic waves reflected substantially simultaneously at substantially the same position in the subject in the adder at the next stage of the adder is (C) an adder or an adder corresponding to a vibrator adjacent to the vibrator at the other end, the delay device delaying the output signal of the delay device by an integer multiple of one cycle of the clock signal so as to be added to each other. A unit addition delay circuit comprising a switch for switching the input to one of the second display correction delay circuits; and (18) the delay addition means when the delay times of the delay units are the same. Each of the digital received signals is delayed by an integer multiple of the clock signal period and distributed to each of the above-mentioned adders so that the digital received signals input simultaneously with each other are added to each other. That has a large number of correction delay circuits provided corresponding to each of the unit addition delay circuit.

A fifth ultrasonic receiving apparatus according to the present invention comprises:
In addition to the components in the fourth ultrasonic receiving apparatus,
The delay addition means of (10) comprises (7) (a), (b),
A minute delay circuit having the configuration of (c) is provided before or after each of the correction delay circuits of (18), thereby achieving both the first and second objects of the present invention. Is done.

[0027]

As a conventional reception dynamic focus technique by analog processing, a delay circuit in which a large number of inductances L and a large number of capacitances C are connected in cascade is provided.
A method is known in which the delay time is made variable by switching where in the delay circuit a received signal is input or where in the delay circuit the received signal is output.
This method has a problem that large noise is generated with the switching. As one method of solving this problem, the received signal is divided into two systems, each of which is amplified with a predetermined gain, and one is delayed with respect to the other, and then both are added to each other to obtain the predetermined gain. Has been proposed (see Japanese Patent Application No. 2-412332 and Japanese Utility Model Publication No. 60-39822). When this method is used, the above-described switching becomes unnecessary, and thus noise accompanying the switching does not occur.However, when dynamic focus is performed over a long area from a shallow point to a deep point in the subject, a substantially sinusoidal waveform is obtained. Although the phases of the received signals SS1 and SS2 (see FIG. 20) can be matched, the envelopes EN1 and EN2 are greatly shifted from each other, and thus a new problem that correct delay addition is not performed occurs.

According to the present invention, the conventional digital delay circuit shown in FIG. 18 cannot provide a fine delay unless the clock signal CK is speeded up. However, the conventional digital delay circuit has a problem of noise such as an analog delay circuit having an inductance L and a capacitance C. The method of changing the phase described in Japanese Utility Model Publication No. Sho 60-39822 and the like can focus on the fact that a subtle delay is possible in a small delay region.
By combining a conventional digital delay circuit as shown in FIG. 8 with a minute delay circuit in which the method of changing the phase is digitized, the problem of delay accuracy in digital processing has been solved.

Here, the method of changing the phase will be described in more detail. FIG. 1 is a schematic diagram of an ultrasonic reception signal for explaining the signal delay method based on the phase change. The signal waveforms of (a), (b), and (c) in this figure are the same as the signal waveforms of (a), (b), and (c) in FIG. 20, and (a), (b) Is the transducer group 1
(See FIG. 18) Signals received by the transducers located at the center and end of FIG. 18, (c) is a signal obtained by delaying the signal of (a) by four times the one cycle T of the clock signal CK. The mark is time T
Represents points sampled at intervals.

Here, the signal (c) obtained by delaying the received signal of (a) by four clocks has an envelope (see FIG. 20) substantially coincident with the received signal of (b), but has a substantially sinusoidal waveform. Are out of phase with (b). Here, the signal (c) can be partially regarded as a sine wave having the center frequency f,
Here, the signal of (c) is set to cosωt (ω = 2πf). This signal is divided into two systems, one is multiplied by A and the other is B
When the two signals are added after being multiplied and delayed by a delay time τ (the time T of one cycle of the clock signal CK or a time that is several times the same), the signal Vout after the addition becomes Vout = Acos (ωt) + Bcos {Ω (t−τ)} (A) By transforming this equation, Vout = Acos (ωt) + B {cos (ωt) cos (ωτ) −sin (ωt) sin (ωτ)} = {A + Bcos (ωτ)｝ cos (ωt) −Bsin (ωτ) sin ( ωt) (B). Here, cos (φ) ≡A + Bcos (ωτ) (C) sin (φ) ≡Bsin (ωτ) (D), Vout = cos (φ) cos (ωt) -sin (Φ) sin (ωt) = cos (ωt−φ) (E), and Vout is a signal obtained by changing the phase of the original signal cosωt by φ. Here, when the delay time is determined so as to satisfy sin (ωτ) ≠ 0 (F), that is, τ ≠ k / 2f (k is an arbitrary integer) (G), the above (C),
From the formula (D), A = cos (φ) −Bcos (ωτ) = cos (φ) −sin (φ) cos (ωτ) / sin (ωτ) = ｛sin (ωτ) cos (φ) −sin (φ) cos (ωτ)｝ / sin (ωτ) = sin (ωτ−φ) / sin (ωτ) (H) B = sin (φ) / sin (ωτ) (I) That is, by substituting the phase φ into the above equations (H) and (I), coefficients A and B are obtained.
By multiplying s (ωt), the original signal cos
(Ωt) and a signal c obtained by delaying this signal by a delay time τ
signal V having an arbitrary phase φ intermediate with os (ωt−τ)
out = cos (ωτ−φ) can be obtained.

When the signal (d) is generated by changing the phase of the signal shown in FIG. 1C based on this principle, the signal (d) becomes a signal having the same phase as the signal (b), The addition produces a correctly added signal (e). Here, the delay time τ may be a multiple of one cycle T of the clock signal CK. However, since the delay for each cycle T is realized by a delay circuit using a conventional shift register or the like, a minute One cycle T is sufficient for the delay time τ in the delay circuit. The clock signal CK needs to be about four times the center frequency of the received signal (at least twice the highest frequency of the band of the received signal) according to the request of the sampling theorem, but need not be a signal of a frequency higher than that. .

The first, third, and fifth ultrasonic receiving apparatuses of the present invention include a delay unit that combines a delay of one cycle T unit of the clock signal CK and a minute delay based on the above principle. Thus, a highly accurate delay can be realized without increasing the speed of the clock signal CK and without significantly increasing the circuit scale. The delay circuit that delays the clock signal CK in units of one cycle T is not limited to the one using the shift register in the above-described conventional example (see FIGS. 18 and 19). May be a delay circuit for controlling the timing of writing and reading of data, and delay circuits having various configurations can be used.

The first ultrasonic receiving apparatus of the present invention aims at a high-accuracy delay, and thus does not refer to the detailed configuration of the adding means. The addition means may have any configuration, for example, by providing the configuration of the addition means in the second ultrasonic reception device of the present invention, by providing the configuration as the third ultrasonic reception device of the present invention However, the present invention is not limited to this. For example, n digital reception signals SDD1, SDD
When adding D2,..., SDDn (see FIG. 18) to each other, at the first timing synchronized with the clock signal CK, the operations of SDD11 = SDD1 + SDD2 SDD12 = SDD3 + SDD4. Then, each is latched, and at the next timing, SDD21 = SDD11 + SDD12 ... SDD2q = SDD1, p-1 '+ SDD1p (q = p
/ 2) is latched by performing the operation of (2), and this is repeated, and a circuit configuration for finally obtaining SDD1 + SDD2 +... + SDDn may be provided, or an adder having any other circuit configuration may be provided.

On the other hand, the second ultrasonic receiving apparatus of the present invention
With the increase in the diameter of the probe, it becomes necessary to add a large number (for example, 128) of digital received signals to each other, and an adding means suitable for adding such a large number of signals is provided. That is, in the second ultrasonic receiving apparatus of the present invention, since the adding means includes the sequential adding circuit of (8) and the many delay circuits of (9), a large number of digital received signals are provided. While the timing is adjusted by the delay circuit, the addition is sequentially performed by the addition circuit. Therefore, even in an ultrasonic receiving apparatus using a large-diameter probe, the addition can be performed extremely efficiently. This addition means
The present invention is excellent in that the fourth ultrasonic receiving apparatus of the present invention including the delay adding means having a smaller circuit scale as a whole can be configured by combining the principle with the delay means by applying the principle.

The second ultrasonic receiving apparatus according to the present invention provides an adding means suitable for increasing the diameter of the probe and capable of being combined with the delay means as described above. Contrary to one ultrasonic receiver, the detailed configuration of the delay means is not mentioned, but the delay means may have any configuration for the purpose of increasing the diameter of the probe, For example, by providing the configuration of the delay unit in the first ultrasonic receiving apparatus of the present invention, may be provided with a configuration as a third ultrasonic receiving apparatus of the present invention,
The present invention is not limited to this. For example, a method of performing the above-described interpolation calculation while allowing a decrease in accuracy or a time-consuming signal processing may be adopted.
A method including two A / D converters for each transducer described in Japanese Patent Publication No. 1-31151 may be adopted.

Further, the third ultrasonic receiving apparatus of the present invention comprises:
It has a configuration in which both the delay means in the first ultrasonic receiving apparatus of the present invention and the adding means in the second ultrasonic receiving apparatus of the present invention are connected, so that the delay accuracy is improved and the probe size is increased. It is a device that is compatible with both the increase in diameter. Further, the fourth ultrasonic receiving apparatus of the present invention provides the first and second display correction delay circuits of (13), (1).
Since it has the addition circuit of 4), the multiple unit addition delay circuits of (15), (16) and (17) and the multiple correction delay circuits of (18), the second ultrasonic reception of the present invention is provided. As with the apparatus, addition suitable for increasing the diameter of the probe can be performed, and addition and delay are organically combined, so that dynamic focus can be realized with a small-scale circuit configuration as a whole.

Further, a fifth ultrasonic receiving apparatus according to the present invention comprises:
The configuration of the fourth ultrasonic receiving apparatus according to the present invention further includes a minute delay circuit in the first ultrasonic receiving apparatus according to the present invention, that is, the configuration of (7), (a), (b), and (c) described above. Since the small delay circuit is provided before or after each of the correction delay circuits in (18), it is suitable for both the delay accuracy and the increase in the diameter of the probe as in the third ultrasonic receiving apparatus of the present invention.
Moreover, the addition and the delay are organically combined similarly to the fourth ultrasonic receiving apparatus of the present invention, and the dynamic focus over a long area is realized with a small-scale circuit configuration as a whole.

[0038]

Embodiments of the present invention will be described below. FIG. 2 is a circuit block diagram of an example of a minute delay circuit provided in the first, third, and fifth ultrasonic receiving devices of the present invention.
3 is a timing chart of the minute delay circuit shown in FIG.

The A / D converter 11 shown in FIG.
An analog reception signal SA obtained by a vibrator (not shown) corresponding to the / D converter 11 and a clock signal CK of a predetermined period T (see FIG. 3) are input, and the rising edge of each pulse of the clock signal CK The analog reception signal SA is sampled to generate a digital reception signal SD. Here, as shown in FIG. 3, the digital reception signal SD obtained by sampling at the rise of each pulse i of the clock signal CK is represented as D (i). The digital reception signal SD is divided into two systems, one of which is input to the multiplier 12 and the other is input to the delay unit 13. This delay unit 1
3, a clock signal CK is also input, the input digital reception signal SD is delayed by one clock (time T) of the clock signal CK, and the delayed digital signal SD 'is output. This digital signal SD ′ is input to the multiplier 14. In this embodiment, the combination of the delay unit 13 and the multiplier 14 is considered as a multiplication / delay unit according to the present invention.

On the other hand, a control signal Sφ representing a phase amount φ to be delayed (see the above equation (E)) is input to memories 15 and 16 from a control circuit (not shown). The memories 15 and 16 store the phase amount φ and the values A and B to be multiplied by the digital reception signals SD and SD ′ input to the multipliers 12 and 14 (see the above-described equations (H) and (I)). ) Is stored in the form of a look-up table.

The memories 15 and 16 output values A and B corresponding to the value of the input control signal Sφ in synchronization with the clock signal CK, and input them to the multipliers 12 and 14, respectively. These multipliers 12 and 14 multiply the input digital reception signals SD and SD 'by A and B to obtain a signal A.
SD, B · SD ′ are output, and these signals A / S
D, B · SD ′ are added to each other by a signal adder 17, whereby a signal SO in which the digital received signal SD is appropriately minutely delayed is generated and input to a latch circuit (not shown).

Here, the relationship between the phase amount φ represented by the control signal Sφ and the coefficients A and B to be multiplied is exemplified. For example, the center frequency f of the received signal is f = 5.0 MHz, and the band of the received signal is f = 5.0 MHz. Is 10 MHz or less, the repetition frequency 1 / T of the clock signal CK is set to four times the center frequency f (about twice the maximum frequency of the band).
If / T = 20 MHz, the delay time is τ = 50 nsec because the delay unit 13 delays by one clock.
Becomes At this time, 2πfτ = ωτ = π / 2 (90 °)
Therefore, from the equations (H) and (I), A = cos (φ) (J) B = sin (φ) (K) Equations (J) and (K) for the above conditions
Is stored in the memories 15 and 16 in advance as a look-up table.

As another example, the center frequency f of the received signal is f = 7.5 Hz, and the highest frequency of the band of the received signal is 1
When the frequency is 0 MHz or less, the repetition frequency 1 / T of the clock signal CK is set to 1 / T = 20M as in the above example.
When set to Hz, ωτ = 3π / 4 (135 °), and from equations (H) and (I), A = 2 ^1/2 sin (3π / 4−φ)... (L) B = 2 ^1/2 sin (Φ)... (M) In this case, look-up tables indicating the correspondence between the phase amounts φ and the coefficients A and B related by the equations (L) and (M) are stored in the memories 15 and 16 in advance. Is done.

As described above, the frequency of the clock signal CK is set to about four times the center frequency f of the received signal or about twice the maximum frequency of the band of the received signal, and the frequency of the clock signal CK and the delay in the delay unit 13 By setting the number of clocks so as to satisfy the condition of the above-described equation (G), a minute delay circuit is realized. Therefore, by combining this minute delay circuit and a delay circuit that delays the clock signal CK in units of the period T, the clock signal CK can be four times the center frequency f of the received signal or the highest band of the received signal. With the frequency being about twice as high as the frequency, a delay with sufficient accuracy can be performed over a long area in the subject.

Note that the delay accuracy required here may be within a phase difference of ± 22.5 ° with respect to the center frequency of the received signal as described above, so that the phase amount φ represented by the control signal Sφ is 45 °. For example, two points of 0 ° and 45 ° may be used in the case where the center frequency f is 5.0 MHz, and three points of 0 °, 45 ° and 90 ° may be used in the case where the center frequency f is 7.5 MHz. The above equation (J), (K) or equation (L),
By providing the memories 15 and 16 for storing the coefficients A and B determined according to (M),
(K) or an arithmetic circuit for performing the operations of the equations (L) and (M) can be used instead.

FIG. 4 is a circuit block diagram of another example of the minute delay circuit. In this figure, the elements corresponding to the respective elements of the minute delay circuit shown in FIG. 2 are given the same numbers and symbols as those shown in FIG. 2 and their explanation is omitted. Also, FIG.
5 is a timing chart of the minute delay circuit shown in FIG.
Comparing the micro-delay circuit shown in FIG. 4 with the micro-delay circuit shown in FIG. 2, the arrangement order of the delay unit 13 and the multiplier 14 is changed, and accordingly, as shown in the timing chart of FIG. Although the timing of B is shifted by one clock, a small delay circuit is realized regardless of which of the delay unit 13 and the multiplier 14 is arranged first.

FIG. 6 is a circuit block diagram showing an example of an adding means provided in the second and third ultrasonic receiving apparatuses according to the present invention.
7 is a timing chart showing a circuit operation of the adding means shown in FIG. In FIG. 7, the numbers given in the figure are:
Each pulse 0, 1, 2,... Of the clock signal CK and each signal sampled at the rise of each of the pulses 0, 1, 2,.

The adding means shown in FIG.
(1), 21 (2),..., 21 (n-1) and a number of latch circuits for latching output signals of the adders 21 (1), 21 (2),. 22 (1), 22
(2),..., 22 (n−2) are connected alternately and continuously, thereby forming an addition circuit 20 sequentially. Also, a number of delay circuits 23 (3, 3
1), 23 (4, 1), 23 (4, 2), ..., 23
(N, 1), 23 (n, 2), ..., 23 (n, n-2)
Is connected. Each of these delay circuits 23 (3,
1), 23 (4, 1), 23 (4, 2), ..., 23
(N, 1), 23 (n, 2), ..., 23 (n, n-2)
Is a delay circuit for delaying each input signal by one period T of the clock signal CK.

In this adding means, the clock signal C
In synchronization with the rise of the pulse 0 of K (see FIG. 7), SDD1 and SDD2 of the digital reception signals SDD1, SDD2, SDD3,... Is the adder 21
(1) are added to each other to generate an addition signal ADD1, and this addition signal ADD1 is supplied to the latch circuit 22.
(1) is input and latched. Also, other digital reception signals SDD3, SDD4,..., SDD
n is a delay circuit 23 (3, 1), 23 (4,
1),..., 23 (n, 1). Next, in synchronization with the rise of pulse 1 of clock signal CK, adder 21
Due to (2), the output signal ADD of the latch circuit 22 (1)
1 'and the digital reception signal SDD3' delayed and output by one clock in the delay circuit 23 (3, 1) are added to each other to generate an addition signal ADD2, and the addition signal ADD2 is added to the latch circuit 22 ( Latched in 2). Along with this, the delay circuits 23 (4, 1),.
23 (n, 1) stored in the digital reception signal S
DD4,..., SDDn are respectively connected to the delay circuits 23 (4,
2),..., 23 (n, 2) are stepped one by one. Since then
By repeating this operation, the digital reception signals SDD1, SDD2,...
An addition signal SI in which the SDDs are added to each other is generated and latched by a latch circuit (not shown).

FIG. 8 is a block diagram showing another example of the adding means.
FIG. 9 is a timing chart showing the circuit operation of the adding means shown in FIG. In the timing chart shown in FIG. 9, the numbers given in the figure denote the respective pulses 0, 1, 2,... Of the clock signal CK and these respective pulses 0, 1, 2,. Represents each signal sampled at the rising edge of.

The adding means shown in FIG.
1 (1), 311 (2),..., 31 (n−1), each of which is formed by combining two of them.
(1), 31 (2),... And the respective latch circuits 32 (1), 3
2 (2)... Are alternately connected in cascade, thereby forming an addition circuit 30 sequentially. In addition, a large number of delay circuits 33 (4, 1), 33 (5,
1),..., 33 (n, 1), 33 (n, 2),.
(N, r-2) are connected. Each of these delay circuits 33 (4,1), 33 (5,1), ..., 33 (n,
1), 33 (n, 2),..., 33 (n, r-2) are delay circuits for delaying each input signal by one cycle T of the clock signal CK, as in the case of FIG.

In this adding means, the clock signal C
In synchronization with the rise of the pulse 0 of K (see FIG. 9), SDD1 and SDD2 of the digital reception signals SDD1, SDD2, SDD3,... 1), an addition signal ADD1 is generated, and the ADD1 and SDD3 are input to the next individual adder 311 (2) to generate an addition signal ADT1, and the ADT1 is input to the latch circuit 32 (1). Latched. In addition, other digital reception signals SDD4, SDD5,.
DDn are delay circuits 33 (4, 1), 33 (5, 5,
1)... 33 (n, 1). Next, in synchronization with the rise of pulse 1 of clock signal CK, individual adder 311
Due to (3), the output signal ADT of the latch circuit 32 (1)
1 'and the digital reception signal SDD4' delayed and output by one clock in the delay circuit 33 (4, 1) are added to each other to generate an addition signal ADD2.
DD2 and the digital reception signal SDD5 'delayed by one clock and output by the delay circuit 33 (5, 1) are added to each other to generate an addition signal ADT2. The ADT2 is supplied to the latch circuit 32 (2). Input and latched. At the same time, each delay circuit 33 (6, 1),
, 33 (n, 1) stored in the digital reception signal S
DD6,..., SDDn are delay circuits 33 (6, 6,
2),..., 33 (n, 2), one by one. Thereafter, by repeating this operation, the digital reception signals SDD1, SDD2,.
DDn are added to each other to generate an addition signal SI, which is input to a latch circuit (not shown).

As described above, the individual adders 311 (1), 311
, 311 (n-1) are fast,
If the operation can be repeated a plurality of times (two times in the example shown in FIG. 8) within one cycle T of the clock signal CK, a plurality of (two in the example shown in FIG. 8) individual adders are connected in cascade. After that, by latching once,
Compared to the case of latching every addition, the number of latch circuits and delay circuits can be reduced, and addition can be performed at high speed.

In the examples shown in FIGS. 6 and 8, each adder (each individual adder) adds two digital reception signals. For example, an adder adds three digital reception signals at once. Needless to say, an (individual adder) may be provided. As shown in FIGS. 6 and 8, a sequential adder circuit in which an adder and a latch circuit are connected in cascade, and a number of adjusters for timing adjustment so that digital reception signals simultaneously input to the adder are added to each other. And sequentially adding the delay circuits, it is possible to cope with an increase in the diameter of the probe and to perform the addition efficiently.

FIG. 10 is a circuit block diagram showing an ultrasonic diagnostic apparatus having one embodiment of the third ultrasonic receiving apparatus according to the present invention. In this figure, the same components as those of the conventional ultrasonic diagnostic apparatus shown in FIG.
Are given the same numbers and symbols as those given in, and the description is omitted. In this ultrasonic receiving apparatus, the delay means 61 (1), 61 (2),... 61 () correspond to a large number of transducers 1 (1), 1 (2),. n)
Is provided. These delay means correspond to the minute delay circuits 611 (1), 611 shown in FIG. 2 or FIG.
, 611 (n) and the delay circuits 6 (1), 6 (2),... That delay the clock signal CK by one cycle T in the conventional ultrasonic diagnostic apparatus shown in FIG. 6
(N), which requires that the envelopes of the received signals be substantially coincident with each other and that the phase difference be within ± 22.5 degrees so that dynamic focus can be performed over a long area in the subject. 61, delay means 61 (1), 61 (2),...
(N) is realized. These delay means 61 (1), 6
1 (2),..., 61 (n), and digital reception signals SDD1, SDD2,.
The SDDn is input to the adding means 71. This adding means 71 has the configuration shown in FIG. 6 or FIG. 8, and thereby the vibrators 1 (1), 1 (2),.
Even if the number of (n) is as large as 128, for example, addition is performed very efficiently.

FIG. 11 is a circuit block diagram of an embodiment of the fifth ultrasonic receiving apparatus according to the present invention. In this figure,
The elements corresponding to the respective constituent elements of the circuit block diagram shown in FIG.
A symbol is attached and the description is omitted. Incidentally, in the circuit block diagram shown in FIG. 10, for example, each of the minute delay circuits 611 (1), 611 (2),.
If 1 (n-1) and 611 (n) are removed or replaced with another known minute delay circuit, it becomes an embodiment of the fourth ultrasonic receiving apparatus of the present invention. Illustration and description of an independent embodiment of the fourth ultrasonic receiving apparatus will be omitted.

N (for example, 128) minute delay circuits 6
11 (1), 611 (2),... 611 (n−1), 61
1 (n) each have the configuration shown in FIG. 2 or FIG. 4, and each of the minute delay circuits 611 (1), 611
(2),... 611 (n−1), 611 (n), each correction delay circuit 45 constituting the correction delay circuit group 45
(1), 45 (2), ..., 45 (n-1), 45 (n)
Is provided. These correction delay circuits 45 (1),
45 (n-1), 45 (n) are integers in units of a period T of a clock signal CK configured using a shift register 8 as shown in FIG. Each of the stages 8 (1), 8 (2),..., 8 (m) of the shift register 8 is a delay circuit 23 of the above-described addition means (see FIGS. 6 and 8).
(3,1), 23 (4,1) ... 23 (n, n-2); 3
3 (4,1), 33 (5,1), ..., 33 (n, r-
This corresponds to 2). Each of these correction delay circuits 45
(1), 45 (2), ..., 45 (n-1), 45 (n)
In the subsequent stage, each unit addition delay circuit 44 (1), 44
, 44 (n-1), 44 (n) are connected, and each unit addition delay circuit 44 (1), 44 (2),
, 44 (n-1), 44 (n) are respectively adders 441 (1), 441 (2),.
41 (n-1), 441 (n), each delay unit 442
(1), 442 (2), ..., 442 (n-1), 442
(N), each switch 443 (1), 443 (2),..., 4
43 (n-1) and 443 (n). Each of the delay units 442 (1), 442 (2), ..., 442 (n-
1) and 442 (n) are the respective correction delay circuits 45 (1) and 4 (4).
Similarly to 5 (2),..., 45 (n−1), 45 (n),
For example, it has a circuit configuration shown in FIG. 19 and has a function of delaying the clock signal CK by an integral multiple of one cycle T. In addition, each switch 443 (1), 443 (2),
, 443 (n-1), 443 (n) are
2 (1), 442 (2), ..., 442 (n-1), 44
The 2 (n) output signal is switched to one of two systems. Here, a large number of vibrators 1 (1), 1 (2),..., 1 (n−1), 1
Each unit provided corresponding to each of the vibrators 1 (2), 1 (3),..., 1 (n-1) excluding the vibrators 1 (1), 1 (n) at both ends of (n). Addition delay circuits 44 (2), 4
4 (3),..., 44 (n−1)
The outputs of 2 (2), 442 (3),..., 442 (n) are
For example, the output signal of the delay unit 442 (2) is
41 (1) and 441 (3) so as to be inputted to any one of the switches 443 (2), 443 (3),.
The adder 441 on both sides via 443 (n-1)
(1), 441 (2), ..., 441 (n-1), 441
(N). Further, the delay device 4 constituting the unit addition delay circuit 44 (1) corresponding to the vibrator (1) at one end.
The output of the switch 42 (1) is input to either the adder 441 (2) of the unit addition delay circuit 44 (2) or the display correction delay circuit 42 (1) adjacent thereto. 1). Further, a unit addition delay circuit 44 (n) corresponding to the vibrator 1 (n) at the other end.
Is output from the adder 441 (n) of the unit addition delay circuit 44 (n-1) adjacent thereto.
-1) or the display correction delay circuit 42 (2). The above two correction delay circuits 42 (1), 4
2 (2) is a correction delay circuit 45 (1), 45 (2),
, 45 (n-1), 45 (n), delay unit 442
(1), 442 (2), ..., 442 (n-1), 442
Similar to (n), for example, it has the circuit configuration shown in FIG. 19 and has a function of delaying the clock signal CK by an integral multiple of one cycle T. These two display correction delay circuits 4
The outputs of 2 (1) and 42 (2) are input to an adding circuit 43 and added to each other to output a tomographic image display signal SI.

The delay adding means shown in FIG. 11 is controlled by the control circuit 3 to A / D converters 5 (1), 5 (2),.
Each of the digital reception signals SD1, SD2,..., SDn− generated by sampling at (n−1), 5 (n).
1, SDn delay amount and switch 443 (1), 443
, 443 (2),... 443 (n−1), 44
The switching direction of 3 (n) is controlled, whereby dynamic focus with sufficient accuracy is realized over a wide area in the subject.

Hereinafter, for ease of explanation, the circuit operation of the delay adding means shown in FIG. 11 when the number of transducers is eight will be described. However, the minute delay circuit 611
(1), 611 (2), ..., 611 (n-1), 611
Since the operation of (n) has already been described, a small delay circuit 611 (1), 611 (2),.
The minute delay due to 1 (n-1) and 611 (n) will be ignored and described.

FIG. 12 is a diagram showing an example of a delay pattern at the time of a scanning line near the center of the screen in linear scanning and convex scanning. In FIG. 12, the horizontal axis represents eight oscillators 1 (1), 1 (2),..., 1 (8), and the vertical axis represents these oscillators 1 (1), 1 (2),. ) Represents the delay time D of the received signal obtained. Each vibrator 1 (1), 1
Each of the received signals obtained in (2),..., 1 (8) is ideally delayed along a delay pattern D5 indicated by a broken line in the figure. Here, one cycle T of the clock signal CK is delayed. The delay along the delay pattern D6 which is a unit is performed.

FIG. 13 shows the delay pattern D6 shown in FIG.
12 is an explanatory diagram of the operation of the circuit shown in FIG. The analog reception signal obtained by each of the transducers 1 (1), 1 (2),..., 1 (8) is converted into an A / D converter (not shown).
, And is input to each of the correction delay circuits 45 (1), 45 (2),..., 45 (8). In FIG. 13, each correction delay circuit 45 (1), 45
(2),... 45 (8), each rectangle represents a delay of one clock (time T) of the clock signal CK,
For example, in the correction delay circuit 45 (1), the input digital reception signal is input to the adder 441 (1) after being delayed by four clocks (time 4T). The signals output from the adders 441 (1), 441 (2),..., 441 (8) are output from the respective delay units 442 (1), 442 (442).
, 442 (8). Each of these delay units 442 (1), 442 (2),..., 442 (8) also represents one clock delay for each rectangle. Each of the delay units 442 (1), 442 (2),.
The output of (8) is input to the adjacent adder as shown in FIG. 13 by each switch (not shown), or is input to the adder 43 via each display correction delay circuit (not shown). .

Here, each correction delay circuit 45 (1), 45
(2),..., 45 (8) and each delay unit 442 (1),
The numbers in each rectangle of 442 (2),.
The relative delay amount of each signal when one cycle T of the clock signal CK is defined as one unit with respect to the time point when the addition is performed by the adding circuit 43 is shown. Each correction delay circuit 45 (1),
45 (2),..., 45 (8) and each delay unit 442
.. 442 (8) are delayed by the number of clocks corresponding to the number of rectangles shown in the figure, and the signal flow is controlled by each switch as shown in the figure. As shown in the numerical values 4, 6, 7, 7, 7, 7, 7, 6, 4 in the first-stage rectangle of (1), 45 (2),..., 45 (8), the vibrators 1 (1 ), 1 (8), the received signals obtained by vibrators 1 (2),
The received signal obtained by 1 (7) is relative to 2 clocks, and the received signals obtained by other vibrators 1 (3), 1 (4), 1 (5) and 1 (6) are relative to 3 clocks. And is added after being delayed. Thus, the delay pattern D6 shown in FIG. 12 is realized.

Since only the relative delay of each received signal is considered in FIG. 13, the display correction delay circuit 42
Although illustrations of (1) and 42 (2) (see FIG. 11) are omitted, the two display correction delay circuits 42 (1) and 42 (2) use the same delay amount to adjust display timing and the like. It may be delayed. FIG. 14 is a diagram illustrating an example of a delay pattern corresponding to a scanning line near both ends of a screen in linear scanning or convex scanning, or a scanning line when a deflection angle is small in sector scanning.

The horizontal axis and the vertical axis of FIG. 14 represent eight oscillators 1 (1), 1 (2),.
(8), these vibrators 1 (1), 1 (2),...
The relative delay time D of the received signal obtained in (8) is shown. For each received signal obtained by each of the oscillators 1 (1), 1 (2),..., 1 (8), one cycle T of the clock signal CK, which is approximated to D7 of an ideal delay pattern, is defined as a unit of delay. A delay along the delayed pattern D8 is performed.

FIG. 15 is an operation explanatory diagram of the circuit shown in FIG. 11 for realizing the delay pattern shown in FIG.
In FIG. 15, the description of the same parts as those in FIG. 13 is omitted. Each correction delay circuit 45 shown in FIG.
(1), 45 (2),... 45 (8), each delay unit 442
, 442 (2),..., 442 (8) and the display correction delay circuit 42 (1) are delayed by the number of clocks corresponding to the number of each rectangle, and the signal flow is performed by each switch (not shown). Are switched as shown in the figure, so that the respective numerical values 11, 12, 12, 12, 12, 12, 1 in the first-stage rectangle of each of the correction delay circuits 45 (1), 45 (2),.
As shown in 1, 9, and 5, when the received signal obtained by the vibrator 1 (8) is used as a reference, each of the vibrators 1 (2), 1 (2),
, 1 (7) are relatively delayed by 6, 7, 7, 7, 7, 6, and 4 clocks, respectively, and added, whereby the delay pattern D8 shown in FIG. 14 is realized. You.

As described above, in the delay addition means shown in FIG. 11, the control circuit 3 controls the delay amount of each received signal and the switching control of each switch, and can be used for any of linear, convex scanning and sector scanning. Various suitable delay additions can be performed. .., 611 (n−).
Since 1) and 611 (n) are also provided, minute delay with sufficient accuracy is performed without increasing the frequency of the clock signal CK. Incidentally, in the delay adding means shown in FIG. 11, each of the minute delay circuits 611 (1), 611 (2),.
-1) and 611 (n) are the respective correction delay circuits 45 (1) and 4 (4).
5 (2)..., 45 (n−1), 45 (n), but each of these minute delay circuits 611 (1), 6
, 611 (n-1), 611 (n) are correction delay circuits 45 (1), 45 (2),.
Needless to say, it may be provided after 1), 45 (n).

[0067]

As described in detail above, in the first ultrasonic receiving apparatus of the present invention, the delay circuit using one cycle of the clock signal as a delay unit and the digital received signal are divided into two systems. A multiplier that generates a multiplied signal by multiplying one digital reception signal by a first predetermined number;
A multiplying / delaying device for multiplying the other digital reception signal by a second predetermined number and generating a multiplication delay signal by delaying the other digital reception signal for a predetermined time; Since the delay means having both the minute delay circuits each including the signal adder for addition is provided, the frequency of the clock signal may be, for example, about four times the frequency of the received signal or about twice the maximum frequency of the band of the received signal. In addition, the delay can be performed with sufficient accuracy without increasing the circuit scale. In this case, it is sufficient for the multiplier / delayer to delay the digital signal by one cycle of the clock signal.

Further, the second ultrasonic receiving apparatus of the present invention comprises:
A sequential adder circuit in which adders and latch circuits are alternately connected in cascade; and each of the input digital received signals is subjected to a clock signal cycle so that the digital received signals input simultaneously with each other are added to each other. Since there is an adding means composed of a large number of delay circuits for distributing to each of the adders after being delayed by an integer multiple, even if it becomes necessary to add a large number of received signals to each other by using a large-diameter probe, it is extremely efficient. Addition is often performed.

Further, the third ultrasonic receiving apparatus of the present invention comprises a delay adding means comprising the delay means of the first ultrasonic receiving apparatus of the present invention and the adding means of the second ultrasonic receiving apparatus of the present invention. Therefore, the delay can be performed with sufficient accuracy without extremely increasing the frequency of the clock signal (operating speed of the circuit) and without increasing the circuit size as in the first ultrasonic receiving apparatus of the present invention. In addition to the above, addition suitable for increasing the diameter of the probe is performed as in the second ultrasonic receiving apparatus of the present invention.

Further, the fourth ultrasonic receiving apparatus of the present invention
First and second display correction delay circuits for delaying each input signal by an integer multiple of the cycle of the clock signal, an addition circuit for adding the output signals of the first and second correction delay circuits to each other, a number of vibrations A plurality of unit addition delay circuits, each of which is provided with a corresponding one of the adders and the delay unit and the switching unit, having the above-described configuration, and converts each of the input digital reception signals into an integer of the period of the clock signal. Since there is provided a correction delay means including a large number of correction delay circuits that are delayed by twice and distributed to each of the large number of adders,
The concept of the adding means in the second ultrasonic receiving apparatus of the present invention and the delay means using one cycle of the clock signal as a delay unit are organically coupled, so that the overall circuit size is small, the cost is excellent, and the size of the probe is large. An ultrasonic receiver suitable for increasing the aperture is realized.

Further, the fifth ultrasonic receiving apparatus of the present invention further includes a minute delay circuit referred to in the first ultrasonic receiving apparatus of the present invention in addition to the fourth ultrasonic receiving apparatus of the present invention. Both the clock signal of the frequency and the delay of sufficient accuracy with the appropriate circuit scale and the enlargement of the probe are satisfied,
Therefore, an ultrasonic receiving apparatus which meets the demand for higher image quality, is advantageous in cost, and has a circuit suitable for LSI implementation is realized.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of an ultrasonic reception signal.

FIG. 2 is a block diagram of an example of a minute delay circuit.

FIG. 3 is a timing chart of the minute delay circuit shown in FIG. 2;

FIG. 4 is a block diagram of another example of the minute delay circuit.

FIG. 5 is a timing chart of the minute delay circuit shown in FIG. 4;

FIG. 6 is a block diagram illustrating an example of an adding unit.

FIG. 7 is a timing chart of the adding means shown in FIG. 6;

FIG. 8 is a block diagram of another example of the adding means.

FIG. 9 is a timing chart of the adding means shown in FIG. 8;

FIG. 10 is a circuit block diagram of one embodiment of a third ultrasonic receiving apparatus according to the present invention.

FIG. 11 is a circuit block diagram of one embodiment of a fifth ultrasonic receiving apparatus according to the present invention.

FIG. 12 is a diagram illustrating an example of a delay pattern.

13 is an operation explanatory diagram of the circuit shown in FIG. 11 for realizing the delay pattern shown in FIG. 12;

FIG. 14 is a diagram illustrating another example of the delay pattern.

15 is an operation explanatory diagram of the circuit shown in FIG. 11 for realizing the delay pattern shown in FIG. 14;

FIG. 16 is a schematic diagram showing a relationship between a transducer and a reflection point of an ultrasonic wave in a subject.

FIG. 17 is a schematic diagram showing a relationship between a vibrator and a delay time.

FIG. 18 is a diagram illustrating an example of a circuit block of a conventional ultrasonic diagnostic apparatus.

FIG. 19 is an internal block diagram of the delay circuit.

FIG. 20 is a schematic diagram of an ultrasonic reception signal.

[Explanation of symbols]

1 oscillator group 1 (1), 1 (2), ..., 1 (n-1), 1 (n) oscillator 2 clock generation circuit 3 control circuit 4 transmission driver group 5 A / D converter group 5 (1 ), 5 (2), ..., 5 (n-1), 5 (n) A
/ D converter 6 delay circuit group 6 (1), 6 (2), ..., 6 (n-1), 6 (n) delay circuit 7 adder circuit 11 A / D converter 12 multiplier 13 delay device 14 multiplication 15 and 16 Memory 17 Signal adder 20 Sequential addition circuit 21 (1), 21 (2) ..., 2 (n-1) Adder 22 (1), 22 (2) ..., 22 (n-2) Latch Circuits 23 (3,1), 23 (4,1), 23 (4,2) ...,
23 (n, n-2) delay circuit 30 sequential addition circuit 311 (1), 311 (2), ..., 311 (n-1)
Individual adders 33 (4,1), 33 (5,1) ..., 33 (n, r-
2) Delay circuits 61 (1), 61 (2), ..., 61 (n-1), 61
(N) delay means 611 (1), 611 (2),... 611 (n-1), 6
11 (n) minute delay circuit 71 addition means 42 (1), 42 (2) display correction delay circuit 43 addition circuit 44 (1), 44 (2), ..., 44 (n-1), 44
(N) unit addition delay circuit 441 (1), 441 (2),..., 441 (n−1),
441 (n) adders 442 (1), 442 (2), ..., 442 (n-1),
442 (n) delay units 443 (1), 443 (2),..., 443 (n−1),
443 (n) switch 45 correction delay circuit group 45 (1), 45 (2), ..., 45 (n-1), 45
(N) Correction delay circuit

Claims (2)

(57) [Claims] A plurality of transducers arranged in a predetermined direction and a clock signal having a predetermined period are generated, which receive ultrasonic waves transmitted into the subject and reflected in the subject to obtain respective analog reception signals. A clock generating circuit that performs analog-to-digital conversion on each of the analog reception signals obtained by each of the plurality of vibrators for each of the predetermined periods and outputs each digital reception signal;
Numerous delay means of variable delay amount for delaying the digital reception signals so that the digital reception signals corresponding to the ultrasonic waves reflected substantially simultaneously at substantially the same position in the subject are output substantially simultaneously with each other. And an ultrasonic receiving apparatus including an adding unit that adds the digital reception signals output from the multiple delay units to each other, wherein each of the multiple delay units is configured to multiply the digital reception signal by an integer multiple of the predetermined period. A delay circuit for delaying the time of the digital reception signal, a multiplier for generating a multiplication signal by multiplying one of the digital reception signals obtained by dividing the digital reception signal by a first predetermined number, and The other digital received signal divided into the system is multiplied by a second predetermined number, and the other digital received signal is An ultrasonic wave, comprising: a multiplication / delay device that generates a multiplication delay signal by delaying by a fixed time; and a minute delay circuit that includes a signal adder that adds the multiplication signal and the multiplication delay signal to each other. Receiver. 2. The clock generation circuit according to claim 1, wherein the clock generation circuit generates a clock signal having a frequency four times a center frequency of the analog reception signal, and the multiplication / delay device adds a second predetermined signal to the other digital signal. 2. The ultrasonic receiving apparatus according to claim 1, wherein the ultrasonic receiving apparatus multiplies the number and delays the other digital received signal by one cycle of the clock signal.