JP2736061B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a method for manufacturing a semiconductor device, and introduces impurities into a silicon surface, for example, a silicon groove formed by RIE. On how to do it. (Prior Art) In a MOS dynamic memory (dRAM), miniaturization and high integration of elements are being promoted in accordance with the proportional reduction rule. MOS capacitor which is a component of dRAM is no exception, the reduction of the gate oxide film thickness t _ox and area S is advanced. When the scaling coefficient alpha, the gate oxide film thickness in t _ox / alpha, area is in S / alpha ^2. The capacitance C is the dielectric constant of the MOS capacitor as epsilon, since represented as C = εS / t _ox, the capacitance C 'is, C' after proportionally reduced = C / alpha becomes smaller to 1 / alpha. Thus, when the capacity of the MOS capacitor becomes small,
Soft errors due to alpha rays are more likely to occur,
In addition, as the ratio with the capacitance of the bit line is reduced and the sensing margin is reduced, a malfunction may occur. For this reason, the area of the MOS capacitor is generally not reduced to S / α ² but to S / α. However, as the size shrinks with each generation, obtaining reliable dRAM is approaching its limit. The use of an insulating film having a large dielectric constant, for example, a Ta ₂ O ₅ film as a means for increasing the capacity of the MOS capacitor has been studied, but has not yet been put to practical use. Also, 10
Consideration is being given to the application of extremely thin and highly reliable silicon oxide films of nm or less, but this also requires extremely high-purity pure water and chemicals, and also requires a clean room with high cleanliness. Has not been put to practical use. Therefore, at present, as a method of increasing the capacity of the MOS capacitor, a method of digging a groove in the surface of the semiconductor substrate to substantially increase the capacitor area without increasing the occupied area is being studied. Also, in order to improve the reliability of the MOS capacitor oxide film against destruction with time, an impurity diffusion layer is formed on the surface of the capacitor Si substrate, the potential of the upper electrode is kept at Vcc / 2, and the impurity diffusion layer of the substrate is maintained. 0V and 5V on the side
A method of distinguishing the contents of the memorandum by taking the two potentials is used. In forming the above-mentioned trenching capacitor, in order to form a deep groove having a small opening area, it is necessary to form a groove having vertical side walls by reactive ion etching (RIE). However, if a conventional ion implantation method is used to form the impurity diffusion layer on the surface of the sidewall close to the vertical, it is difficult to form the impurity diffusion layer with a uniform concentration over the entire sidewall surface. is there. Therefore, in order to achieve a uniform concentration distribution, a silicon oxide film doped with impurities is deposited on the surface inside the trench, and then heat-treated at a high temperature,
A method of diffusing impurities from the silicon oxide film to the silicon surface inside the trench has been studied. The impurity diffusion layer formed on the side wall increases the amount of stored charge in the capacitor.
In order to maintain a surface concentration of 5 × 10 ¹⁸ cm ⁻³ or more and to maintain good separation from the capacitor formed in the adjacent groove, the depth of the diffusion layer needs to be small. To achieve the object, the impurity concentration in the impurity-doped oxide film must be increased. However, after forming the Si groove by the RIE method, the impurity-doped oxide film is deposited, and when the impurity is diffused from the oxide film to the silicon surface inside the Si groove by a high-temperature heat treatment, the oxide film and the silicon There is a problem that a precipitate of an impurity is formed at the interface with the silicon and the surface concentration and diffusion depth of the diffusion layer to be formed on the silicon surface vary. It is considered that these are because impurities having a concentration higher than that capable of forming a solid solution in silicon reach the interface. If the diffusion temperature is lowered, there arises a problem that a high surface concentration cannot be obtained. (Problems to be Solved by the Invention) The present invention is to oxidize and remove the silicon surface before forming an impurity oxide film on the silicon surface, or to perform a high-temperature short-time heat treatment from the impurity-added oxide film. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a diffusion layer is formed with good controllability by applying a primary oxidation means. [Constitution of the Invention] (Means for Solving the Problems) The present invention provides a method for forming an impurity-doped oxide film on a silicon surface inside a silicon groove formed by RIE.
After oxidizing the silicon surface inside the trench to form an oxide film and etching to remove the shell when impurities are deposited, the impurity oxide film is applied and a heat treatment is performed to form a diffusion layer on the silicon surface with good controllability. . Alternatively, after depositing an impurity-doped oxide film on the silicon surface, the total amount of impurities in the diffusion layer to be formed is transferred to the silicon substrate by a heat treatment at a high temperature of 1050 ° C. or higher and a short time of 100 seconds or shorter, Thereafter, in order to obtain a desired diffusion depth, heat treatment at 1000 ° C. or less is performed to form a diffusion layer in which both the surface concentration and the diffusion depth are well controlled. (Operation) In RIE for forming a silicon groove, CF ₄ or CCl ₄
Carbon fluoride gas or chloride gas is used, but the carbon-based deposits formed at that time are removed because they are oxidized in a high-temperature oxidizing atmosphere to become carbon dioxide and volatilized. Is done. In addition, crystal defects remaining as damage near the silicon surface by RIE are not only removed by oxidation, but also crystallinity is restored and disappeared by high-temperature heat treatment. Further, the concentration and diffusion rate of impurities that can be dissolved in silicon greatly depend on temperature. Therefore, if the concentration of impurities added to the oxide film is reduced so as not to precipitate, the surface concentration of the diffusion layer is reduced. Therefore, after an oxide film containing impurities at a high concentration is applied to the silicon surface, the silicon substrate is subjected to a heat treatment at a high temperature of 1050 ° C. or more for 100 seconds or less by irradiating light with a lamp or the like. A diffusion layer having a high surface concentration and a small diffusion depth is formed without forming a precipitate at the interface of the silicon substrate. By the way, heat treatment at 1100 ° C for 10 seconds results in a surface concentration of about 10
^{At 21} cm ^-3 the diffusion depth is about 100 mm. Then 1000
A desired depth can be obtained by performing a heat treatment at a temperature of not more than ° C. 1000 ° C for the impurity diffusion layer diffused under the above conditions
Heat treatment for 1 hour, the surface concentration is about 1 ×
At 10 ¹⁹ cm ^-3 , the diffusion depth can be controlled to approximately 0.1 μm. At this time, even if precipitates are formed at the interface and transfer of impurities to silicon is hindered, since the amount of impurities necessary for forming the diffusion layer already exists in silicon,
A sufficient surface concentration can be obtained. As described above, according to the present invention, a desired diffusion depth can be obtained while maintaining a sufficient surface concentration. (Example) FIGS. 1A to 1D are process cross-sectional views showing a manufacturing process of an example of the present invention. As shown in FIG. 1A, for example, an N-type (100) silicon substrate 1 having a specific resistance of 10 Ω · cm is prepared, and reactive ion etching (RIE: Reactive Ion Etc) is performed.
The oxide film 2 serving as a mask for forming a groove in a silicon substrate by the hing) method is formed by CVD (chemical vapor deposition).
Formed by photolithography and the RI of the oxide film 2
After removing the oxide film in the groove forming portion by E, the groove 3 is formed by the RIE method using an etching gas containing CCl ₄ as a main component. Subsequently, as shown in FIG. 1B, the mask oxide film 2 is removed by etching with diluted hydrofluoric acid.
After forming a 200 膜 oxide film 4 with 800 ℃ steam, 1000
Heat-treat in a non-oxidizing atmosphere at 30 ° C for 30 minutes. Thereafter, as shown in FIG. 1 (c), the oxide film 4 is removed by etching with diluted hydrofluoric acid, and then the oxide film 5 to which arsenic atoms are added at 10 ²¹ cm ^-3 or more is formed by low-pressure CVD (Chemical Vapor Depositio).
After the deposition at 1000 ° by the n) method, heat treatment is performed in a nitrogen atmosphere at 1000 ° C. for 1 hour to form an impurity diffusion layer 6 on the groove surface. Further, as shown in FIG. 1 (d), an oxide film 7 having a thickness of 10 nm for a MOS capacitor is formed at 900 ° C. in dry oxygen diluted to 50% with an argon gas. A crystalline silicon gate electrode 8 is formed. In this embodiment, the heat treatment was performed for 30 minutes in a non-oxidizing atmosphere at 1000 ° C. after forming the oxide film 4 at 200 ° C. with steam at 800 ° C., but within the scope of the present invention, this oxidation and heat treatment It goes without saying that various modifications are possible. In short, it is only necessary that crystal defects due to deposits or damage on the silicon surface during RIE for forming a silicon groove disappear. According to this embodiment, as shown in the plan view of FIG. 2A and the cross-sectional view of FIG. 2B, the CV (capacity- The voltage) characteristics are shown in FIG. In FIG. 3, C-C of the MOS capacitor formed according to the conventional example and the present embodiment is shown.
The V characteristic is shown. Next, another embodiment of the present invention will be described. 4 (a) to 4 (c) are process cross-sectional views showing a manufacturing process of another embodiment of the present invention. As shown in FIG. 4A, for example, an N-type (100) silicon substrate 11 having a specific resistance of 10 Ω · cm
Is prepared and reactive ion etching (RIE: Reactive Ion
An oxide film 12 serving as a mask when forming a groove in a silicon substrate by an etching method is formed by CVD (Chemical Vapor Depositi).
on), and then the photolithography method and the oxide film 12 are formed.
After removing the oxide film in the groove forming portion by RIE, the groove 1 is formed by RIE using an etching gas containing CCl ₄ as a main component.
Form 3. Subsequently, as shown in FIG. 4 (b), the mask oxide film 12 is removed by etching with diluted hydrofluoric acid, and then an oxide film to which arsenic atoms have been added in an amount of 5 × 10 ²¹ cm ⁻³ or more.
14 is applied by low-pressure CVD (Chemical Vapor Deposition), and then heat-treated at 1100 ° C. for 10 seconds, and then heat-treated at 1000 ° C. for 1 hour in a nitrogen atmosphere to form an impurity diffusion layer 15 on the groove surface. Further, as shown in FIG. 4C, a 10 nm-thick oxide film 16 for the MOS capacitor is
Thereafter, the gate electrode 17 is formed in dry oxygen diluted with argon gas, and thereafter a normal phosphorus-doped polycrystalline silicon gate electrode 17 is formed. In this embodiment, the arsenic concentration in the deposited oxide film is 5 × 10 ²¹ cm.
^-3 , The high-temperature and short-time heat treatment condition was 1100 ° C. for 10 seconds, and the subsequent diffusion condition was 1000 ° C. for 1 hour. However, within the scope of the present invention, this oxidation and heat treatment can be variously modified. Not even. In short, heat treatment is performed at a high temperature to suppress the formation of precipitates on the silicon surface, and the heat treatment is performed in a short time to suppress the diffusion depth. Is to suppress. According to this embodiment, as shown in the plan view of FIG. 5A and the cross-sectional view of FIG. 5B, the CV (capacity- The voltage) characteristics are shown in FIG. In FIG. 6, the C-value of the MOS capacitor formed according to the conventional example and the present embodiment is shown.
The V characteristic is shown. [Effects of the Invention] According to the present invention, it is possible to manufacture a semiconductor device in which a capacitor having a small capacitance change can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a process according to one embodiment of the present invention, FIG. 2 is a structural view of a device completed according to the present invention, and FIG. FIG. 4 is a cross-sectional view showing a process for explaining another embodiment of the present invention, FIG. 5 is a completed structure diagram, and FIG. 6 is an evaluation diagram thereof. 1,11… silicon substrate, 2,12… oxide film for RIE mask, 3,13… silicon groove, 5,14… impurity doped oxide film, 6,15… impurity diffusion layer, 7,16… ... Gate oxide film for MOS capacitor, 8,17 ... Capacitor gate electrode.

Claims (1)

(57) [Claims] Forming a groove in the semiconductor substrate; forming an impurity-doped oxide film in the groove; and performing a heat treatment at a first temperature to diffuse impurities from the impurity-doped oxide film to the surface of the groove; Performing a heat treatment at a second temperature lower than the first temperature. 2. 9. The method according to claim 8, further comprising a step of removing the impurity-doped oxide film, a step of forming an insulating film on the surface of the groove, and a step of forming an electrode on the surface of the insulating film. 2. The method for manufacturing a semiconductor device according to claim 1. 3. Forming a groove in the semiconductor substrate; forming an impurity-doped oxide film in the groove; and forming impurities at an interface between the semiconductor substrate and the impurity-doped oxide film. A semiconductor, comprising: a first heat treatment step of introducing an impurity from the additional oxide film to the surface of the groove; and a second heat treatment step of forming a diffusion layer on the surface of the groove using the impurity introduced to the surface of the groove. Device manufacturing method. 4. 4. The method according to claim 3, wherein the second heat treatment step is lower in temperature and longer than the first heat treatment step.