JP2733861B2 - External synchronous programmable device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention enables a circuit designer to easily realize or change an arbitrary circuit according to a desired circuit specification,
For example, the present invention relates to an external synchronization type programmable device capable of performing a so-called external synchronization operation such that an internal circuit operates in synchronization with the phase and frequency of an external signal.

[Conventional technology]

Conventionally, a programmable logic device (programmable logic device) has been used as a device that allows a circuit designer to easily realize or change a circuit according to a desired circuit specification.
vice) is known.

In this programmable logic device, an appropriate logic path of an AND-OR two-stage configuration can be realized by programming appropriate grid points of an AND matrix and an OR matrix, and the circuit is changed by changing the program. Since it can be redesigned, it has excellent functions such as being versatile.

Further, the programmable logic device not only realizes a simple random logic, but also realizes an arbitrary sequential circuit by feeding back the output of the logical sum matrix or the output of the built-in flip-flop to the input side of the logical product matrix. Therefore, it is suitable for use in control devices such as a sequential controller and various measuring instruments.

Conventionally, a programmable logic device having a configuration as shown in FIG. 5 has been generally used. In other words, the in FIG. 5, an input signal line L ₁ ~L _m and product term lines l ₁ consisting of arrayed horizontal line group so as to cross these input signal lines to l _n consisting of longitudinal line group in Fig. made a logical matrix 1, these product term lines l ₁ to l _n which can realize any logic circuit by suitably programming the lattice points formed on each of these intersections portion provided with a An OR matrix (functionally indicated by multiple-input OR gates OR _{1 to} OR _i in the figure) connected via an AND output (functionally indicated by an AND gate in the figure) is provided. Furthermore, general-purpose input ports I _{1 to} I _j for supplying a logic signal from outside to some of the input signal lines in the input signal lines L _{1 to} L _m , and a clock input terminal CLK for supplying a clock signal , An output port for outputting an output signal of an OR matrix (multi-input OR gates OR _{1 to} OR _{i in the} figure) to the outside, and a control signal for controlling an output timing of the output port. A control signal input terminal CNT and the like are provided.

The configuration of the output port, Stated representative output circuit according to the output terminals P _1, (indicated by OR ₁ in the figure) certain logical sum output is connected to the data input contact D of the D-type flip-flop FF ₁ and, connected to the output terminal P ₁ and the output contact point Q via the output buffer circuit B _1. The clock input contacts of the flip-flop FF ₁ is wired so that the clock signal from the clock input terminal CLK via the input buffer circuit is supplied, the output buffer circuit B ₁ represents a control signal input terminal
To transfer the output signal of the flip-flop FF ₁ to the output terminal P ₁ in response to the logic level of the control signal supplied from the CNT, into a high impedance state. Moreover, it is wired to feed back the inverted output of the flip-flop FF ₁ in a part of the input signal line group of the input signal line L ₁ ~L _m via a buffer circuit FB _1. The output circuit according to the output terminal P ₂ to P _i of residual also has the same configuration, for example, those of the output circuit are formed in the cell structure.

Then, by programming an appropriate lattice point of the logical product matrix 1, a shift resist, a counter, and the like are formed by the above-described flip-flops formed in the output circuit, and the output is fed back to the logical product matrix 1. A complicated sequential controller and various signal processing circuits can be realized.

[Problems to be solved by the invention]

By the way, as an effective technical technique in a sequential controller or a signal processing circuit, it is known to control various devices and perform signal processing by synchronizing a phase and a frequency so as to follow a phase and a frequency of a certain signal. ing.

According to this technical method, when a plurality of systems each operating in synchronization with different frequencies are operated in synchronization with each other, the phase of a signal transmitted from one system is synchronized. By operating the other system so as to follow the frequency and the frequency, the other system can be operated synchronously with the one system.

A PLL (phase-locked loop) is known as a typical example of the technical means for performing the so-called external synchronization. As an application example, a motor speed control system, an FM / AM transmission / reception system, It is applied to measuring instruments that extract only the target signal from noise, and the PLL device
Developed as C (integrated circuit).

However, conventional PLL devices have been developed as dedicated devices for various applications.
It is necessary to select a specific PLL device according to the application, and to change the system, replace it with a separate PLL device, and furthermore, a PLL device suitable for realizing the desired system However, there are problems such as inconvenience such as not being able to be found, and low degree of freedom in system design.

The present invention has been made in view of such a conventional problem, and enables an external synchronous operation and allows a circuit designer to easily realize or change an arbitrary circuit according to a desired circuit specification. An object of the present invention is to provide a highly versatile external synchronous programmable device.

[Means for solving the problem]

In order to achieve such an object, the present invention provides a programmable logic unit having a logical product matrix and a logical sum matrix for realizing an arbitrary logic circuit by connecting appropriate grid points by a program, A phase difference with an internal signal formed by a logic circuit formed by the program is compared, a signal indicating the phase difference is output, and a signal indicating whether the phases match or not matches a predetermined value of the logical product matrix. And a phase comparison circuit for supplying the input signal line to the programmable IC device.

[Action]

According to the present invention having such a configuration, by inputting an external signal supplied from the outside and an internal signal generated by an internal circuit realized by an internal programmable logic unit to the phase comparator, the external signal is Since a difference signal indicating the delay or advance of the phase or frequency between the internal signals can be generated, an external synchronization type system such as a PLL that feeds back the internal circuit so that the difference signal reaches a predetermined value is used. It can be realized easily and with a small number of parts.

Also, by realizing a control circuit for controlling various devices in accordance with a signal indicating whether the phases of the two signals match or not with a programmable logic unit, an external synchronous system such as a PLL can be easily and reduced in number of parts. It can be realized with points.

Furthermore, since the programmable logic section can form an arbitrary circuit by programming an appropriate grid point, the degree of freedom in design is high and changes can be easily made.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

First, the structure will be described with reference to FIG. In this embodiment, which are formed as a single IC (integrated circuit device) by CMOS semiconductor process, to the signal input line L ₁ ~L _m and these signal input line consisting of longitudinal line group in Fig. It is realized any logic circuit by programming the lattice points formed on each of these intersections portions appropriately with and a product term lines l ₁ to l _n consisting of arrayed horizontal line group so as to intersect logical the product matrix 1, functions in the logical sum matrix (Fig connected through an aND output (in the figure indicated by functionally aND gate) made from these product term lines l ₁ to l _n which can Other input OR gates OR _{1 to} O
R _i , OR _X , OR _Y ). Further, the input signal line L ₁
To general input terminals I _{1 to} I _j for externally supplying a logic signal to some of the input signal lines within L _m , and a clock signal CK.
And a control signal input terminal CNT for supplying a control signal. Then it is formed output port having a plurality of output terminals P ₁ to P _i for outputting an output signal of the OR matrix (multi-input OR gates OR ₁ ~OR _i in the figure) to the outside.

Stated on behalf of the output circuit according to the output port Output terminals P _1, (indicated by OR ₁ in the figure) certain logical sum output is connected to the data input contact D of the D-type flip-flop FF _1, the output contact Q is connected to the output terminal P ₁ via the output buffer circuit B _1. The clock input contact CK of the flip-flop FF ₁ is connected to the clock input terminal via the input buffer circuit.
CLK are wired so that the clock signal is supplied from the output buffer circuit B ₁ represents an output terminal P to the output signal of the flip-flop FF ₁ in response to the logic level of the control signal supplied from the control signal input terminal CNT Transfer to ₁ or change to high impedance state. Furthermore, flip-flop FF ₁
An inverted output via a buffer circuit FB ₁ signal input line L ₁ of
It is wired to return a portion of the signal input line group among the ~L _m. The output circuit according to the output terminal P ₂ to P _i of residual also has the same configuration, for example, those of the output circuit are formed in the cell structure.

Furthermore, 2 input-output terminal is OS ₁ and an amplifier connected between the SO _2, its input contact is connected to the clock input of the internal flip-flop (CK).

3 is a phase comparison circuit, which is a certain OR matrix OR _X
The first signal S ₁ output from the logical sum matrix OR _Y
Comparing the second phase between the signal S ₂ output from the logic signal S indicating the outputs a logic signal S _U and S _D representing the phase difference, the phase of both signals a match or mismatch Output _LX .

4 is a charge pump circuit outputs a pulse modulated digital signal SP corresponding to the logic signal S _U and S _D output from the phase comparator circuit 3 to the output terminal Pn _1.

FIG. 2 shows the phase comparison circuit 3 and the charge pump circuit 4
The following shows a specific example of the circuit. That is, the phase comparator 3, a plurality of NAND gates, the AND gate, a digital phase comparator circuit constituted by the inverter gate and an exclusive OR gates (Exclusive NOR Gate), signal S for the signals S ₁ supplied The logic signal _SU and the logic signal _SD having a time width corresponding to the phase difference at the rising edge of ₂ are output. When the relative signal S ₂ phase of the signal S ₁ is proceeds, the logic signal S _D is "H" level, the Ki phase of the signal S ₁ is delayed with respect to signal S _2, the logic signal S _U " L "level.

Further, a circuit including an AND gate 3a, an exclusive OR gate 3b, a NAND gate 3c, and an inverter gate 3d outputs a signal S ₁
"H" level when the phase match of S _2, the phase and outputs a logic signal S _LK the logic level of both signals S ₁ and S ₂ of the phase becomes "L" level at a different range when a mismatch between .
The logic signal _SLK is wired so as to be output via the output terminal _PLK .

On the other hand, as shown in FIG. 2, the charge pump circuit 4 is formed of a P-channel MOS transistor and an N-channel MOS transistor connected between the power supply contact _VDD and the ground contact. Logic signal _SU is supplied to the gate contact of
The gate contact type transistor with a logic signal S _D are wired to be supplied, these common node contacts are connected to the output terminal Pn _1. Therefore, when the logic signal _SU is at the “L” level and the logic signal _SD is at the “L” level, an “H” level output _SP is generated, and the logic signal _SU is at the “H” level and the logic signal S If _D is "H" level, "L" level to generate an output S _P, in the case of other combinations, except for the transient state, the output terminal Pn ₁ a high impedance state.

Further, in FIG. 1, 5 is a D-type flip-flop, the logic signal S _LK from the phase comparator 3 is supplied to the data input contact D, the output signal S _F output contact Q via the buffer circuit 6 With the input signal line l _{m-1 of the} logical product matrix 1
It is wired so as to be supplied to L _m-2 . Further, a signal _SCK from a predetermined output of the AND matrix 1 (functionally indicated by an AND gate 9) is used as a clock (C
K) supplied to the input.

FIG. 3 shows a circuit configuration when the external synchronous programmable device of the embodiment having such a structure is applied to a PLL. That is, the portion shown in the dotted line in FIG. 3 is the external synchronous programmable device according to this embodiment, and 1 / M is programmed by programming an appropriate lattice point of the logical product matrix 1 (see FIG. 1). Frequency divider 1a, 1 / N
A frequency dividing circuit 1b and a signal processing circuit 1c are realized.

Incidentally, 1 / M frequency dividing circuit 1a is, for example, and inputting an external signal S _G from the outside to the input terminals I _1, predetermined output OR _X of the OR matrix an external signal S _G and M division as the divided signal S ₁ is generated, realized by programming the appropriate grid points of the aND matrix.

1 / N frequency dividing circuit 1b is a signal S _Y that the input signal line L _m N
Dividing so that the signal S _2, which is the division to a predetermined output OR _Y of the OR matrix is generated, realized by programming the appropriate grid points of the AND matrix.

The signal processing circuit 1c is a circuit for outputting the output _SLK from the phase comparison circuit 3 to the input signal lines Lm _-1 and Lm _-2 via the flip-flop 5 to form various control signals. Yes, it is formed by programming the appropriate grid points between the input signal lines Lm _-1 and Lm _-2 and the OR matrix.

The clock signal generation circuit 10 is provided with the logical product matrix 1
Are formed by programming the appropriate grid points so that a signal _SCK is generated at the output of a predetermined AND matrix indicated by the AND gate 9 in FIG.

Furthermore, as an external circuit, as shown in FIG.
A low-pass filter (lag-lead filter) 11 consisting of a resistor and a capacitor is connected to the output terminal Pn ₁ and the input / output terminals OS ₁ and O
Crystal resonator between S _2, variable capacitance diodes, resistors and constitute a voltage controlled oscillator circuit 12 comprising including amplifier 2 by connecting the capacitor or the like, the output signal S _P is the voltage controlled oscillator circuit of the low-pass filter 11 It is supplied to 12 input contacts.

According to thus constituted PLL circuit generates a signal S _Y of the oscillation frequency by the voltage-controlled oscillator circuit 12 corresponds to the voltage of the signal output S _P from the low-pass filter 11, 1 / N frequency dividing circuit 1b
There outputs a signal S ₂ by dividing the signal S _Y to 1 / N. Also, 1
/ M frequency dividing circuit 1a is a signal S _G and outputs the signals S ₁ and M division.
Then, the phase comparison circuit 3 detects a phase difference between the signal S ₁ and the internal signal S ₂ , a signal corresponding to the phase difference is output from the charge pump circuit 4, and further, the signal S integrated by the low-pass filter 11. _P is output.

Then, the feedback control in the PLL circuit by automatically repeating the phase difference between the signals S ₁ and the internal signal S ₂ is actuated so that the zero, external synchronization is realized with respect to the external signal S _G.

FIG. 4 shows the phase comparison circuit of FIG. 2 and the PL shown in FIG.
To illustrate the operation of the L circuit, the signal S _{1 is} compared to the signal S ₂
5 shows signal waveforms at the respective contacts when the phase is delayed, when the phase is advanced, and when the phase is completely locked.

Here, as shown after 1200 μS, when the phases of the signals S ₁ and S ₂ coincide with each other, the AND in the phase comparison circuit 3
_A so-called whisker in the form of a pulse is generated in the output signal S _A of the gate 3a (see FIG. 2), and no such pulse is generated in the output signal S _X of the exclusive OR gate 3b. even logic signal S _LX finally occurs 3 will causing whiskers, when a logic signal S _LX containing the whiskers directly supplied to the signal processing circuit 1c according to a logical product matrix, is possible to perform normal signal processing become unable. However, in this embodiment, a flip-flop 5 for removing such an unnecessary whisker-like pulse is built in in advance, and the logic signal S
_{Since LX} is fed back into the AND matrix via the flip-flop 5, normal signal processing can be performed.

As described above, according to the embodiment, an arbitrary circuit according to the program can be realized by programming appropriate lattice points of the logical product matrix (see FIG. 1), and the phase of the two signals can be changed. The built-in phase comparison circuit that supplies a logic signal that detects a match or a mismatch to the AND matrix is very effective in realizing an external synchronous system, and is versatile and offers great design flexibility. Can be improved.

In the above embodiment, the case of manufacturing by applying the CMOS process has been described. However, by applying the Bi-CMOS process,
A phase comparison circuit capable of processing an analog signal may be formed therein.

〔The invention's effect〕

As described above, according to the present invention, by inputting an external signal supplied from the outside and an internal signal generated by an internal circuit realized by an internal programmable logic unit to a phase comparator, the external signal Since it is possible to generate a signal indicating the advance, delay, or coincidence of the phase or frequency between the internal signals, an external synchronous type such as a PLL for feeding back a voltage-controlled oscillation circuit so that the signal reaches a predetermined value. The system can be easily realized with a small number of parts.

Also, since a control circuit for controlling various devices in accordance with a signal indicating whether the phases of the two signals match or not can be realized using the programmable logic unit,
A complicated external synchronization type system can be easily realized with a small number of parts.

Furthermore, since the programmable logic section can form an arbitrary circuit by programming an appropriate grid point, the degree of freedom in design is high and changes can be easily made.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing the configuration of an embodiment according to an embodiment of the present invention; FIG. 2 is a circuit diagram showing a specific circuit example of a phase comparator; FIG. FIG. 4 is a timing chart for explaining the operation of the PLL circuit shown in FIG. 3; FIG. 5 is a configuration explanatory diagram showing a configuration of a conventional programmable logic device; Symbols in the figure: 1; AND matrix 1a; 1 / M frequency divider 1b; 1 / N frequency divider 1c; signal processing circuit 2; amplifier 3; phase comparator 3a; AND gate 3b; exclusive OR gate 3c; NAND gate 3d; Inverter gate 4; Charge pump circuit 5; Flip-flop 6; Buffer circuit 7a, 7b; Analog switch 9; Output of AND matrix 10; Clock signal generation circuit 11; Low-pass filter 12; Voltage control Oscillator circuit 13, 15; Analog switch 14; Output buffer circuit 16; Inverter gate

Claims (1)

(57) [Claims] A programmable logic unit having a logical product matrix and a logical sum matrix for realizing an arbitrary logic circuit by program connection; and an external signal and an internal signal formed by the logic circuit formed by the program. A phase comparison circuit for comparing the phase difference and outputting a signal indicating the phase difference, and supplying a signal indicating whether the phases match or not to a predetermined input signal line of the AND matrix; An external synchronous type programmable device characterized by the above-mentioned.