JP2729819B2 - Synchronous tracking circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a delay lock loop (hereinafter referred to as "delay lock loop").
DLL).

[Prior Art] FIG. 2 is a block diagram showing a conventional circuit of this type, in which (1) is a demodulator, (2) is an A / D converter,
(3) is a Viterbi decoder, (5) and (8) are multipliers, (6) and (9) are bandpass filters (hereinafter referred to as BPF), and (7) and (10) are Envelope detector, (11) is an adder, (12) is a loop filter, (14) is a PN code generator (PN is pseudo noise), and (15) is a voltage controlled oscillator (hereinafter
VCO). Y (t) is the input signal, E
(T) represents Early code, and L (t) represents Late code.

The input signal y (t) is demodulated by the demodulator (1),
The signal is converted into a binary signal by the D converter (2), and soft-decision Viterbi decoding is performed by the Viterbi decoder (3). This decryption involves:
The clock signal extracted from the input signal y (t) is used. That is, reference numerals (5), (6), (7),
(8), (9), (10), (11), (12), (14),
The part indicated by (15) is a synchronization tracking circuit for extracting a clock signal. When the oscillation phase of the VCO (15) is locked by this circuit, a clock for decoding is output from the VCO (15) (circuit (Not shown).

FIG. 3 is an explanatory diagram for explaining the operation of the synchronization tracking circuit shown in FIG. 2. In each figure of FIG. 3, the horizontal axis represents the phase difference between the two input codes of the multiplier (5) or (8), and the vertical axis. Is an adder (11)
Is the output of FIG. 3A shows, for example, the phase difference between the code sequence included in y (t) and E (t) when the output of the envelope detector (7) is turned off, and the adder (1) at that time.
The correspondence with the output of 1) is shown.

FIG. 3B shows the outputs of the envelope detectors (7) and (10) when the amount of phase delay between E (t) and L (t) is one chip (one sign bit) τ. When superimposing with opposite polarities [addition is performed by reversing the detection polarities of the envelope detectors (7) and (10). When the detection polarities of (7) and (10) are the same, subtraction is performed by the adder (11)], and FIG. 3 (c) shows the characteristics of the result of the superposition. If the phase difference is between A and B in FIG. 3 (c), the VCO (15) is subjected to negative feedback control, and the phase difference becomes near point S. The section AB is temporarily referred to as a capture range.

FIG. 3 (d) shows the outputs of the envelope detectors (7) and (10) when the phase delay between E (t) and L (t) is τ / 2, superimposed with opposite polarities. FIG. 3 (e) shows the characteristics of this superimposed result. The capture range in the case of FIG. 3 (e) is CD.

Comparing the two characteristics shown in FIGS. 3 (c) and (e),
(C) has a wider capture range, so even if the phase error suddenly increases for some reason, it can be returned to the synchronization point. However, (e) shows the phase difference characteristic with respect to the loop filter output. , The amount of phase jitter can be reduced.

Assuming that the amount of phase jitter is σ, the bandwidth of the BPFs (6) and (9) is B, the chip period is T, the equivalent noise bandwidth is B _L , the carrier power is P, and the one-sided noise power density is N. For the characteristic of (c), (σ / T) ² = NB _L (1 + 2NB / P) / 2P, and for the characteristic of FIG. 3 (e), (σ / T) ² = NB _L (1 + 8NB / 9P) ) / 4P means that
For example, JK Holmes: Coherent Spread Spectrum System
(Wiley 1982).

[Problem to be Solved by the Invention] Since the conventional device is configured as described above,
Since the amount of phase delay between (t) and L (t) is fixed, there is a problem that it is not possible to switch between increasing the capture range or decreasing the phase jitter depending on the situation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem in the conventional art, and has as its object to obtain a synchronization tracking circuit that automatically switches the amount of phase delay according to the situation.

[Means for Solving the Problems] In the synchronization tracking circuit according to the present invention, when the state of the line deteriorates, the phase delay amount is automatically reduced to reduce the phase jitter.

[Operation] In the present invention, while the line condition is good, the phase delay is increased to keep the capture range wide, and when the line condition becomes poor, the phase delay is reduced to reduce the phase jitter. It becomes possible.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG. 2 denote the same or corresponding parts,
(4) is an error rate detection circuit, and (13) is a selector.

In the PN code generator (14) of FIG. ₁ , E ₁ (t), L ₁
A first combination of (t) and a _second combination of E ₂ (t) and L ₂ (t) are generated. For example, it is assumed that the phase delay is τ in the first combination and the phase delay is τ / 2 in the second combination.

The output of the Viterbi decoder (3) is an error rate detection circuit (4)
Is used to detect the bit error rate. When this bit error rate is less than a predetermined value, E (t), L (t) is E ₁ (t), L
₁ (t) is output, and when the code error rate becomes equal to or more than the predetermined value, the selector (13) is output by the error rate detection circuit (4) so that E ₂ (t) and L ₂ (t) are output. ). Therefore, when the line condition is good and the error rate is small, the capture range is kept large, and when the code error rate is large, switching is performed to reduce the phase jitter and reduce the code error.

FIG. 4 is a block diagram showing another embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 1 indicate the same or overall parts, and (16) denotes a C / N detector. When the C / N detector (16) detects that the C / N of the line is equal to or less than a predetermined value, E
₂ (t), the combination of L ₂ (t) is output.

[Effects of the Invention] As described above, according to the present invention, when the bit error rate is small, the capture range of the phase locked loop can be kept large in that state, and the phase jitter is reduced when the error rate is large. Thus, the error rate can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional circuit, FIG. 3 is an explanatory diagram for explaining the operation of the synchronization tracking circuit shown in FIG. 2, and FIG. FIG. 4 is a block diagram showing another embodiment of the present invention. (4) ... Error rate detection circuit, (5), (8) ... Multipliers, (6), (9) ... BPF, (7),
(10) ... envelope detector, (11) ... adder,
(12)… Loop filter, (13)… Selector, (1
4) PN code generator, (15) VCO, (16) C / N
Detector. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] An PN code generator for generating a PN code by using an output frequency of a voltage controlled oscillator as a clock;
A late code obtained by delaying the early code for a predetermined time is output, an output obtained by envelope-detecting the product of the input signal and the early code through a band-pass filter, and the input signal and a late cod
In a synchronous tracking circuit that feedback-controls the oscillation frequency of the voltage-controlled oscillator as an error signal with the difference between the product of e and the output obtained by envelope detection through a band-pass filter, the PN code generator includes an Early code and a Late code. A first combination in which the delay time between is a predetermined time;
A second delay in which the delay time between the early code and the late code is smaller than the delay time of the first combination.
Means for generating a combination of the above, if the bit error rate detected by the error rate detection circuit is equal to or greater than a predetermined value, or if the carrier-to-noise ratio detected by the carrier-to-noise ratio detector is equal to or less than a predetermined value, Means for switching the output of the PN code generator so as to output an early code and a late code of two combinations.