JP2728591B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a vector arithmetic processor and a cache memory or an external memory having a high-speed transfer mode, and more particularly to an optimum transfer according to the state of a data group to be transferred. The present invention relates to an information processing apparatus that automatically selects a mode.

[0002]

2. Description of the Related Art In a high-performance information processing system using a general-purpose processor, an external support circuit such as a dedicated data processing circuit or a dedicated processor may be added in order to improve the performance of the entire system.

In such a high-performance information processing system, since the data transfer speed greatly affects the performance of the system, an external cache memory or an external memory constituted by a DRAM in a high-speed transfer mode is connected to the high-speed transfer mode. Generally, data transfer is performed in a burst transfer mode (hereinafter, referred to as a burst mode).

[0004] The burst mode is one of block transfer systems, and is a data transfer mode on the premise that an external cache memory or an external memory composed of a nibble mode DRAM which is a high-speed transfer mode is connected to a processor or the like. This is a transfer method that is most effective when the data amount is large and continuous.

[0005]

However, when a vector operation processor is used as a processor for performing data processing in addition to a general-purpose processor, when vector data to be handled is not always continuous or when a data array that is not suitable for performing burst transfer is used. In such a case, if the transfer is performed in the burst mode, there is a problem that the efficiency of the bus access deteriorates and the performance of the system is affected.

An object of the present invention is to provide an information processing apparatus having a vector operation processor and an external cache memory connected thereto or an external memory having a high-speed transfer mode. The purpose is to make bus access.

[0007]

Means for Solving the Problems To solve the above problems,
For this purpose, the present invention provides a vector operation processor (1)
External memory (4) or cache with fast transfer mode
The vector operation, comprising one of the memories (2)
From the processor (1) to the external memory (4) or the key;
Transfer data to one of the cache memories (2)
Information processing apparatus, the vector operation processor
(1) Burst mode transfer based on the data
Or basic mode transfer.
Determining means (7) for determining
The transfer mode of the data is set based on the determination result.
Either the last mode transfer or the basic mode transfer
Control means (6) for switching to either
The determining means (7) determines that the data is continuous in the positive direction.
Continuous data judgment circuit (8) for judging whether or not
And the address of the data is the external memory (4) or
Location of the transfer destination memory area in the cache memory (2)
Address judgment to judge whether starting from a fixed address
A circuit (9) and the number of the data is stored in the destination memory area.
Data to determine whether the number is the specified number of data in the area
A number determination circuit (10); and the control means (6).
The continuous data determination circuit (8), the address determination
In the circuit (9) and the data number determination circuit (10).
The transfer mode based on the respective judgment results.
Either the last mode transfer or the basic mode transfer
It is configured to switch to one or the other.

[0008]

[0009]

According to the present invention, a vector operation processor is provided.
The determination means (7) included in (1) is the data to be transferred.
Perform burst mode transfer or basic
It is determined whether to perform mode transfer. And the system
The control circuit (6) is based on the determination result of the determination means (7).
The data transfer mode to burst mode transfer or
Switch to one of the basic mode transfers. this
At this time, the continuous data determination time included in the determination means (7)
Road (8) determines whether data is continuous in the forward direction.
Set. On the other hand, the address determination included in the determination means (7)
The circuit (9) stores the data address in the external memory (4) or
Indicates a predetermined destination memory area in the cache memory (2).
It is determined whether or not it starts from the address. Furthermore, judgment
The data number determination circuit (10) included in the stage (7)
Data is the number of specified data in the transfer destination memory area.
It is determined whether or not there is. Then, the control means (6)
Connection data determination circuit (8), address determination circuit (9), and
For each determination result in the data number determination circuit (10),
Based on the transfer mode, the burst mode transfer or basic mode
Switch to one of code transfer. Therefore,
Data that is not necessarily suitable for burst mode transfer
From a vector operation processor (1) that may handle
When transferring data, select data suitable for burst mode transfer.
Data only in burst mode and
For data that is not suitable for
Since the transfer can be performed by using the bus , efficient bus access can be achieved as a whole .

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. Figure 1 (a) (b) showing the overall configuration of a data processing apparatus which is an embodiment of the present invention.

In these figures, reference numeral 1 denotes a vector arithmetic processor having a built-in burst condition determination circuit to be described later;
Is an external cache memory, 3 is an external memory (main storage device), and 4 is an external memory (main storage device) composed of a DRAM having a nibble mode of a high-speed data transfer mode.

The present invention, as shown in FIG.
An information processing apparatus having a configuration in which an external memory 3 is connected to a vector operation processor 1 via an external cache memory 2 or, as shown in FIG. This is applied to an information processing apparatus having a connected configuration.

FIG. 2 shows the internal configuration of the vector operation processor 1 in detail. In FIG. 2, reference numeral 5 denotes an operation unit of the vector operation processor, which includes a multiplier, an adder, and the like. Reference numeral 6 denotes a control unit that controls the arithmetic unit 5 and the entire processor. Reference numeral 7 denotes a burst condition judging circuit which is a main part of the present invention. The burst condition judging circuit 7 judges, based on various information on transfer data transmitted from the control unit 6 before data transfer, whether or not the data transfer in the burst mode is optimal. Is what you do.

FIG. 3 shows the internal configuration of the burst condition determination circuit 7 in detail. As shown in FIG. 3, the burst condition determination circuit 7 includes three determination circuits that perform predetermined determination operations based on information on transfer data from the control unit 6, that is, a continuous data determination circuit 8 and an address. A judgment circuit 9, a data number judgment circuit 10, and an AND circuit 11 for judging that the condition is satisfied in all of the judgment circuits 8, 9, and 10 are built in.

The conditions for optimal data transfer in the burst mode include the following three conditions. The continuous data determination circuit 8, the address determination circuit 9, and the data number determination circuit 10 perform these three determinations, respectively. This is to confirm that the condition is satisfied.

(1) Judgment of continuous data This is a case where data arranged continuously on the memory is loaded and a case where data is continuously stored on the memory. At this time, the address increment of the data (the previous address) Must be increased in the positive direction. The above-described continuous data determination circuit 8 determines that the data is continuous and the increment of the address is in the positive direction.

(2) Address determination This is based on the assumption that the address of the continuous data array must start from the beginning of one line of the external cache memory. Then, the above-described address determination circuit 9 determines that the operation starts from the head address.

(3) Determination of Number of Data This is based on the assumption that the number of data to be continuously loaded or stored must exist for at least one line of the cache memory. The size of one line, which is an access unit of the cache memory, is the size of data width × 4, and the above-described data number determination circuit 10 determines that the data of this size (depending on the data size) exists. It is to judge.

As described above, all of the above three conditions must be satisfied for data transfer in the burst mode. In the present invention, the continuous data determination circuit 8
The address judging circuit 9 and the data number judging circuit 10 judge whether these conditions are satisfied, and execute data transfer in the burst mode when the conditions are satisfied, and execute data transfer in the basic mode when the conditions are not satisfied. It is.

That is, as shown in FIG. 4, when the three conditions (steps 100 to 102) are satisfied and the conditions are satisfied, the block access request signal BL of the external terminal is set.
# Is asserted (step 103) to notify the outside that the transfer in the burst mode is possible. As a result, a burst access response signal BURST # is returned. When the signal is detected (step 104), data transfer in the burst mode is performed (step 105).
However, when the condition is not satisfied (when any one of steps 100 to 102 is NO), or when the burst access response signal BURST # is not detected (step 104, NO), data transfer in the basic mode is performed (step 104). Step 106).

Therefore, according to the present invention, even when a vector operation processor is used as a processor for performing data processing in addition to a general-purpose processor, the present invention is suitable for a case where vector data to be handled is not always continuous or for performing burst transfer. If the data array is not the same, the data transfer is performed in the basic mode instead of the burst mode. As a result, the adverse effect on the system performance due to the reduced bus access efficiency is avoided, and the optimal data transfer is always performed. It will be.

[0022]

As described above, according to the present invention,
Data that is not always suitable for burst mode transfer
Vector processor (1) that may handle data
Suitable for burst mode transfer when transferring data from
While extracting only data and transferring it in burst mode,
Basic mode is used for data that is not suitable for burst mode transfer.
Since the transfer can be performed by the code, efficient bus access as a whole becomes possible.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a system configuration of an information processing apparatus according to the present invention.

FIG. 2 is a schematic block diagram illustrating an internal configuration of a vector operation processor according to the present invention.

FIG. 3 is a schematic block diagram showing an internal configuration of a burst condition determination circuit which is a main part of the present invention.

FIG. 4 is a flowchart for determining a data transfer mode according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Vector arithmetic processor 2 ... External cache memory 3 ... External memory 4 ... High-speed mode DRAM 5 ... Operation part 6 ... Control part 7 ... Burst condition judgment circuit 8 ... Continuous data judgment circuit 9 ... Address judgment circuit 10 ... Data number judgment Circuit 11 ... AND circuit

Claims (1)

(57) [Claims] A vector operation processor (1) and a high-speed
An external memory (4) having a transfer mode or a cache memory
And the above-mentioned vector operation program.
From the processor (1) to the external memory (4) or the
In the information processing apparatus for transferring data to one of the flash memories (2), the vector operation processor (1) performs burst mode transfer based on the data,
To determine whether to perform basic mode transfer
Means (7) , based on the determination result in the determination means (7),
The data transfer mode is the burst mode transfer or the
Control method to switch to one of basic mode transfer
(6), and the determining means (7) determines whether the data is continuous in the forward direction.
A continuous data determination circuit (8), wherein the address of the data is the external memory (4) or
A predetermined number of transfer destination memory areas in the cache memory (2)
Address determination circuit that determines whether or not to start from an address
(9) when the number of the data is a predetermined data in the transfer destination memory area;
Data number judging circuit to judge whether it is the number of data
(10), wherein the control means (6) is provided with the continuous data determination circuit.
(8) the address determination circuit (9) and the data
Based on each determination result in the number determination circuit (10)
The transfer mode is the burst mode transfer or the
An information processing device for switching to one of basic mode transfer .