JP2725359B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a configuration of an electrostatic protection circuit thereof.

[Prior Art] A conventional electrostatic protection circuit of this kind will be described with reference to FIG. FIG. 4 (a) is a cross-sectional view of a conventional device, and FIG.
FIG. 2B is an equivalent circuit diagram thereof.

In FIG. 4 (a), a P-type semiconductor substrate 18 is surrounded by a LOCOS oxide film 12 and a high-concentration P-type buried layer 13,
A bipolar transistor including a high-concentration N-type buried layer 14, a high-concentration N-type region 16 and a high-concentration P-type region 17 is formed. On the semiconductor substrate, the buried layer 14 is
The N-type region 16 is connected to the emitter electrode 7 via the polycrystalline silicon 15, and the P-type region 17 is connected to the base electrode 8. The collector electrode is connected to an input (or output, hereinafter the same) terminal 3 connected to an internal circuit to be protected, the emitter electrode 7 and the semiconductor substrate 18 are connected to a power supply line (for example, GND power supply line) 4 and Electrodes are hundreds of ohms ~
It is connected to a power supply line 4 via a resistor 2 of several tens of ohms. The equivalent circuit diagram is shown in FIG. 4 (b), where 1 is an NP including a buried layer 14, regions 16 and 17.
N transistor.

 Next, the operation of this circuit will be described.

First, a case where a positive voltage pulse is applied to the input terminal 3 with respect to the power supply line 4 will be described. The voltage of this pulse is NP
When the breakdown voltage exceeds the base-collector breakdown voltage (so-called BV _CBO ) of the N-transistor 1, a hole is formed in the high-concentration P-type region 17 forming the base from the high-concentration N-type buried layer 14 forming the collector. Is injected. When enough charge for this transistor to perform a transistor operation is stored in the high-concentration P-type region 17, the NPN transistor 1 operates as a transistor to inject electrons from the high-concentration N-type region 16 forming an emitter. Occurs and a current flows from the collector to the emitter. At this time, the voltage between the input terminal 3 and the power supply line 4 is changed from BV _CBO to the collector-emitter voltage of the NPN transistor 1 (so-called BV
_CBO ). The situation at this time is shown in FIG. Here, even if the resistor 2 is not provided, that is, even if the base is open, almost the same operation is performed.
Since the base potential of the NPN transistor 1 is fixed at the emitter potential, the circuit shown in the figure is superior in the sense of preventing unnecessary operation of the NPN transistor 1 at normal times.

Next, a case where a negative voltage pulse is applied to the power supply line 4 to the input terminal 3 will be described. As shown in FIG. 4A, since the N-type buried layer 14 of the transistor 1 is formed on the P-type semiconductor substrate 18, a parasitic diode (hereinafter referred to as a C-Sub diode) 5 is formed here. And
Then, the semiconductor substrate 18 is connected to a power supply line (GND line) and
Since the mold buried layer 14 is connected to the input terminal, the C-Sub diode 5 is eventually inserted as shown in FIG. 4 (b). Therefore, the C-Sub diode 5 is biased in the forward direction, and discharges the electric charge between the input terminal 3 and the power supply line 4.

[Problems to be Solved by the Invention] In the above-described conventional electrostatic protection circuit, when a negative voltage pulse is applied to the input terminal, a parasitic C-
I expect from Sub diode. However, when a negative pulse with a steep rising was applied, the evaluation result was obtained that this diode did not perform the bypass function, and thus the protection transistor was destroyed by a relatively low voltage pulse. . It is considered that such a result occurs for the following reasons. That is, generally, the parasitic C-Su
b Diodes have poor response and cannot immediately respond to steep voltage changes such as pulse voltages.
Although a forward voltage is applied to the parasitic C-Sub diode, a large current flows from the emitter of the NPN transistor to the collector, and the collector-emitter is destroyed (short-circuited).

In addition, an evaluation result was obtained that even when a positive pulse voltage was applied to the input terminal, the collector-emitter of the NPN transistor was destroyed (short-circuited). However, no internal circuit elements were destroyed at this time. That is, the above-described conventional electrostatic protection circuit is excellent in protection ability for the internal circuit element,
The electrostatic breakdown voltage of the electrostatic protection circuit itself is not sufficient. Therefore, the conventional integrated circuit device has a disadvantage that a sufficient electrostatic breakdown voltage cannot be obtained as a result.

[Means for Solving the Problems] In a semiconductor integrated circuit device according to the present invention, a first second conductivity type semiconductor region formed on a first conductivity type semiconductor substrate is used as a collector region, and the first second conductivity type semiconductor region is formed on the first second conductivity type semiconductor region. A first conductivity type diffusion layer formed in a surface region of a conductivity type semiconductor region as a base region, and a second conductivity type diffusion layer formed in a surface region of the first conductivity type diffusion layer , A bipolar transistor having an emitter region, a second second conductivity type semiconductor region formed on the first conductivity type semiconductor substrate, and a second second conductivity type semiconductor region formed in a surface region of the second second conductivity type semiconductor region. And a diode having two first conductivity type diffusion layers, the first second conductivity type semiconductor region and the second second conductivity type semiconductor region.
A conductive type semiconductor region is commonly connected to an input or output terminal; the second conductive type diffusion layer and the second first conductive type diffusion layer are commonly connected to a power supply line; The semiconductor device is characterized in that the conductive type diffusion layer is opened or connected to the power supply line via a resistor, and the collector extraction region and the base region of the bipolar transistor are separated by an isolation region.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1A is a sectional view showing a reference example on which the present invention is premised, and FIG. 1B is an equivalent circuit diagram thereof. The same reference numerals are given to portions common to the conventional example. In this embodiment, as shown in FIG.
A transistor having an N-type buried layer 14, an N-type region 16 and a P-type region 17 on the top 18 is separated by a LOCOS oxide film 12 and a P-type buried layer 13 to form a high-concentration N-type buried layer 14a and a high-concentration P-type region. Tiode with 17a (hereinafter C
-B diode). This CB
The N-type buried layer 14a and the P-type region 17a of the diode are formed simultaneously with the N-type buried layer 14 to the P-type region 17 of the transistor, respectively. The CB diode is provided with an anode electrode 10 and a cathode electrode 11, and these electrodes are connected to the power supply line 4 and the input terminal 3, respectively. 6 as shown in FIG. 1 (b).

Next, the operation of the electrostatic protection circuit according to the present embodiment will be described. When a positive voltage pulse is applied to the input terminal 3 with respect to the power supply line 4, the NPN transistor 1 performs a bipolar operation to bypass the current to the power supply line 4. The operation is the same. Next, when a negative voltage pulse is applied to the input terminal 3 with respect to the power supply line 4, the parasitic C-Sub diode 5 of the NPN transistor 1
Since the responsive CB diode 6 quickly bypasses the current by the forward operation, the NPN transistor 1 is not burdened and the NPN transistor 1 is protected from destruction.

The present inventor has conducted an experiment with a BiCMOS logic integrated circuit device. As a result, under the condition that the input capacitor is 200 pF and the series resistance is 0Ω, the input terminal 3 is connected to the power supply line 4 in the sample before the CB diode 6 is added. The electrostatic withstand voltage when a negative voltage pulse was applied was 225 V, and the electrostatic withstand voltage when a positive voltage pulse was applied was 300 V, whereas the sample with the CB diode 6 added was 450 V. And showed a significant improvement of 150 to 225V. Even when a positive voltage pulse was applied to the power supply line 4 to the input terminal 3, the improvement in the electrostatic breakdown voltage was observed because the current path due to the reverse breakdown of the CB diode 6 was caused by the load of the NPN transistor 1. It is presumed that this was due to lightening.

Next, an embodiment of the present invention will be described with reference to FIG. The difference between this embodiment and the embodiment shown in FIG.
The point is that the LOCOS oxide film 12 separates the collector extraction region below the collector electrode 9 from the high-concentration P-type region 17.

Investigation of the destruction example of the above-mentioned reference example device revealed that the place where the electrostatic breakdown occurred was concentrated on the silicon substrate surface between the collector electrode 9 and the emitter electrode 7 of the transistor 1. This accident is a phenomenon in which an alloy spike (eutectic between aluminum and silicon, which is an electrode material) occurs between the collector electrode 9 and the emitter electrode 7, which is caused by the surface of silicon (the interface between silicon and an insulating film). It is considered that current concentration due to electrolytic concentration easily occurs due to impurities such as crystal defects and dust. In the embodiment shown in FIG. 2, the LOCOS oxide film is used to separate the collector extraction region of the NPN transistor 1 from the high-concentration P-type region 17 serving as a base in order to avoid electrostatic breakdown due to such an effect. I have. With such a structure, a surface portion where electric field concentration is likely to occur can be eliminated, and the electrostatic withstand voltage can be further improved.

By the way, in general, separating the collector and the base of the NPN transistor with the LOCOS oxide film may cause undesired results such as an increase in the element area and an increase in the collector resistance. Even if there is an NPN transistor used for the internal circuit,
There is no need to separate the bases with a Locos oxide film.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.
This is an example in which the present invention is applied to a semiconductor integrated circuit device in which TTL level and ECL level input circuits and output circuits are mixed. In this embodiment, a first power supply line 4a and a third power supply line having a lower potential than the first power supply line 4a are used. And two power lines 4b, and C
The anode of the -B diode 6, the emitter of the NPN transistor 1, and one end of the resistor 2 are connected to the first power supply line 4a, and the anode of the C-Sub diode 5 is connected to the second power supply line 4b. The other points are the same as the embodiment of FIG. Thus, the C-Sub diode is
CB diode 6
Is indispensable for bypassing the current from the first power supply line 4a to the input terminal 3.

[Effects of the Invention] As described above, the present invention provides an electrostatic protection circuit in a circuit using a conventionally known NPN transistor, between the emitter and collector of the NPN transistor, the same as the NPN transistor. C formed using the process
According to the present invention, a bypass circuit with good responsiveness can be given to a negative pulse, and a partial current is applied to a positive pulse. Can be bypassed by the diode. Therefore, according to the present invention, the NP for electrostatic protection
It is possible to prevent electrostatic breakdown of the N-transistor itself, and as a result, it is possible to realize a semiconductor integrated circuit device having a high electrostatic withstand voltage. According to the embodiment in which the collector extraction region and the base region of the NPN transistor are separated by the separation region, the concentration of the electric field on the substrate surface between the collector electrode and the emitter electrode, which is apt to cause electrostatic breakdown, is reduced to reduce the breakdown voltage. It can be further improved. Also, according to the embodiment in which the P-type semiconductor substrate is connected to the second power supply, the TTL level and E
A highly reliable protection circuit can be realized for a circuit using two power supplies, such as a semiconductor integrated circuit device in which a CL level circuit is mounted.

[Brief description of the drawings]

FIG. 1A is a sectional view of a reference example on which the present invention is premised, FIG. 1B is an equivalent circuit diagram thereof, FIG. 2 is a sectional view showing one embodiment of the present invention, FIG. 3 is a circuit diagram showing another embodiment of the present invention, and FIG. 4 (a) is a sectional view of a conventional example.
FIG. 4 (b) is an equivalent circuit diagram, and FIG. 5 is an explanatory diagram of the operation of the circuit shown in FIG. 3 ... input (or output) terminal, 4 ... power line (GND)
4a... First power supply line (GND line), 4b... Second power supply line, 5... C-Sub diode, 6... CB diode, 7... Emitter electrode, 8. Base electrode, 9 ...
Collector electrode 10 Anode electrode 11 Cathode electrode 12 Locos oxide film 13 High-concentration P-type buried layer
14, 14a: high-concentration N-type buried layer, 15: polycrystalline silicon, 16: high-concentration N-type region, 17, 17a ... high-concentration P-type region, 18: P-type semiconductor substrate.

Claims (2)

(57) [Claims] A first conductive type semiconductor substrate formed on a first conductive type semiconductor substrate;
The second conductive type semiconductor region as a collector region, the first first conductive type diffusion layer formed in the surface region of the first second conductive type semiconductor region as a base region, A bipolar transistor having a second conductivity type diffusion layer formed in a surface region of the conductivity type diffusion layer as an emitter region; a second second conductivity type semiconductor region formed on the first conductivity type semiconductor substrate; A diode having a second first-conductivity-type diffusion layer formed in the surface region of the second second-conductivity-type semiconductor region; and a first second-conductivity-type semiconductor region. And the second second conductivity type semiconductor region are commonly connected to an input or output terminal, and the second conductivity type diffusion layer and the second first conductivity type diffusion layer are commonly connected to a power supply line. The first first conductivity type diffusion layer is opened or resisted; Is connected to the power line through the semiconductor integrated circuit device between the base region of the bipolar transistor and the collector lead-out region of the bipolar transistor is characterized in that it is separated by an isolation region. A first conductive type semiconductor substrate formed on the first conductive type semiconductor substrate;
The second conductive type semiconductor region as a collector region, the first first conductive type diffusion layer formed in the surface region of the first second conductive type semiconductor region as a base region, A bipolar transistor having a second conductivity type diffusion layer formed in a surface region of the conductivity type diffusion layer as an emitter region; a second second conductivity type semiconductor region formed on the first conductivity type semiconductor substrate; A diode having a second first-conductivity-type diffusion layer formed in the surface region of the second second-conductivity-type semiconductor region; and a first second-conductivity-type semiconductor region. And the second second conductivity type semiconductor region are commonly connected to an input or output terminal, and the second conductivity type diffusion layer and the second first conductivity type diffusion layer are commonly connected to a first power supply line. And the first first conductivity type diffusion layer is opened or Through a resistor connected to said first power supply line, wherein the first conductivity type semiconductor substrate is a semiconductor integrated circuit device characterized by being connected to the second power supply line.