JP2720677B2 - MIS transistor and method of forming the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS transistor, and more particularly to a source / drain structure thereof and a method of forming the same.

[0002]

2. Description of the Related Art In recent years, as ICs have become more highly integrated, the cell size has been reduced, the gate length has been reduced, and it has become difficult to suppress the short-channel effect and punch-through. In order to solve this problem, as a method of increasing the channel length without increasing the element area, a structure in which the source / drain layer 21 is raised on the silicon substrate 22 as shown in FIG. ing. In the figure, 23 is a gate polysilicon, 24
Is an insulating film. In making such a structure, using selective epitaxial growth of silicon reduces the number of steps,
This is advantageous in device fabrication.

[0003]

However, as shown in FIG. 3B, usually, SiCl ₂ H ₂ or SiCl ₂ H ₂
And when a selective epitaxial growth using the HCl, facets 26 are formed, without close contact with SiO ₂ and the silicon epitaxial layer, it has a problem that the leakage current becomes extremely large.

[0004] An object of the present invention is to eliminate such a conventional drawback and to provide a structure and a structure necessary for forming a flat face / source / drain lift-up layer which is in close contact with a side wall portion of an insulating film and has no facets. It is to provide a forming method.

[0005]

In order to achieve the above object, a MIS transistor according to the present invention has an insulating film on a side wall of a gate electrode, and has a source / drain raised layer in contact with the insulating film. Wherein the insulating film protrudes in the shape of an eave toward the source / drain side.

A MIS transistor having an insulating film on a side wall of a gate electrode and having a source / drain lift-up layer in contact with the insulating film, wherein the insulating film protrudes in a reverse taper shape toward the source / drain. Is what it is.

In the method of forming a MIS transistor according to the present invention, the insulating film formed on the side wall of the gate electrode is projected to the source / drain side in an eaves-like manner, and a silane-based gas or a chlorosilane-based gas or a halogen or a halogen is used. The source / drain layer is selectively epitaxially grown under a pressure such that a gas phase reaction does not occur by irradiating the material to which hydrogen chloride has been added.

Further, an insulating film formed on the side wall of the gate electrode is projected to the source / drain side in a reverse taper shape, and irradiated with a silane-based gas or a chlorosilane-based gas or a gas obtained by adding halogen or hydrogen halide thereto. Then, the source / drain layers are selectively epitaxially grown under a pressure that does not cause a gas phase reaction.

[0009]

The principle of the present invention will be described. The inventor has
It has been found that when the side wall shape is an eaves shape, the side wall of the insulating film and the Si epitaxial layer are in close contact with each other. It is based on the following reasons. The growth of Si using disilane gas is H
The rate of growth is limited by the desorption. Near the side wall,
It is considered that the raw material gas is decomposed on the side wall, and the decomposed radicals promote the growth by extracting hydrogen.
Therefore, no epitaxial layer is formed on the side wall without forming a facet.

As shown in FIG. 1A, a silicon substrate 1
1 is patterned with an insulating film 12 and the disilane gas 13 reflected on the eave-shaped side wall of the substrate in which the side wall of the silicon opening is formed in an eaves shape is decomposed and hydrogen is extracted, and as shown in FIG. Thus, the raised silicon epitaxial growth layer 14 near the side wall is formed. In the vicinity of the insulating film, the growth is accelerated by the amount reflected by the side walls, and the eaves can be buried without any gaps, so that a silicon epitaxial layer without facets is formed as shown in FIG. 1C.

The second method of this formation is a method using an insulating film pattern having a reverse tapered shape as shown in FIG. 2 for the side wall. When the shape of the side wall is reverse tapered, the facet is not formed as described above, and an epitaxial layer in close contact with the side wall is formed. The principle is the same as in the previous method.Since the disilane gas is decomposed on the substrate and the decomposed radicals accelerate the growth by extracting hydrogen, radicals increase near the reverse tapered side wall, and the growth occurs. It is thought that the speed will be faster.

Further, the present inventor has found that an MIS transistor having an insulating film portion having an overhanging structure has a very small leakage current. It is based on the following reasons. As described above, in the eaves shape, the epitaxial layer and the insulating film side wall are in close contact with each other. If the epitaxial layer is formed as usual without adhesion, facets and the like are generated, and the leakage increases.

Further, the present inventor has found that when the insulating film portion is formed in a reverse tapered structure, the leak current is further reduced as compared with the case where the insulating film portion is formed in an eaves-like structure. It is based on the following reasons. In the case of the eaves type, the boundary between the insulating film side wall and the epitaxial layer is sharp and the electric field concentration is easy to occur. This is because it becomes difficult.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below. Here, base pressure 1 × 10 ^-9 Torr
, Using a vacuum apparatus equipped with a nozzle for supplying disilane gas.

The sample wafer has a thermal oxide film 20 on its surface.
A 6-inch n-type Si (100) substrate was used for a sample in which 00 angstrom (hereinafter referred to as Å) was formed and patterned to form a silicon opening.

After the RCA cleaning, the sample wafer was transported into a forming chamber and cleaned by heating at 800 ° C. for 10 minutes. The substrate temperature was lowered to 578 ° C. (temperature for epitaxial growth), and the substrate was irradiated with a disilane gas partial pressure of 1 × 10 ⁻³ Torr. SEM observation of the cross section at the time when the Si film thickness was grown to about 2000 ° showed that FIG.
SEM images similar to those shown in FIGS. 2 (b) and 2 (c) and FIGS. 2 (a), 2 (b) and 2 (c) were obtained, confirming the effects of the present invention. (A) is about 500Å, (b) is about 15
00 ° and (c) show the case where the growth is about 2000 °.

Next, the source / drain of the MIS transistor having a gate oxide film thickness of 60 ° and a channel length of 0.4 μm was formed by the above method. Impurities were also doped during irradiation with disilane gas. For comparison, measurements were made of a conventional facet formed using SiCl ₂ H ₂ and a normal MIS transistor having a source / drain formed by ion implantation into a substrate. FIG. 4 shows the electrical characteristics at that time.

As compared with the conventional method, the characteristics of the transistor formed by this method are good and the leakage current is small. This indicates that the source / drain layer is formed in close contact with the side wall. I have. In addition, the reverse tapered type has a smaller leakage current than the eave type side wall shape because of the absence of electric field concentration, indicating better transistor characteristics.

In this embodiment, disilane (Si
Although an example of using the _{2 H 6), SiH 4,} Si 3 H 8, S
iH ₂ Cl _2, may be SiCl _4, etc., and this Cl _2,
A halogen such as F ₂ or a hydrogen halide such as HCl or HF may be added.

Although the present embodiment is directed to a silicon wafer, the method of the present invention employs an SOS (Silicon on Sapphire) substrate having silicon on its surface or, more generally, an SOI (Silicon on I).
Of course, the present invention can be applied to an nsulator substrate.

[0021]

As described above in detail, according to the present invention, a flat, side wall without facets can be obtained by forming the side wall portion into an eaves shape or a reverse taper shape and performing selective epitaxial growth using a silane-based gas as a source gas. The raised source / drain layer can be formed in close contact with the portion.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C are diagrams showing an epitaxial growth process according to a first embodiment of the present invention.

FIGS. 2A, 2B, and 2C are diagrams showing an epitaxial growth process according to a second embodiment of the present invention.

FIG. 3A is a conceptual diagram of a conventional transistor having a source and a drain, and FIG. 3B is a diagram showing the problem.

FIG. 4 is a diagram showing leakage current characteristics of a transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Silicon substrate 12 Insulating film 13 Disilane reflecting on the side wall 14 Grown silicon layer

Claims (4)

(57) [Claims] An MI having an insulating film on a side wall of a gate electrode and having a source / drain lift-up layer in contact with the insulating film.
An S transistor, wherein the insulating film protrudes in the shape of an eave toward the source / drain side. 2. An MI having an insulating film on a side wall of a gate electrode and having a source / drain lift-up layer in contact with the insulating film.
An S transistor, wherein the insulating film protrudes in a reverse taper shape toward the source / drain side. 3. An insulating film formed on the side wall of the gate electrode is projected to the source / drain side in an eaves-like manner, and irradiated with a silane-based gas or a chlorosilane-based gas or a gas obtained by adding halogen or hydrogen halide thereto. A method of forming a MIS transistor, wherein a source / drain layer is selectively epitaxially grown under a pressure at which a gas phase reaction does not occur. 4. An insulating film formed on the side wall of the gate electrode is projected in a reverse taper shape toward the source / drain, and irradiated with a silane-based gas or a chlorosilane-based gas or a gas obtained by adding halogen or hydrogen halide thereto. A source / drain layer is selectively epitaxially grown under a pressure at which a gas phase reaction does not occur.
A method for forming an S transistor.