JP2716342B2 - Chip type multilayer ceramic capacitor - Google Patents

Chip type multilayer ceramic capacitor

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Publication number
JP2716342B2
JP2716342B2 JP5155954A JP15595493A JP2716342B2 JP 2716342 B2 JP2716342 B2 JP 2716342B2 JP 5155954 A JP5155954 A JP 5155954A JP 15595493 A JP15595493 A JP 15595493A JP 2716342 B2 JP2716342 B2 JP 2716342B2
Authority
JP
Japan
Prior art keywords
multilayer ceramic
ceramic capacitor
chip
type multilayer
thin plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5155954A
Other languages
Japanese (ja)
Other versions
JPH0737747A (en
Inventor
知秀 伊達
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5155954A priority Critical patent/JP2716342B2/en
Publication of JPH0737747A publication Critical patent/JPH0737747A/en
Application granted granted Critical
Publication of JP2716342B2 publication Critical patent/JP2716342B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はチップ型積層セラミック
コンデンサに関し、特にクラック防止構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type multilayer ceramic capacitor, and more particularly to a structure for preventing cracks.

【0002】[0002]

【従来の技術】図4(a)に示すように、従来のチップ
型積層セラミックコンデンサは、導電性の内部電極を被
着形成した誘電体シートを内部電極取り出し部が相対向
するように複数枚交互に積層しその上下に保護層となる
誘電体シートを積層して一体化した後、得られた積層セ
ラミック素子1の相対向する内部電極2の取り出し面に
外部電極3を設けた構造となっていた。
2. Description of the Related Art As shown in FIG. 4 (a), a conventional chip-type multilayer ceramic capacitor comprises a plurality of dielectric sheets having conductive internal electrodes formed thereon such that internal electrode extraction portions are opposed to each other. After alternately laminating and laminating dielectric sheets to be protective layers on the upper and lower sides of the laminated ceramic element and integrating them, an external electrode 3 is provided on a surface of the obtained multilayer ceramic element 1 from which internal electrodes 2 facing each other are taken out. I was

【0003】また、実装時のストレス緩和のため上記の
チップ型積層セラミックコンデンサの外部電極を形成し
た面に金属製のキャップ状の部材を被覆した図4(b)
に示すような金属キャップ付きチップ型積層セラミック
コンデンサや特開平3−136308号公報の様に導電
性の内部電極を被着形成した誘電体シートを内部電極取
り出し部が相対向するよう複数枚交互に積層し、さらに
その上下に保護層となる誘電体シートを積層して一体化
した積層セラミック素子の外側に熱膨張係数の違う層を
設けその積層セラミック素子を一体焼成するチップ型積
層セラミックコンデンサが提案されていた。
Further, in order to reduce stress during mounting, the surface of the above-mentioned chip-type multilayer ceramic capacitor on which external electrodes are formed is covered with a metal cap-shaped member as shown in FIG.
A plurality of chip-type multilayer ceramic capacitors with metal caps and a dielectric sheet having conductive internal electrodes formed thereon as shown in JP-A-3-136308 are alternately arranged such that internal electrode extraction portions face each other. A chip-type multilayer ceramic capacitor is proposed in which a layer having a different coefficient of thermal expansion is provided outside of a laminated ceramic element in which a dielectric sheet serving as a protective layer is laminated above and below the laminated ceramic element, and the laminated ceramic element is integrally fired. It had been.

【0004】[0004]

【発明が解決しようとする課題】この従来のチップ型積
層セラミックコンデンサは、実装によって基板に固定す
る時あるいは固定された状態で急激な温度変化を受ける
と、基板とセラミック材料の熱膨張率の違いによって外
部電極と積層セラミック素子の界面近傍で熱応力が発生
するが、セラミック材料は金属材料と違って弾性等によ
る応力の緩和がほとんどなく、応力集中に伴う脆性破壊
を起こしやすいことから、この熱応力が外部電極と積層
セラミック素子界面近傍で集中し臨界破壊応力を超えた
ときにクラックが生じその絶縁抵抗が劣下するという問
題があった。
The conventional chip-type multilayer ceramic capacitor has a difference in the coefficient of thermal expansion between the substrate and the ceramic material when it is fixed to the substrate by mounting or when subjected to a rapid temperature change while being fixed. This causes thermal stress near the interface between the external electrode and the multilayer ceramic element.However, unlike a metal material, a ceramic material hardly relieves stress due to elasticity and the like, and tends to cause brittle fracture due to stress concentration. When the stress is concentrated near the interface between the external electrode and the multilayer ceramic element and exceeds the critical fracture stress, cracks occur and the insulation resistance is deteriorated.

【0005】また、従来の金属キャップ付きチップ型積
層セラミックコンデンサは、金属キャップを付ける作業
が自動化されにくくまた金属キャップ自体がコスト的に
高いという問題がある。また特開平3−136308号
公報の様な導電性の内部電極を被着形成した誘電体シー
トを内部電極取り出し部が相対向するよう複数枚交互に
積層し、さらにその上下に保護層となる誘電体シートを
積層して一体化した積層セラミック素子の外側に熱膨張
係数の違う層を設けその積層セラミック素子を一体焼成
するチップ型積層セラミックコンデンサにおいては熱膨
張係数の異なる異種のセラミック材料を一体焼成するの
でその焼成時にデラミネーションとよばれる層剥離が発
生し易い。また熱膨張係数を合わせた積層構造により上
述の従来のチップ型積層セラミックコンデンサより臨界
破壊応力が高くなるが一体焼成しているので臨界破壊応
力を越えればクラックが生じその絶縁抵抗が劣下すると
いう問題があった。
Further, the conventional chip-type multilayer ceramic capacitor with a metal cap has a problem that the operation of attaching the metal cap is difficult to be automated and the metal cap itself is expensive. Also, a plurality of dielectric sheets on which conductive internal electrodes are adhered and formed as disclosed in JP-A-3-136308 are alternately laminated such that the internal electrode take-out portions are opposed to each other. In a chip-type multilayer ceramic capacitor in which layers with different coefficients of thermal expansion are provided outside the multilayer ceramic element obtained by laminating body sheets and integrated, the different ceramic materials with different coefficients of thermal expansion are integrally fired. Therefore, delamination called delamination is likely to occur during the firing. In addition, the laminated structure with the same coefficient of thermal expansion makes the critical fracture stress higher than that of the above-mentioned conventional chip-type multilayer ceramic capacitors, but since it is integrally fired, cracks will occur if the critical fracture stress is exceeded, and the insulation resistance will be inferior. There was a problem.

【0006】[0006]

【課題を解決するための手段】本発明のチップ型積層セ
ラミックコンデンサは、導電性の内部電極を被着形成し
た誘電体シートを内部電極取り出し部が相対向するよう
複数枚交互に積層し、さらにその上下に保護層となる誘
電体シートを積層して一体化した積層セラミック素子の
相対向する内部電極取り出し面に外部電極を設けてなる
チップ型積層セラミックコンデンサにおいて、すくなく
ともその実装面側に薄板が重ね保持されていることを特
徴とした構造を有する。
According to the present invention, there is provided a chip-type multilayer ceramic capacitor in which a plurality of dielectric sheets having conductive internal electrodes formed thereon are alternately laminated such that internal electrode extraction portions face each other. In a chip-type multilayer ceramic capacitor in which external electrodes are provided on opposing internal electrode extraction surfaces of a laminated ceramic element in which a dielectric sheet serving as a protective layer is laminated and integrated on the top and bottom, at least a thin plate is mounted on the mounting surface side It has a structure characterized by being stacked and held.

【0007】その重ね保護手段としては上記を外部電極
の一部を共用して保持することや、接着剤によって保持
する構造が好ましい。
[0007] As the lap protection means, it is preferable to use the above-mentioned structure in which a part of the external electrode is shared and held, or the structure is held by an adhesive.

【0008】[0008]

【実施例】次に本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0009】図1は、本発明の一実施例によるチップ型
積層セラミックコンデンサの斜視図である。図2は図1
の断面図である。
FIG. 1 is a perspective view of a chip type multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 shows FIG.
FIG.

【0010】以下に、製造方法を説明する。Hereinafter, a manufacturing method will be described.

【0011】化学式ABO3(A,Bは金属元素、Oは
酸素)で表わされ、結晶構造がペロブスカイト構造を持
つ誘電体セラミック粉末と有機バインダーを混合しスラ
リー状にしたものをテープキャスト法にて成膜し乾燥さ
せた誘電体シート上に、銀・パラジウムからなる内部電
極2を形成しその取り出し部が相対向するように積層す
る。さらに、その上下に保護層となる誘電体シートを積
層し一体化する。そして、熱圧着・脱バインダーを行っ
た後、焼結することで積層セラミック素子1を得る。次
に、上記誘電体セラミックと同じセラミック材料等の耐
熱性のある薄板9をその下面または両面に配設し、銀を
主体とする外部電極3を内部電極2取り出し面に形成し
てチップ型積層セラミックコンデンサを得る。この様に
して得られたチップ型積層セラミックコンデンサは、従
来のチップ型積層セラミックコンデンサが図5のように
実装によって基板7に固定される時あるいは固定された
状態で急激な温度変化の影響を受けると、基板材料、外
部電極3に比べてセラミック材料の熱膨張率が一桁小さ
いことから外部電極3と積層セラミック素子間に生じる
熱応力により発生したクラック10を積層セラミック素
子1と薄板9の間隙11にそって逃がすことができる。
そして、クラック10を積層セラミック素子1の内部に
入れないことにより積層セラミックコンデンサの絶縁抵
抗劣下を防ぐことができる。
A slurry obtained by mixing a dielectric ceramic powder having a chemical formula of ABO3 (A and B are metal elements and O is oxygen) and having a perovskite crystal structure with an organic binder is formed by a tape casting method. An internal electrode 2 made of silver / palladium is formed on the formed and dried dielectric sheet, and the internal electrodes 2 are stacked so that their take-out portions face each other. Further, a dielectric sheet serving as a protective layer is laminated and integrated above and below. Then, after performing the thermocompression bonding and the binder removal, the multilayer ceramic element 1 is obtained by sintering. Next, a heat-resistant thin plate 9 made of the same ceramic material as the above-mentioned dielectric ceramic is disposed on the lower surface or both surfaces thereof, and the external electrodes 3 mainly composed of silver are formed on the surface from which the internal electrodes 2 are taken out. Obtain a ceramic capacitor. The chip-type multilayer ceramic capacitor thus obtained is affected by a sudden temperature change when or when the conventional chip-type multilayer ceramic capacitor is fixed to the substrate 7 by mounting as shown in FIG. In addition, since the coefficient of thermal expansion of the ceramic material is one order of magnitude smaller than that of the substrate material and the external electrode 3, a crack 10 generated by thermal stress generated between the external electrode 3 and the multilayer ceramic element causes a gap between the multilayer ceramic element 1 and the thin plate 9. 11 can be escaped.
By preventing the crack 10 from entering the inside of the multilayer ceramic element 1, the insulation resistance of the multilayer ceramic capacitor can be prevented from being deteriorated.

【0012】この効果は、特に、温度サイクル試験によ
って裏付けられる。表1は温度サイクル試験における寿
命特性を本実施例と従来のチップ型積層セラミックコン
デンサで比較したものである。試験条件(JIS C
5102に準ずる)を以下に示す。
This effect is supported, in particular, by temperature cycling tests. Table 1 shows a comparison of the life characteristics in the temperature cycle test between this embodiment and a conventional chip-type multilayer ceramic capacitor. Test conditions (JIS C
5102) is shown below.

【0013】 最低使用温度: −55℃ 最高使用温度: 125℃ サイクル数 : 1000回 不良判定基準:絶縁抵抗の初期値からの2桁以上の劣化 サンプル数 : 100個 基板材料 :アルミニウムMinimum operating temperature: −55 ° C. Maximum operating temperature: 125 ° C. Number of cycles: 1000 times Failure criterion: Degradation of two or more digits from the initial value of insulation resistance Number of samples: 100 Board material: Aluminum

【0014】[0014]

【表1】 [Table 1]

【0015】以上から明らかなように薄板をコンデンサ
本体に密着させないで、間隙11を設けたことにより温
度サイクルに対して優れた実力を持つチップ型積層セラ
ミックコンデンサが得られる。
As is clear from the above description, by providing the gap 11 without the thin plate being in close contact with the capacitor body, a chip-type multilayer ceramic capacitor having excellent ability with respect to the temperature cycle can be obtained.

【0016】図3に示す実施例2は本発明の第二実施例
であり、セラミックやプラスチック等の薄板9が接着剤
6において固定されている。本実施例のチップ型積層セ
ラミックコンデンサは温度サイクル試験での寿命特性で
実施例1と同等の値を示す。
Embodiment 2 shown in FIG. 3 is a second embodiment of the present invention, in which a thin plate 9 of ceramic, plastic or the like is fixed with an adhesive 6. The chip-type multilayer ceramic capacitor of the present embodiment shows the same value as that of the first embodiment in the life characteristics in the temperature cycle test.

【0017】[0017]

【発明の効果】以上説明したように本発明は、チップ型
積層セラミックコンデンサにおいて薄板を密着させずに
設けた構造を持っているので、従来のチップ型積層セラ
ミックコンデンサが実装によって基板に固定されると
き、あるいは固定された状態で急激な温度変化の影響を
受けると基板材料、外部電極に比べてセラミック材料の
熱膨張が一桁小さいことから外部電極と積層セラミック
素子間に生じる熱応力により発生するクラックによる絶
縁抵抗の劣下を、薄板を設けたことにより間隙11にク
ラックを逃がし絶縁抵抗の劣下を防ぐ効果がある。
As described above, the present invention has a structure in which thin plates are provided in a chip-type multilayer ceramic capacitor without being closely attached to each other, so that a conventional chip-type multilayer ceramic capacitor is fixed to a substrate by mounting. When it is affected by a sudden temperature change in the fixed state, the thermal expansion of the ceramic material is smaller than that of the substrate material and the external electrode by one order of magnitude, so that the thermal expansion occurs between the external electrode and the multilayer ceramic element. The thin plate is provided to prevent the deterioration of the insulation resistance due to the cracks and to prevent the cracks from escaping into the gap 11 to prevent the deterioration of the insulation resistance.

【0018】なお、薄板の材料としては積層セラミック
コンデンサ本体のセラミック材料と同一材料とすれば、
大きなコストアップが抑制される点で好ましい。クラッ
ク防止の意味では実装基板とコンデンサ本体との中間の
熱膨張率を有する材料が好ましい。
If the material of the thin plate is the same as the ceramic material of the multilayer ceramic capacitor body,
This is preferable in that a large cost increase is suppressed. From the viewpoint of preventing cracks, a material having a thermal expansion coefficient intermediate between that of the mounting substrate and the capacitor body is preferable.

【0019】また、本発明は、従来のチップ型積層セラ
ミックコンデンサ製造ラインをそのまま有効に利用でき
安価な積層セラミックコンデンサを供給できるという効
果を有する。
Further, the present invention has an effect that a conventional chip-type multilayer ceramic capacitor manufacturing line can be effectively used as it is and an inexpensive multilayer ceramic capacitor can be supplied.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例の斜視図である。FIG. 1 is a perspective view of one embodiment of the present invention.

【図2】図1の断面図である。FIG. 2 is a sectional view of FIG.

【図3】本発明の実施例2の断面図である。FIG. 3 is a sectional view of a second embodiment of the present invention.

【図4】(a)は従来のチップ型積層セラミックコンデ
ンサの断面図である。(b)は従来の金属キャップ付き
積層セラミックコンデンサの断面図である。
FIG. 4A is a cross-sectional view of a conventional chip-type multilayer ceramic capacitor. (B) is a sectional view of a conventional multilayer ceramic capacitor with a metal cap.

【図5】従来のチップ型積層セラミックコンデンサに基
板に実装したところの断面図である。
FIG. 5 is a cross-sectional view of a conventional chip-type multilayer ceramic capacitor mounted on a substrate.

【符号の説明】[Explanation of symbols]

1 積層セラミック素子 2 内部電極 3 外部電極 4 導電性接着剤 5 金属キャップ 6 接着剤 7 基板 8 はんだ 9 薄板 10 クラック 11 間隙 DESCRIPTION OF SYMBOLS 1 Multilayer ceramic element 2 Internal electrode 3 External electrode 4 Conductive adhesive 5 Metal cap 6 Adhesive 7 Substrate 8 Solder 9 Thin plate 10 Crack 11 Gap

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 導電性の内部電極を被着形成した誘電体
シートを内部電極取り出し部が相対向するよう複数枚交
互に積層し、さらにその上下に保護層となる誘電体シー
トを積層して一体化した積層セラミック素子の相対向す
る内部電極取り出し面に外部電極を設けてなるチップ型
積層セラミックコンデンサにおいて、すくなくともその
実装面側に薄板が密着せずに重ね保持されており、前記
薄板の厚みが前記積層セラミック素子の積層方向の厚み
より薄く、かつ前記薄板の長さが前記積層セラミック素
子の長さと同じであるとともに前記外部電極が前記薄板
の両端にも設けられていることを特徴とするチップ型積
層セラミックコンデンサ。
1. A plurality of dielectric sheets on which conductive internal electrodes are adhered and formed are alternately laminated such that internal electrode take-out portions are opposed to each other, and dielectric sheets serving as protective layers are laminated on and under the dielectric sheets. in facing the chip-type monolithic ceramic capacitor formed by providing an external electrode to the internal electrode extraction surface of the integral laminated ceramic device, are held stacked without contact sheet is to at least the mounting surface side, the
The thickness of the thin plate is the thickness of the multilayer ceramic element in the stacking direction.
The thinner plate and the length of the thin plate
The external electrode is the same as the length of the
The chip-type multilayer ceramic capacitor is also provided at both ends of the chip.
【請求項2】 前記チップ型積層セラミックコンデンサ
と前記薄板とが前記外部電極の一部によって保持されて
いる構造を有することを特徴とする請求項1記載のチッ
プ型積層セラミックコンデンサ。
2. The chip-type multilayer ceramic capacitor according to claim 1, wherein the chip-type multilayer ceramic capacitor and the thin plate have a structure held by a part of the external electrode.
【請求項3】 前記チップ型積層セラミックコンデンサ
と前記薄板とが接着剤によって保持されている構造を有
することを特徴とする請求項1記載のチップ型積層セラ
ミックコンデンサ。
3. The chip-type multilayer ceramic capacitor according to claim 1, wherein said chip-type multilayer ceramic capacitor and said thin plate have a structure held by an adhesive.
JP5155954A 1993-06-28 1993-06-28 Chip type multilayer ceramic capacitor Expired - Fee Related JP2716342B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5155954A JP2716342B2 (en) 1993-06-28 1993-06-28 Chip type multilayer ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5155954A JP2716342B2 (en) 1993-06-28 1993-06-28 Chip type multilayer ceramic capacitor

Publications (2)

Publication Number Publication Date
JPH0737747A JPH0737747A (en) 1995-02-07
JP2716342B2 true JP2716342B2 (en) 1998-02-18

Family

ID=15617166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5155954A Expired - Fee Related JP2716342B2 (en) 1993-06-28 1993-06-28 Chip type multilayer ceramic capacitor

Country Status (1)

Country Link
JP (1) JP2716342B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8576537B2 (en) 2008-10-17 2013-11-05 Kemet Electronics Corporation Capacitor comprising flex crack mitigation voids
CN107240496B (en) * 2010-12-28 2019-06-07 株式会社村田制作所 Electronic component
US9241408B2 (en) 2010-12-28 2016-01-19 Murata Manufacturing Co., Ltd. Electronic component
KR102004804B1 (en) * 2017-08-28 2019-07-29 삼성전기주식회사 Composite electronic component and board for mounting the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04302116A (en) * 1991-03-28 1992-10-26 Mitsubishi Materials Corp Chip type electronic parts with base stand
JP3090422U (en) * 2002-05-31 2002-12-13 味美 森下 Knee cover

Also Published As

Publication number Publication date
JPH0737747A (en) 1995-02-07

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