JP2716088B2 - Music signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial applications"   The present invention relates to a tone signal used in an electronic musical instrument or the like.
It relates to a generator. "Conventional technology"   In electronic musical instruments, how easy it is to reproduce the sound of natural musical instruments
A major issue is how to generate sound. In electronic musical instruments
Various methods are known as musical tone signal generation methods.
But among them, the instantaneous value of the musical sound waveform of a natural instrument
Sampling is performed sequentially and stored in the memory.
Reads the stored sampling data and generates a tone signal
PCM method produces musical tone closest to natural musical instrument
Can be excellent. In addition, about this PCM method
Is JP-A-52-121313 (Title of invention; electronic musical instrument)
Is disclosed. "Problems to be solved by the invention"   The tone waveform of a natural instrument is the pitch or sound of the same instrument.
It differs slightly depending on the area. For example, a piano place
In this case, although slightly, the tone waveform differs for each pitch (range).
Has become. Note that the waveform cycle differs for each pitch.
Of course, the shape of the waveform itself other than the period differs.
Has become. Therefore, the PCM method is truly natural
When trying to generate musical sounds close to the instrument,
The tone waveform is stored for each pitch (range) as necessary.
And as a result, the memory capacity becomes extremely large.
You. That is, in the tone signal generator of the PCM system
The biggest challenge is how to reduce the memory capacity.
You. Therefore, the applicant of the present invention first used the linear prediction method.
The characteristic feature of the “music signal
Generator "(Japanese Patent Application No. 59-212382).   This invention is a further improvement of the above-mentioned prior invention,
The goal is to reduce memory capacity even further.
It is an object of the present invention to provide a tone signal generator capable of performing the above. "Means to solve the problem"   According to the present invention, waveform data indicating each instantaneous value of a musical tone waveform is
Quadratic linear prediction operation and quantization by differential quantization
Compressed data obtained by this data compression
Storage means for storing the stored data and readout of the waveform.
Indicating means to be displayed, and
The data in the memory is read out and the second-order linear prediction operation is performed.
Decoding by a decoding operation based on
Signal means, and the wave decoded by the decoding means.
Generating tone signals based on shape data.
ing.   In this specification, "differential quantization method"
Is   DM (Delta Moduration)   ADM (Adaptive Delta Moduration)   DPCM (Differential Pulse Code Moduration)   ADPCM (Adaptive Differential Pulse Code Modurati
on) And the like. "Action"   According to the present invention, linear prediction operation and differential quantization
Data compression is performed by both means of quantization
U. This allows more data compression than conventional ones
It works. "Example"   Hereinafter, referring to the drawings, a tone signal according to an embodiment of the present invention will be described.
The signal generator will be described. Fig. 1 shows the tone signal generation
FIG. 2 is a block diagram for explaining a basic configuration of the apparatus, and FIG.
Shows the configuration of an electronic musical instrument using the same tone signal generator.
It is a lock figure. This electronic musical instrument is
Converts musical tones of natural musical instruments collected into digital data
This digital data is used for linear prediction and ADPCM
Compress using the compression method and store the compressed data in memory
To memorize. During music formation, this menu
Reads and decodes data in memory to form tone signals
You. [Basic configuration]   In FIG. 1, 1 is a data compression circuit, and 2 is a data pressure circuit.
In which data compressed by the compression circuit 1 is stored.
The memory 3 stores the data read from the data memory 2
This is a decoding circuit for decoding. In the data compression circuit 1,
4 is a microphone for picking up the sound of a natural instrument,
5 is a sampler of the output signal of the microphone 4 at a constant period.
And convert it to digital data (sampling data).
A / D (analog / digital) converter to convert, 6 is waveform
Processing device. This waveform processing device 6 includes an A / D converter 5
Output data is stored in the internal memory,
The standardized data is written to the memory 7. Where
Classification refers to the following processing. Fig. 3 shows one of the musical tone signals.
FIG. 3 is a diagram showing an example, and as shown in FIG.
Tack (rising part) ATC waveform whose amplitude gradually increases
Becomes Normalization means that this attack part ATC is
This is a process of converting into a waveform having the same amplitude as the PT amplitude. Concrete
Specifically, the amplitude envelope of the attack section ATC is exactly the opposite
The changing envelope data is stored in each of the attack section ATC
This is a process of multiplying the sampling data. Note that this
The processing is performed to improve the accuracy of the reproduction of the musical tone in the part where the amplitude is small.
It is performed. In addition, the sun output from the A / D converter 5
The number of bits of the pulling data is, for example, 24 bits.
Then, the waveform processing device 6 converts the sampling data
And then the minimum required number of bits
Data (for example, 12 bits) is stored in the waveform memory 7
Write as data Sn.   Next, 8 is a changeover switch, and 9 is a linear prediction coefficient operation circuit.
It is. When the waveform data Sn is stored in the waveform memory 7,
The changeover switch 8 is turned on to the linear prediction coefficient operation circuit 9 side.
Then, each waveform data Sn in the waveform memory 7 is sequentially read.
The linear prediction coefficient calculation circuit 9
Supplied to The linear prediction coefficient calculation circuit 9 receives the supplied
Based on the waveform data Sn, the N frames shown in FIG.
Calculate optimal linear prediction coefficients a1 and a2 for each of [0] to [N-1]
And writes it to the coefficient memory 10. These linear prediction coefficients a1, a
Various methods have been conventionally known as the calculation method of 2.
For example, the Durbin method using the autocorrelation function is available.
It is effective. Also, the coefficient a₁, A_TwoIs the full waveform data in the frame.
Data, or from some waveform data.
Good.   Next, 11 is a line meter that performs data compression based on the linear prediction method.
This is a prediction operation circuit.
12 is a subtraction circuit, 13 is an addition circuit, 14 is a predicted value calculation circuit
It is. Further, in the predicted value calculation circuit 14, 14a, 14a
b is each D-FF (delay flip-flop), 14c, 14d
Are the linear prediction coefficients a output from the coefficient memory 10 respectively.₁, A_Two
Is a multiplier having a multiplication coefficient, and 14e is an addition circuit.
The output of the adding circuit 14e is supplied to the subtracting circuit 12 as the predicted value ◇ Sn.
Be paid. 16 is the data by ADPCM quantization method.
ADPCM operation circuit that performs compression, and linear prediction operation circuit 11
12-bit data En output from the subtraction circuit 12
And converts it into a quantized difference code Cn. This amount
The child difference code Cn is stored in the data memory 2. Ma
The ADPCM operation circuit 16 also receives the quantized difference code Cn.
And the addition circuit of the linear prediction operation circuit 11
Output to 13. In this case, the decrypted data is the data En
Does not become exactly the same data, but includes an error dn. sand
That is, the decoded data is “En + dn”. Note that this
The ADPCM operation circuit 16 will be described later in detail.   Next, the operation of the linear prediction operation circuit 11 will be described. Person in charge
Each of the frames [0] to [N-1] in the number memory 10
Linear prediction coefficient a₁, A_TwoIs written,
The exchange switch 8 is turned on to the linear prediction operation circuit 11 side. Next
Of each frame [0], [1],.
The waveform data Sn is sequentially read and supplied to the subtraction circuit 12.
Also, the waveform data Sn of frame [0] is stored in the waveform memory.
7 is read from the coefficient memory 10,
Linear prediction coefficient a corresponding to₁, A_TwoBut the frame
The waveform data Sn of [1] is read from the waveform memory 7 and
The frame [1] in the coefficient memory 10
Linear prediction coefficient a₁, A_TwoBut ... each read from memory 10
And supplied to multipliers 14c and 14d. The waveform memory 7
Pulse and D-FF that determine the read timing of
The clock pulses supplied to 14a and 14b are the same. Decrease
The arithmetic circuit 12 subtracts the predicted value ◇ Sn from the waveform data Sn.
You. That is, Sn− ◇ Sn = En …… (1) And the data En obtained by this operation is
Output to ADPCM operation circuit 16. Here, the predicted value ◇ Sn is
Currently close to the waveform data Sn supplied to the subtraction circuit 12.
Value. (The reason will be described later.) As a result, the data
En is data whose value is much smaller than the waveform data Sn.
You. ADPCM operation circuit 16 quantizes data En by 4 bits
Convert to difference code Cn and output to data memory 2
Then, the data “En + dn” is output to the adding circuit 13. Addition times
The road 13 adds the data “En + dn” and the predicted value ◇ Sn.
Calculate. The result of this addition is En + dn + ◇ Sn = Sn + dn (2) Becomes That is, the output of the adder circuit 13 is substantially equal to the waveform data.
The value is equal to the value Sn. Therefore, within D-FF14a
Is almost equal to the waveform data Sn one clock pulse before.
Data is stored in the D-FF14b two clock pulses before.
Data Sn which is substantially equal to the data Sn of FIG. On the other hand, before
The previously described linear prediction coefficient calculation circuit 9 calculates the waveform data of the previous two
Sn_-2And the previous waveform data Sn_-1From Fig. 1
When the predicted value ◇ Sn is calculated by the circuit 14, the predicted value ◇
Coefficient a such that Sn is closest to the current data Sn₁, A_TwoIs calculated
And writes it to the coefficient memory 10. Therefore, this factor
a₁, A_TwoThe predicted value ◇ Sn calculated using
Very close values.   In this manner, the linear prediction operation circuit 11
Waveform data Sn output from 7 is converted to data En with a small value
ADPCM arithmetic circuit 1
Output to 6.   Next, the ADPCM operation circuit 16 will be described. First, 17
Is a subtraction circuit, and predictive data ◇ En_-1Reduced
The result of this subtraction is entered as data en (12 bits).
Output to coder 18. Encoder 18 converts data en to ADPC
Quantized by M method, 4-bit quantized difference code C
Output as n (the most significant bit is the sign bit). 19
Is based on the value of the quantized difference code Cn output from the encoder 18.
Thus, the adaptive quantization width data Δ
n (8 to 12 bits).
The processing operation is as follows.   First, the immediately preceding quantization width data is_-1Then the quantum
The quantization width control circuit 19 performs the following operation to obtain the next quantization width data.
Data Δn. Δn = Δn_-1・ K …… (3) K in this equation (3) is the immediately preceding quantized difference code
Cn_-1Is a coefficient determined by the value of. Figure 4 shows the quantity
FIG. 9 is a diagram showing the relationship between the value of the child difference code Cn and the coefficient k.
As shown in the figure, the absolute value of the quantized difference code Cn is large.
The value is set to increase as
ing. However, in this embodiment, as shown in FIG.
The value obtained by rounding off the second place below the decimal point of the value of coefficient k to k
Is stored in a predetermined memory in the quantization width control circuit 19.
I'm making it. Note that Cn = “1000” in FIG.
Corresponds to "0".   The encoder 18 has the quantization width as shown in FIG.
Difference PCM code when the value of data Δn is “1”
Calculate the relative value en / Δn of the code en
Convert to minute code Cn and output. In this case, en / Δn
The value can take any value between -1 and +1 but the quantization difference
Since the minute code Cn is 4 bits, the linear conversion operation is
I can't. Therefore, in this embodiment, en / Δn is
It is divided into sections as shown in FIG.
Conversion to the child difference code Cn is performed. example
For example, when en / Δn is not less than 1/2 and less than 5/8, the quantization difference code
Code Cn is set to “0100” and en / Δn is 0 or more and less than 1/8
In this case, the quantization difference code Cn is set to “0000”.   Next, 20 is the quantization difference code Cn and the adaptive quantization width Δn
Is a decoder that decodes data en based on This
In the case of, the decoded data contains an error dn based on quantization.
Therefore, the output data of the decoder 20 is “En + dn”
Becomes The specific decoding process of this decoder 20 is as follows.
It is as follows. Replace each bit of the quantized difference code Cn with (B_Three,
B_Two, B₁, B₀), The data “en + dn” is given by
Is calculated. en + dn =(1-2 ・ B ₃ )・ ｛Δn / 2 ・ B_Two+ (Δn / 4) · B₁+
(Δn / 8) ・ B₀+ Δn / 8｝ (4)   In the above equation (4), the term with an underline
Is the term that makes up the sign and the sign bit, B_ThreeIs “1”
Is negative when "0" and positive when "0". Also in braces
The closed term is the term corresponding to the absolute value, and the value of Δn
Is multiplied by the weight of each bit, and
The offset value Δn / 8 is added to create the absolute value of en + dn
It is.   The output data “en + dn” of the decoder 20 is added to an adder circuit.
Supplied to 21. The adding circuit 21 outputs the data “en + dn”
Forecast data ◇ En_-1And are added. The result of this addition is en + dn + ◇ En_-1= En + dn (5) Becomes That is, the output of the addition circuit 21 is almost equal to the data En.
Becomes The data output from the adding circuit 21
"En + dn" is one clock pulse by D-FF22.
Is delayed and the predicted data_-1To subtraction circuit 17
Is output.   Thus, the prediction data ◇ En_-1Is almost data En_-1Like
Therefore, the output data en of the subtraction circuit 17 is
Data En and Data En_-1(One timing before the clock pulse
This is data indicating the difference from the data En). As a result,
The value of data en is much smaller than the value of data En, and
Therefore, this data en is converted into 4 bits by the encoder 18.
Large (even 3 bits) code Cn
No child error occurs.   Next, the decoding circuit 3 will be described. This decoding circuit 3
Is the quantized difference code sequentially read from the data memory 2.
A circuit for decoding the code Cn into data “Sn + dn = Hn”,
It comprises an ADPCM decoding circuit 24 and a linear prediction decoding circuit 29.
ing. The ADPCM decoding circuit 24 performs the above-described quantization width control circuit.
A quantization width control circuit 25 having the same configuration as the
The decoder 26 having the same configuration, the adding circuit 27 and the D-FF 28
It is configured. Then, the data “en +
dn "is output, and the addition circuit 27
In the data ◇ En_-1Are added, and as a result of the addition,
That is, when the data “En + dn” is read into the D-FF28,
In addition, it is output to the linear prediction decoding circuit 29. The above
In the decoding process, the ADPCM operation circuit 16
Exactly the same process as decrypting data "En + dn" from code Cn
It is.   Next, the linear prediction decoding circuit 29 is added to the addition circuit 30 as described above.
Composed of the predicted value calculating circuit 14 and the arithmetic circuit 31 having the same configuration.
Have been. In this case, the multipliers 31c and 31d in the arithmetic circuit 31
Are the coefficients a read from the coefficient memory 10 respectively.₁, A_TwoBut
Supplied. In addition, data memory is provided to the D-FFs 31a and 31b.
Clock pulse that determines read timing of 2 is supplied
Is done. According to the linear prediction decoding circuit 29,
The output data of the arithmetic circuit 31 is the predicted value ◇ Sn described above,
Therefore, the output data of the adding circuit 30 is En + dn + ◇ Sn
= Sn + dn = Hn (6) Becomes   Then, the decoded data Hn is stored in D / A (digital / analog).
Log) converted to obtain a tone signal.   The above is the configuration of the tone signal generating device according to this embodiment.
You. In the above circuit, the error dn based on the quantization is calculated by the addition circuit 2
It is included in each output data of 1,14e.
Therefore, the prediction data ◇ En which is the feedback data
_-1, Sn also includes the error dn. That is,
The above circuit is of the error feedback type and therefore
Therefore, no error is accumulated in the decoded data Hn. Ma
In addition, the linear prediction operation circuit 11 and the linear prediction decoding circuit 29, ADPCM
The number of input / output bits of the arithmetic circuit 16 and ADPCM decoding circuit 24 and
Finite word length data
It is possible to prevent the occurrence of an error caused by the calculation.   If extremely high-precision calculations are possible,
If it is not necessary to consider the accumulation of quantization errors,
Fig. 7 shows the shape prediction operation circuit 11 and ADPCM operation circuit 16, respectively.
The operation circuits 11A and 16A shown in FIG.   In addition, a normal tone signal generator has a structure shown in FIG.
No data compression circuit 1 is provided. This data compression circuit
1 is provided because the tone signal generator is a sampler.
Electronic instruments (performers can sample sounds themselves
Electronic musical instruments). [Configuration of the embodiment in FIG. 2]   Next, the electronic musical instrument shown in FIG. 2 will be described.   First, a description will be given of a method of forming a musical tone in this electronic musical instrument.
You.   First, the data compression circuit shown in FIG.
Musical tone waveform standardized and compressed by channel 1
However, for each tone, and for each touch intensity (keypress intensity),
It is stored for each pitch (for each keyboard key). An example
For example, the type of tone is 10, the number of keys is 40, and the touch intensity is 5 steps.
In the case of floor, 10 × 40 × 5 = 2000 kinds of musical sound waveforms are stored
ing. In this case, it is stored in the data memory 35.
Each musical tone waveform has the entire waveform from the beginning to the end of the musical tone.
However, as shown in FIG.
The waveform and the middle of the waveform following this attack part ATC (repeated
(Return RPT waveform). And at the time of music formation
First, the waveform of the attack part ATC is read out,
Thus, the waveform of the repetition unit RPT is repeatedly read. And
After the read waveform is enveloped,
D / A conversion is performed to produce a tone signal.   Hereinafter, the circuit of FIG. 2 will be described in detail. First, code 36
Is a keyboard, and 37 is a touch detection circuit. This touch
The detection circuit 37 detects that any key on the keyboard 36 is pressed.
When the touch is detected, the touch intensity of the same key is detected and the detected touch
The touch data TD corresponding to the intensity is output. This touch
As a method of detecting the intensity, a key is pressed slightly
Contacts that are turned on when the key is pressed to the lowest point.
Contacts for each key, and these contacts
Touch based on the time between successive turns on in response to key-on
Method to detect the touch strength, or use a piezoelectric element
An element for detecting the key press pressure is provided, and the output of this element is
For example, a method of performing detection based on such a method is employed.   Reference numeral 38 denotes a key press detection circuit, which is located below each key of the keyboard 36.
Of each key based on the output of the key switch
Detect ON / OFF state. And any key is
If it is detected that the key has been turned on,
Output KC and key-on signal KON (“1” signal)
At the rising edge of this key-on signal KON.
Then, a key-on pulse KONP is output. Also, the key
When it is detected that the key is turned off, the key-on signal KON
To the “0” signal. Also, multiple keys can be turned on at the same time.
If any key is pressed, one of the keys (for example,
Key or the key with the highest note)
Perform the above processing. Note clock generation circuit 39
Key sound indicated by key code KC output from detection circuit 38
Generates a note clock NCK with a frequency corresponding to high
Output to the section. The address counter 40 is a note clock
NCK is counted up and the count output is added to adder 4
Supply to 1.   The tone selection circuit 42 includes a plurality of tone selection operators and
And the currently set tone selection operator
The tone code TC corresponding to the tone of is output. start
The address memory 43 stores each tone waveform in the data memory 35.
Address data indicating the storage address of the first data is stored
Key code KC, tone code T
When the C and touch data TD are supplied, respectively,
Address data indicating the start address of the tone waveform corresponding to the
Data is read out and output as start address data SA.
Is forced. Repeat address memory 44 is data memory 35
Indicates the storage address of the repeat data of each tone waveform in
This is a memory in which address data is stored. Here, the repeat data is the repetition part RPT shown in FIG.
Means the first data. To this repeat address memory 44
Key code KC, tone code TC, and touch data TD
When supplied, the musical tone waveform corresponding to each of these data
Address data indicating the storage address of the Pete data is read.
And output as repeat address data RA
You. 45 is a selector, and the start address data SA,
Select one of the repeat address data RA,
Output to the addition circuit 41. 46 is a setting for controlling the selector 45.
/ Reset flip-flop.
When the output Q of the rop 46 is a “0” signal,
End A is selected and start address data SA is added to the adder circuit
41, and when the signal is “1”, the input of selector 45
Force end B is selected and repeat address data RA is added
Output to the road 41. The adder circuit 41
Output and the output of the selector 45, and
It is supplied to the data memory 35 as dress data AD.   The attack end address memory 47 has a data memory 35
Attack end data of each tone waveform in the memory
Memory that stores address data indicating
You. Here, the attack end data is shown in FIG.
This is the last data of the attack part ATC. This attack
Key code KC, tone code T to end address memory 47
When the C and touch data TD are supplied, respectively,
Of attack end data of musical sound waveform corresponding to data
The address data indicating the address is read and the attack
Output to the comparison circuit 48 as the end address data AEA
You. The comparison circuit 48 outputs the address output from the addition circuit 41.
Compare data AD with attack end address data AEA
When the two match, the attack end signal AEND
(“1” signal) is output. 49 is D- for timing adjustment
FF (delay flip-flop)
Signal AEND is delayed by one timing of note clock NCK
And output it as signal AENDD. Repeat end address
The memory 51 is a repetition section of each tone waveform in the data memory 35.
Address data indicating the storage address of end data is recorded.
This is the memory that is remembered. Here,
Is the last data of the repeat part RPT shown in FIG.
U. Key code to this repeat end address memory 51
KC, tone code TC, touch data TD are supplied respectively
And the repetition section of the tone waveform corresponding to each of these data
Address data indicating the storage address of the read data
And compared as repeat end address data REA
Output to the road 52. The comparison circuit 52 outputs from the addition circuit 41
Address data AD and the repeat end address data
Data REA, and when they match, repeat
Output the REND signal (“1” signal). 53 is a timing tone
D-FF for adjustment and notes the repeat end signal REND
One timing delay of clock NCK, as signal RENDD
Output.   The repeat frame memory 56 shown at the top of FIG.
Belongs to the repeat data described above (the first data of the repetition part RPT)
Frame numbers are stored for each tone waveform.
The memory that is being used. That is, in the waveform example of FIG.
In this case, the repeat data belongs to frame [2].
To which frame this repeat data belongs
This is determined for each musical tone waveform. Repeat frame
This repeat data is stored in advance in the
The number of the frame to which the data belongs is stored.
Code KC, tone code TC, and touch data TD are supplied respectively.
Then, the frame number corresponding to each of these data is read.
Output to the preset data terminal PD of the frame counter 57.
Output to The frame counter 57 is currently
A counter that outputs the number of the frame being performed.
Reset by the key-on pulse KONP and the signal RE
The output data of the repeat frame memory 56 is
It is preset and the output of D-FF58 is counted up.
To The count output of the frame counter 57 is
Frame end address memo as frame code FLC
The data are supplied to the memory 59 and the linear prediction coefficient memory 61. Frey
The memory end address memory 59 stores frames [0] to [N-
[1] Data memory in which each final waveform data is stored
Address data indicating 35 addresses are stored for each tone waveform.
It is a stored memory. To this memory 59
Do KC, tone code TC and touch data TD are supplied respectively
And N address data corresponding to each of these data in advance.
The storage area where the data is stored is specified, and this storage
Each address data in the area is sent from the frame counter 57
Read based on the output frame code FLC
You. The read address data is
Comparison circuit 60 as the memory end address data FLEA (FLC)
Output to The comparison circuit 60 outputs from the addition circuit 41
Address data AD and frame end address data
Compare with FLEA (FLC), and when they match, "1" signal
Is output. 58 is a D-FF for timing adjustment,
The output signal of the comparison circuit 60 is one time of the note clock NCK.
Output to the clock terminal CK of the frame counter 57.
Power.   The linear prediction coefficient memory 61 stores the linear prediction coefficient a₁, A_TwoIs remembered
Each sound waveform in the data memory 35
Has a storage area corresponding to each of these storage areas.
N at the rear correspond to frames [0] to [N-1], respectively.
Set of linear prediction coefficients a₁, A_TwoIs stored. And ki
-Code KC, tone code TC and touch data TD are supplied respectively
Then, the storage area corresponding to each of these data
Is selected and the linear prediction coefficient a in this storage area is₁, A
_TwoIs the frame code output from the frame counter 57.
Read based on the FLC.   Next, 63 is the quantization difference output from the data memory 35.
A decoding circuit for decoding the code Cn into decoded data Hn.
8 is shown in FIG. The configuration of the decoding circuit 63 is basically
This is similar to the decoding circuit 3 shown in FIG.
Signal circuit 24A and a linear prediction decoding circuit 29A.
You. In the ADPCM decoding circuit 24A, 100 is a quantization difference code.
When the code Cn is supplied, the coefficient k corresponding to the value is output.
ADPCM coefficient memory, and the conversion data shown in FIG.
Is stored. This ADPCM coefficient memory 100 outputs
The coefficient k is supplied to one input terminal of the multiplier 101, where
Then, the previous quantization width data Δn_-1And the product is taken. You
That is, the calculation of the above-mentioned expression (3) is performed, and
The quantization width data Δn is calculated. The output of this multiplier 101
The force data Δn is supplied to the input terminal B of the selector 102.
The selector 102 receives an input when a “1” signal is supplied to the terminal SA.
Select the terminal A, and when the “1” signal is supplied to the terminal SB, the input terminal
Select B. That is, the selector 102
Select input terminal A only when Lus KONP is output, and others
In this case, the input terminal B is selected. 103 is quantization width data Δ
Initial value of n Δn₀Is an initial value storage unit in which
Initial value Δn that is the stored value₀Is the input terminal A of the selector 102
Supplied to The output signal of this selector 102 (Δn
Or Δn₀) Is a decoder 110 via a maximum / minimum control unit 104,
Supplied to delay flip-flop 105 and latch 106
Is done. The maximum / minimum control unit 104 calculates the quantization width data Δn.
It regulates the maximum and minimum values.
Small value is (16)_Ten, The maximum value is (1552)_TenIs set to
If the data Δn exceeds these limits,
The above-mentioned limit value is output. Delaif
The lip flop 105 is based on the note clock NCK.
Although the quantization width data Δn is delayed by one clock timing,
Therefore, the latch 106 receives the attack end signal AEND.
When supplied, the quantization width data Δ supplied to the input end
n is latched. Delay Flip Flow Above
The output data of the latch 105 and the latch 106 are
7 input terminals A and B. The selector 107 is connected to the terminal SA
When the "1" signal is supplied to the terminal, the input terminal A is selected, and the terminal
When the "1" signal is supplied, the input terminal B is selected. Sand
That is, the selector 107 is input only when the signal RENDD is supplied.
Select end B, otherwise select input A. This
In this case, when the input terminal A of the selector 107 is selected,
One clock timing by Ray flip-flop 105
Quantized width data Δn delayed_-1Is output from output terminal S
Is done. When the input terminal B of the selector 107 is selected,
In this case, the data in the latch 106 is output.
The operation of this case will be described later. And, according to the above configuration,
Thus, a quantization width control circuit 108 is configured. Next,
The coder 110 is similar to the decoders 20 and 26 shown in FIG.
(4) a decoder for performing the operation of the expression, and the output data
Becomes “en + dn”. 111 is an addition circuit, which is a decoder 1
Data “en + dn” output from 10 and selector 117
Predicted data output from En_-1And add
The result, that is, the data “En + dn” is linearly decoded by the predictive decoding circuit 29A.
Is output to the adder circuit 65. 115 is D-FF28 shown in FIG.
D-FF similar to the above, and the data supplied to the input terminal
Based on the note clock NCK, one clock timing
Output with a delay. 116, key-on pulse KONP
A gate that opens when no force is applied
In the open state, the output of the D-FF 115 is
Is supplied to the input terminal A. 118 is a latch and attack
When the end signal AEND is supplied, the
And latch it. The output of this latch 118
The force signal is supplied to the input terminal B of the selector 117. SEREC
117 selects the input terminal B only when the signal RENDD is supplied.
Otherwise, the input terminal A is selected. In this case,
When the input terminal A of the selector 117 is selected, the D-FF 115
"En + dn" delayed by one clock timing
Output from the output end. Also, the input terminal B of the selector 117
Is selected, the data in latch 118 is output.
However, the operation in this case will be described later.   Next, the linear prediction decoding circuit 29A will be described. Ma
65 is the data "En + d" supplied to one of its input terminals.
n "and the predicted value ◇ Sn supplied to the other input terminal.
Addition circuits 66 and 67 each add the signal AEN to the load terminal L.
Latch to read data of input terminal when DD is supplied, 6
8,69 are selectors, respectively. These selectors 68, 69
Input terminal A when repeat end signal REND is "1" signal
Data at the input terminal B when the signal is "0".
Output. 70 and 71 are supplied with the note clock NCK, respectively.
Read the data at the input end and send it to the key-on pulse KONP
Therefore, the D-FFs 72 and 73 reset are each a linear prediction coefficient.
Number a₁, A_TwoIs the multiplier coefficient, and 74 is the multiplier of the multipliers 72 and 73.
This is an addition circuit for adding each output.   Next, in FIG. 2, reference numeral 76 denotes an envelope generator.
Key-on signal KON has risen to a “1” signal
After that point, key code KC, tone code TC, touch data
Envelope data ED determined according to each value of data TD
The output is supplied to the multiplication circuit 77. Fig. 9 (a) is keio
(K), and (B) and (C) are envelopes respectively.
An example of a change in the value of the data ED is shown. Where (b) is
-In the case of a bass-based tone, (c) is a sustained tone.
Is the case. The multiplication circuit 77 is output from the decoding circuit 63
The decrypted data Hn is multiplied by the envelope data ED, and
The result of the multiplication is output to D / A converter 78. D / A converter 78 multiplies
Converts the output data of the circuit 77 into an analog signal,
Output to system 79. The sound system 79 has a D / A conversion
Amplifies the output signal of the converter 78 and sounds it through a speaker.
You. [Operation of the embodiment in FIG. 2]   First, the performer operates the tone selection operator to select the tone of the musical tone.
When the color is set, the tone selection circuit 42 outputs the set sound.
The tone code TC corresponding to the color is output and supplied to each part of the circuit.
Be paid. Next, one of the keyboards 36 by the performer
When any key is pressed, the touch detection circuit 37
The data TD receives the key-on pulse KO from the keypress detection circuit 38 again.
NP, key-on signal KON (“1” signal) and key code KC are each
Output to each part of the circuit. Key-on pulse KONP detects key press
When output from the circuit 38, the flip-flop 46
Reset the counters 57 and D-FF70 and 71 (Fig. 8).
It is. When the frame counter 57 is reset, the frame
The frame code FLC output from the
"0" and the frame code FLC "0"
Memory 59 and linear prediction coefficient memory 61
Output to As a result, the frame end address
Frame end address FLEA (0) is output from memory 59
Also, the linear prediction coefficient memory 61
Linear prediction coefficient a₁, A_TwoIs output. Also the key mentioned above
The on-pulse KONP is applied to the address
To the address counter 40.
Reset. Furthermore, the key-on pulse KONP is
It is supplied to the selector 102 in FIG. This allows the initial
Initial value Δn of Δn output from value storage unit 103₀Is
The decoder 11 via the
Supplied to 0 and latched internally.   The key-on signal KON is output from the keypress detection circuit 38.
After that, the envelope generator 76
The envelope data ED is output. Also, the key code KC
A note clock generation circuit output from the key press detection circuit 38
After being supplied to 39, the note clock generation circuit 39
Note that the frequency corresponding to the pitch of the pressed key
Lock NCK is output and supplied to the address counter 40.
You. The address counter 40 uses this note clock NCK
Count up. Thereby, the address counter 40
Count output sequentially changes to 0, 1, 2,.... This
The count output of the dress counter 40 is supplied to the adder circuit 41
In the adding circuit 41, the output of the selector 45 and the adder are added.
Is calculated. At this time, flip-flop 46 is reset.
Therefore, the start address memory 43
Whether the input start address data SA is the selector 45
Output from As a result, the output of the addition circuit 41
Start address data SA and address counter 40 count
Data and the data output, and this data is
The data is output to the data memory 35 as the address data AD. sand
That is, "SA + 0", "SA + 1", "SA + 2" ...
The dress data AD is sequentially output to the data memory 35. This
As a result, the data memory 35 first reads the attack part ATC
The quantized difference codes Cn are sequentially output and supplied to the decoding circuit 63
Is done.   The decoding circuit 63 first converts the quantized difference code Cn into data
Decrypt to “En + dn” and then convert this data “En + dn”
Data Hn. In other words, the quantum
At the time when the digitized difference codes Cn are sequentially output,
The beat end signal REND is in the “0” signal,
Impulse KONP only becomes “1” signal at key-on,
After the key is turned on, the signal immediately becomes “0”.
Each input terminal A of the collectors 107 and 117 (FIG. 8) is selected,
The data supplied to the input terminal A is output from each output terminal S.
Is forced. That is, at this point, the AD in FIG.
PCM decoding circuit 24A is the same circuit as ADPCM decoding circuit 24 in FIG.
It has become. As a result, the data output from the data memory 35 is output.
In the ADPCM decoding circuit 24A, the quantized difference data Cn
In the circuit of FIG. 1, decoding is performed in the same manner as in the case of FIG.
+ Dn ”is output to the linear prediction decoding circuit 29A.   During key-on, the key-on pulse KONP is set to “1”.
As a result, the output of the gate 116 becomes “0” and this data
“0” is supplied to the adder circuit 111 via the selector 117.
You. As a result, the adder 111 outputs the data “en + dn”
Is output as data “En + dn” as it is.   The linear prediction decoding circuit 29A decodes the data "En + dn"
Data Hn = Sn + dn. That is, first, key-on
When signal KON rises, repeat end
The signal REND is at the "0" signal, and therefore the selector 68,6
9 (Fig. 8) Data at each input terminal B is output from each output terminal
Is done. That is, at this point, the linear
The predictive decoding circuit 29A is the same as the linear predictive decoding circuit 29 in FIG.
It is a circuit. Therefore, the output from the adder circuit 111
The input data “En + dn” is sent to the linear prediction decoding circuit 29A.
Is decoded in the same manner as described above, and the decoded data Hn
Is output as   The multiplication circuit 77 adds the decoded data Hn to the
An envelope is provided, and the output of the multiplication circuit 77 is D / A
The signal is converted to an analog tone signal by the converter 78,
The analog tone signal is converted to a tone in the sound system 79.
Is pronounced. Thus, first, the frame [0]
Is formed.   Next, the address data AD is the frame end address FL
When EA (0) is reached, the comparator circuit 60 outputs a “1” signal.
And the clock terminal of the frame counter 57 via the D-FF 58.
Supplied to child CK. As a result, the frame counter 57
Incremented and frame code FLC becomes “1”
You. When the frame code FLC becomes “1”, the frame
Frame address FLEA from the command address memory 59
(1) is output. Also, from the linear prediction coefficient memory 61
Linear prediction coefficient a for frame [1]₁, A_TwoIs output and multiplication is performed.
Are supplied to devices 72 and 73 (FIG. 8).   Hereinafter, the reading of the data memory 35 proceeds, and
Thus, the tone of the frame [1] is formed. And the ad
Address AD reaches frame end address FLEA (1)
Then, in the same way as above, the frame end address
From frame 59, the frame end address FLEA (2) is
Further, the linear prediction coefficient memory 61 stores the linear prediction of frame [2].
Coefficient of measurement a₁, A_TwoAre output, and thereafter, the frame [2]
A musical tone is formed.   Then, for example, during the tone formation of this frame [2]
The address data AD is the attack end address
When the AEA matches (see FIG. 3), the comparator 48
Attack end signal AEND is output.
Signal AEND to the load terminal L of the latches 106 and 118 (FIG. 8)
Supplied. As a result, the latch 106 has an attack section ATC
Is stored as the quantization width data Δn corresponding to the last data of
The latch 118 has the last data “En +
dn ”is stored.   In addition, note-taking starts when the attack end signal AEND occurs.
One timing after the lock NCK, the D-FF4 shown in FIG.
9 outputs the signal AENDD. This signal AENDD
It is supplied to the address counter 40 through the gates 86 and 84,
Thereby, the address counter 40 is reset. Ma
The signal AENDD is supplied to the set terminal S of the flip-flop 46.
To set flip-flop 46.
It is. When the flip-flop 46 is set, the reset
Pete address RA is supplied to adder circuit 41 via selector 45.
Be paid. The signal AENDD is supplied to the latches 66 and 67 (FIG. 8).
Is supplied to the load terminal L of the
The output data of FF70 and 71 are read into latches 66 and 67, respectively.
You. Now, the attack output from the adding circuit 65 in FIG.
The data Hn of the last part of the part ATC and the first part of the repetition part RPT
Assuming that the minute data Hn is as shown in FIG.
The outputs of D-FF70 and 71 are shown in Fig. 10 (b) and (c), respectively.
Data, and signal AEND and signal AENDD
It is output at the timings shown in FIGS.
As can be seen from these timing diagrams, the signal AENDD
Is supplied to the load terminals L of the latches 66 and 67, the latch 6
The last data of the attack part ATC (A1) and 6,67 respectively
The second last data (A2) is stored.   The above is the operation based on the signal AENDD. After that, add
From the circuit 41, "RA + 0", "RA + 1", "RA + 2" ...
Address data AD are sequentially output, thereby
The tone formation of the return part RPT is performed. In this case, the attack
Each time the frame changes, a new
Linear prediction coefficient a₁, A_TwoComes out of the linear prediction coefficient memory 61.
And supplied to the decoding circuit 63.   Next, the address data AD is the repeat end address RE
If it matches A, that is, the tone of the first repetition part RPT
When the formation is completed, the repeat end signal is output from the comparison circuit 52.
REND (“1” signal) is output, D-FF53 and selector
68, 69 (FIG. 8). Selector 68, 69
When the pete end signal REND is supplied, the selectors 68 and 69
Input terminal A is selected, and the outputs of latches 66 and 67 are selected.
Are supplied to the input terminals of the D-FFs 70 and 71 through the input terminals 68 and 69, respectively.
Next, when the note clock NCK is output, the D-FFs 70 and 71
The outputs of latches 66 and 67 are read into
Outputs a signal RENDD (“1” signal). This signal RENDD
Is output to the preset terminal PR of the frame counter 57.
As a result, the output of the repeat frame memory 56 (this
In the example of "2"), the frame counter 57 is preset.
Is done. As a result, the frame code FLC becomes “2”.
Frame address from the frame end address memory 59.
Address FLEA (2) is output and the linear prediction coefficient
The linear prediction coefficient a of the frame [2] from the memory 61₁, A_TwoIs each
Are output each time. The signal RENDD is shown in FIG.
The signals are supplied to the selectors 107 and 117.
7,117 input terminals B are selected. When this input terminal B is selected
Output, the outputs of the latches 106 and 118 activate the selectors 107 and 117, respectively.
Output via Therefore, the second time of the repeat part RPT
Of the first quantized difference code Cn in the tone formation
At which point, the quantization width referred to as the previous value
Data Δn_-1And PCM playback code ◇ En_-1Each
And the one corresponding to the last quantized difference code Cn of the ATC
It is as if the tone formation continued from the attack part ATC
Has the same effect as was done.   The signal RENDD is addressed via OR gates 86 and 84.
The counter 40 is supplied to the
Data 40 is reset. As a result, the addition circuit 41
Again, "RA + 0", "RA + 1", "RA + 2" ...
The dress data AD is sequentially output.
The second tone generation of T is performed. In this case, linear
Prediction coefficient a₁, A_TwoOf course, it changes for each frame.   Here, the decryption data at the beginning of the second repetition unit RPT
The data Hn will be described. Now, as shown in Fig. 11 (a)
Thus, the decoded data Hn of the last part of the repetition unit RPT is
2, RE1. Fig. 11 (b) and (c) show the
A signal end signal REND and a signal RENDD are shown. Also,
The data A described in FIG.
1, A2 (decoded data of the last part of the attack part ATC) is recorded.
Remembered. In this case, the timing of the signal RENDD
As shown in FIGS. 11 (d) and (e), the D-FFs 70 and 71
Are read data A1 and A2, respectively. On the other hand, this signal REN
At the timing of DD, the first quantum of the repetition unit RPT
The structured difference code Cn is read from the data memory 35. You
That is, the first quantum of the repetition part RPT in the second time
When the structured difference code Cn is read from the data memory 35
In the case where the data in the D-FFs 70 and 71 are
The same and therefore the same decoding as in the first case
Data Hn is output from linear prediction decoding circuit 29A. As well
Then, the second, third,...
Data Hn is the same as in the first case.   Next, the tone formation of the second repetition unit RPT is completed.
Then, by the same process as above, the third time,
The tone formation of the repetition section RPT of the fourth time is performed.   Next, when the player releases the key, the key-on signal KON
Returns to the “0” signal. As a result, the envelope data ED
Gradually attenuates to "0", and thus the generated musical tone is attenuated.
And stop. [Experimental results of the above embodiment]   FIG. 12 is a view showing an experimental result of the above embodiment. Same figure
(A) shows the original data Sn sampled from the piano sound
You. FIG. 2B shows the data Sn shown in FIG.
Is converted to a quantized difference code Cn by the data compression circuit 1.
And store the code Cn in the memory.
8 and decoded by the circuit shown in FIG.
Signal data Hn. The figure (c) shows the data of (a).
The result obtained by subtracting the data Hn of (b) from the data Sn,
Indicates a reproduction error. In (c), the vertical scan
The kale is four times larger than (a) and (b).   As shown in Fig. (C), the above-mentioned embodiment
Despite being compressed and stored in memory,
It is possible to reproduce with a very small error.   In the above embodiment, the order of the linear prediction operation, that is,
The number of stages of the D-FFs 14a and 14b in FIG. 1 is quadratic. Experiment
According to the result, the reproduction error is the smallest in the second order case.
Become. For example, FIG. 4D shows the case where the order is set to 4th order.
(All other conditions are the same as in (a) to (c))
Therefore, the reproduction error is larger than in the case of the second order. this
The reason is that the accuracy of the linear prediction operation is
Of the ADPCM calculation
This is because the compression ratio (accuracy) of the road decreases.
On the other hand, in the case of the second order, the correlation between each of the data En
Remains to some extent, which results in the ADPCM arithmetic circuit.
Compression rate is improved. [Modification of the above embodiment] (1) The ADPCM decoding circuit 24A shown in FIG.
May be configured. In the circuit shown in FIG.
If both the latches 106 and 118 in FIG.
Instead of the Δn repetition unit for calculating the initial value of the repetition unit RPT.
Period value memory 106A and attack part final data value memory 11
8A (both ROM) is provided. That is, this
The circuit sends data to latches 106 and 118 by the signal AEND, respectively.
Instead of storing the data, the data to be stored is stored in advance.
It is prepared in the lips 106A and 118A. Note that this
In this case, not only the data but also each tone waveform in the data memory 35
Prepared corresponding to each.   FIG. 14 shows the linear predictive decoding circuit 29A shown in FIG.
It may be configured as follows. In the circuit shown in FIG.
Is not provided with the latches 66 and 67 shown in FIG.
Initial value data memory 130 for initial value calculation of repetition unit RPT
(ROM) is provided. In this initial data memory 130
Is the last compressed data A1,
A2 is recorded corresponding to each tone waveform in the data memory 35.
Key code KC, tone code TC, touch
When the data TD is supplied, the corresponding data A1, A2
Is read and supplied to the selectors 68 and 69.   In each of the above configurations, the memories 106A, 118A, 130A
Each as RAM, when power is turned on or when tone is selected, etc.
Calculation to obtain each data and store it.
Good.   Also, the decoding circuit 63 of FIG. 2 is equivalent to the circuits 24A, 29A,
The circuit in Fig. 13 and the circuit in Fig. 14 can be combined appropriately.
No. (2) The above embodiment is a single-tone electronic musical instrument.
Of course, the present invention can be applied to a double tone electronic musical instrument. And double sound
In the case of a child musical instrument, it is preferable to use time-division processing. (3) Comparison circuits 48, 52, 60 and multiplier 7 in the above embodiment
The arithmetic processing such as 2,73 may be performed by time division processing. (4) In the above embodiment, the data stored in the data memory 35 is
Although the musical sound waveform to be used has a standardized waveform,
Unenveloped waveforms with envelopes are stored in the same memory 35.
You may let it. (5) In the above embodiment, the tone code TC, the key code
The tone waveform is recorded for each of the
I reminded me that the tone waveform only corresponds to the tone code TC.
It may be stored. Also, each of the controls operated by the player
A musical sound waveform may be stored according to the operation state. the above
Either combination is possible. (6) For each key code KC and each touch data TD
Instead of storing musical tone waveforms,
You may make it. For example, in the case of touch data TD,
The waveform corresponding to the strongest touch data TD and the weakest touch
Each waveform corresponding to data TD is stored, and
For touch data TD, the strongest and weakest touches
Waveform is calculated from each waveform corresponding to data TD by interpolation calculation.
Ask. Note that the circuit configuration for performing this interpolation calculation is
Is disclosed in JP-A-60-55398. (7) In the above embodiment, there is one repetition unit RPT.
However, it is necessary to provide multiple
May be. In such a case, the repetition section and the next
In order to make the connection with the return part smooth, interpolation connection
-147793) may be used. Also, JP-A-59-18
Even when using the waveform connection method described in 8697
Good. (8) In the above embodiment, the waveform processing device 6 (first
Digital data output from Fig.) Is temporarily stored in the waveform memory.
7, the compression process is performed.
This compression processing may be performed on the image. (9) In the above embodiment, the output data of the A / D converter 5
After standardizing the data, compression is performed.
Calculation so that the repeat part is connected smoothly.
After performing the data editing, that is, after performing waveform editing appropriately
It may be compressed. (10) In the above embodiment, the microphone 4
A / D conversion by the A / D converter 5
Music data is obtained, but instead of this, a computer
Get the original music data by simulation
You may do it. (11) Data compression circuit, data memory, and data decoding
The circuit is integrated into one electronic musical instrument
You may comprise a child instrument. (12) The present invention is not limited to keyboard musical instruments.
Also applicable to electronic instruments without keyboards, such as rhythm or rhythm sound sources
It is. (13) After the decoding circuit, touch data TD and key code
(Digital) filter whose filter characteristics change according to KC etc.
Filter to control the tone by passing this filter.
You may control. (14) Method of forming address data AD of data memory 35
May be a method other than the above embodiment. For example, F number
(Frequency number) accumulating method, sequentially decreasing from ALL “1”
To form address data by calculating
Using the set type address counter 40,
How to Preset Dresses, (Micro)
Any method of calculating addresses using a program
Method may be used. (15) In the above embodiment, the repetition unit RPT is
Reads repeatedly to form a musical tone
Records the entire musical tone waveform from the start to the end in the memory.
Remember, do n’t read repeatedly
Is also good. (16) In the above embodiment, linear prediction is performed for each frame.
Coefficient a₁, A_TwoIs changed, but for all frames
Linear prediction coefficient a₁, A_TwoMay be the same value. This
In the case of, of course, there is no need to divide the frames. (17) The frame switching method is not limited to the method of the above embodiment.
No. For example, using the upper bits of the address data AD
Frame switching may be performed. (18) In the above embodiment, the frame switching position and
Although the return section settings are independent,
Both may be synchronized by performing frame switching or the like. "The invention's effect"   As described above, according to the present invention, the tone waveform
The waveform data indicating each instantaneous value is subjected to a second-order linear prediction operation and
Data is compressed by quantization using the differential quantization method,
The data obtained by this data compression is stored in memory
Read and decode the stored data,
A tone signal is generated based on the decoded waveform data.
Memory capacity is significantly larger than the conventional one.
And minimize the reproduction error
There is an effect that can be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention;
FIG. 2 is a block diagram showing a configuration example when the embodiment is used in an electronic musical instrument, FIG. 3 is a diagram showing an example of a musical tone waveform,
5 shows the relationship between the coefficient k and the quantization difference code Cn. FIG. 5 is a diagram for explaining the principle of data compression by the encoder 18 in FIG. 1, and FIG. 6 is data en, quantization width data. FIG. 7 shows the relationship between Δn and the quantized difference code Cn. FIG. 7 shows the linear prediction operation circuit 11 and the ADPCM operation circuit 1
6 is a block diagram showing another configuration example, FIG. 8 is a block diagram showing a detailed example of the decoding circuit 63 in FIG. 2, FIG. 9 is a waveform diagram showing an example of an envelope waveform, and FIG.
Timing diagram for explaining the connection between the ATC and the repetition unit RPT,
FIG. 11 is a timing chart for explaining the connection between the end of the first repetition section RPT and the beginning of the second repetition section RPT. FIGS. FIG. 13 is a diagram showing experimental results of the embodiment shown in FIG. 2, FIG. 13 is a block diagram showing another configuration example of the ADPCM decoding circuit 24A, and FIG. 14 is a linear prediction decoding circuit 29A.
FIG. 13 is a block diagram showing another example of the configuration. 1 ... Data compression circuit, 2,35 ... Data memory, 3,63 ...
... Decoding circuit, 11 ... Linear prediction operation circuit, 16 ... ADPCM operation circuit.

Claims (1)

(57) [Claims] A storage means for compressing the waveform data indicating each instantaneous value of the musical tone waveform by a second-order linear prediction operation and quantization by a differential quantization method, and storing the data obtained by the data compression; Instructing means for instructing, and decoding means for reading data in the storage means in accordance with the instruction of the instructing means, and decoding by a decoding operation based on a secondary linear prediction operation and a differential quantization scheme, A tone signal generating apparatus for generating a tone signal based on waveform data decoded by the decoding means.