JP2715966B2 - Synchronous switching device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous switching device used in a digital wireless communication system, and more particularly to a synchronous switching device for switching a working line to a protection line at a receiving end of a digital wireless communication system without an instantaneous interruption.

[0002]

2. Description of the Related Art When a working line of a communication system is switched to a protection line, first, a protection line is connected in parallel to a working line at a transmitting end, and a signal to be transmitted is also passed through the protection line. Switch to the protection line. If the signal to be transmitted is a digital signal and the relative delay time difference between the working line and the protection line is one clock cycle or more, the signal transmitted on the working line and the signal transmitted on the protection line are directly switched at the receiving end. Bits are dropped or duplicated, causing instantaneous interruption. To avoid this momentary interruption, the relative delay time difference is set to 1
It must be adjusted within the clock cycle.

When the line is a wireless line, the propagation time fluctuates due to fading or the like, and the relative delay time difference between the working line and the protection line may fluctuate by one clock cycle or more. For this reason, the initial adjustment is performed so that the average of the relative delay time differences, in other words, the fixed component of the relative delay time difference is within one clock cycle, but further adjustment of the fluctuation component is required.

A variable delay circuit is provided to adjust the relative delay time difference, and the relative delay time difference is detected by comparing the frame phases of the signal transmitted on the working line and the signal transmitted on the protection line. 2. Description of the Related Art There is known a synchronous switching device that controls a delay amount of a variable delay circuit based on a detection result.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a specific structure of a synchronous switching device employing such a system.

[0006]

According to the present invention, there is provided a synchronization switching apparatus comprising: a working data signal transmitted on a working radio line; and a protection data signal transmitted on a protection radio line for switching the working radio line. A synchronous switching device that switches the working-side data signal to the backup-side data signal without an instantaneous interruption by adjusting the relative delay time difference between the input clock signal and the input clock signal at a division ratio M (M is an integer of 2 or more). A first frequency divider that divides and outputs a frequency, and a second frequency divider that divides and outputs a spare clock signal, which is a clock of the spare data signal, by a dividing ratio N (N is an integer of 2 or more). A frequency divider; a phase comparator for detecting a phase difference between signals output from the first and second frequency dividers; and an output for reducing the phase difference detected by the phase comparator. The phase is controlled to generate the clock signal A variable frequency oscillator that outputs the clock signal to the first frequency divider; a read control unit that outputs the clock signal as a read clock signal; and a read control unit that receives the standby data signal and sequentially uses the standby clock signal as a write clock. A FIFO memory for sequentially reading and outputting the read clock signal supplied from the read control unit as a read clock, and a spare frame synchronization circuit for outputting a spare frame pulse in frame synchronization with the data signal read by the FIFO memory A working-side frame synchronizing circuit for outputting a working-side frame pulse in frame synchronization with the working-side data signal; and The value N / M, which is the ratio of the frequency division ratio N to the frequency ratio M, is 1 When the delay is larger than the delay, the frequency division ratio of at least one of the first and second frequency dividers is controlled so as to be smaller than 1, and the timing between the working frame pulse and the spare frame pulse is controlled. Control means for outputting a switching control signal when the values match, inputting the working data signal, a working clock signal which is a clock of the working data signal, a data signal read by the FIFO memory, and the read clock signal. The active side data signal and the active side clock signal are selected and output until the switching control signal is input from the control means, and when the switching control signal is input, the data signal read by the FIFO memory and the read clock are input. And a switching circuit for selecting and outputting a signal.

In the present invention, the control means counts the read clock signal input during a period from the input of the working frame pulse to the input of the spare frame pulse and outputs a count value. Detecting the advance / delay of the spare frame pulse with respect to the working frame pulse based on frame length information of the working data signal and the spare data signal and the count value output by the counting circuit. When the speed is progressing, the frequency dividing ratio N is set to be larger than the frequency dividing ratio M. When the speed is delayed, the frequency dividing ratio N is set to be smaller than the frequency dividing ratio M. And a control circuit for controlling the frequency division ratio N of the second frequency divider.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing one embodiment of the present invention, an M frequency divider 11 of a read control unit 1 divides an input clock signal by M and outputs the result. The N frequency divider 12 is a frequency divider with a variable frequency division ratio N, and divides the frequency of the backup clock signal CLKIS, which is the clock of the backup data signal DATAIS transmitted through the protection channel, by N and outputs the frequency. The phase comparator 13 detects a phase difference between the output of the M frequency divider 11 and the output of the N frequency divider 12, and outputs a detection result. An exclusive OR circuit can be used as the phase comparator 13. The filter 14 smoothes the output of the phase comparator 13 and outputs the result. VC
O15 is a clock generator whose output phase is controlled by the output of the filter 14, and outputs the generated clock signal to the M frequency divider 11 and also outputs it as a read clock signal CLKR. The output phase of the VCO 15 is controlled so that the output of the filter 14 becomes smaller, in other words, the phase difference between the output of the M divider 11 and the output of the N divider 12 becomes smaller. If the frequency division ratio N of the N frequency divider 12 is equal to the frequency division ratio M of the M frequency divider 11, the read clock signal CLKR output from the VCO 15 is phase-synchronized with the backup clock signal CLKIS.

The FIFO memory 2 uses the spare clock signal CLKIS as a write clock to generate the spare data signal D
ATAIS is sequentially written, the read clock signal CLKR output from the VCO 15 is sequentially read as a read clock, and output as a data signal DATAR.

The frame synchronization circuit 3 includes a FIFO memory 2
And the read clock signal CLKR, which is the clock of the data signal DATAR,
Reserved frame pulse FP in frame synchronization with ATAR
Output S. The frame synchronization circuit 4 receives the working data signal DATAI transmitted through the working line and the working clock signal CLKI as a clock thereof, and outputs a working frame pulse FP in frame synchronization with the working data signal DATAI. .

The counting circuit 5 has a current-side frame pulse FP
Is used as a start signal, the read-out clock signal CLKR is counted using the spare frame pulse FPS as a stop signal,
Output the count value. This count value is a signal indicating how many clock cycles the spare frame pulse FPS is delayed with respect to the working frame pulse FP, and the data signal DATAR is determined with reference to the working data signal DATAI.
Is a signal indicating how many clock cycles are delayed. Working data signal DATAI and data signal DATA
If there is no relative delay time difference from R, the count value becomes zero.
The control circuit 6, the frame length information and count value counting circuit 5 and outputs the line switching controller of the data signal based on the (not shown) or ^these line switching command, use side data signal DATAI and data signals DATAR The frequency division ratio N of the N frequency divider 12 is controlled so as to reduce the relative delay time difference between them, and when the count value output from the counting circuit 5 becomes zero, a switching control signal is generated and output.

The switching circuit 7 has a working data signal DAT.
AI, working clock signal CLKI, data signal DAT
AR, the read clock signal CLKR, and the switching control signal from the control circuit 6, the output data signal D
The signal to be selectively output as ATAO and output clock signal CLKO is switched from the current working data signal DATAI and working clock signal CLKI to the data signal DATAR and read clock signal CLKR.

Since the embodiment shown in FIG. 1 has the above-described configuration, the working-side data signal DATAI transmitted through the working line and the working-side clock signal CLKI as its clock are directly input to the switching circuit 7. . The protection side data signal DATAIS transmitted by the protection line connected in parallel to the working line at the transmitting end in response to the line switching command from the line switching control device is sequentially written to and read from the FIFO memory 2 and is delayed. Signal DATAR
The read clock signal CLK which is the clock
It is input to the switching circuit 7 together with R.

Assuming that the maximum variation width of the relative delay time difference between the working data signal DATAI and the backup data signal DATAIS is ± m clock cycles, the FIFO memory 2 adjusts the maximum variation width by using the FIFO memory 2. The signal storage capacity is set to 2m + 1 clock cycles.
The working-side data signal DATAI is set to the spare-side data signal D.
The initial adjustment of the fixed component of the relative delay time difference is made so that the average delay of m clock cycles with respect to ATAIS is delayed.
With these settings, the delay amount of the FIFO memory 2 becomes a minimum 0 and a maximum 2 m clock cycle, and the data signal DAT
Since AR is delayed by a minimum of 0 m and a maximum of 2 m clock cycles from the spare data signal DATAIS, the relative delay time difference between the two data signals input to the switching circuit 7 is less than ± m clock cycle. By adjusting the amount of delay by the FIFO memory 1, the relative delay time difference between the two data signals input to the switching circuit 7 can be made within one clock cycle.

Assuming that the count value output from the counting circuit 5 is n,
When the data signal DATAR lags behind the working-side data signal DATAI, the count value n is the delay itself in units of the clock cycle. If you are going in the opposite direction,
The protection-side frame pulse FPS as the stop signal of the counting circuit 5 is the working-side frame pulse FP as the start signal.
Since the frame pulse is a frame pulse that is one frame after the frame No. 1, the value f−n is the advance with the frame length set to f clock cycle. Since the relative delay time difference between the data signal DATAR and the working data signal DATAI is less than ± m clock cycle and the frame length f clock cycle is much larger than the maximum variation width of the relative delay time difference ± m clock cycle, The value n in the case is slightly smaller than the value f and much larger than the value m. Accordingly, the threshold value between the value f and the value m is used to determine the threshold value of the count value n, and it is possible to determine whether the count value is advanced or delayed.

The control circuit 6 controls the frequency division ratio N of the N frequency divider 12 to be equal to the frequency division ratio M of the M frequency divider 11 when no line switching command is input. Therefore,
At this time, the read clock signal CLKR, which is the read clock of the FIFO memory 1, is phase-synchronized with the spare clock signal CLKIS, which is the write clock.
The amount of delay by the FO memory 1 continues to be determined by the initial state.

When the line switching command is input, the control circuit 6 determines the count value n output from the counting circuit 5 as a threshold value,
If the value n is smaller than the threshold value, the data signal DATAR
Is behind the working-side data signal DATAI. In this case, the control circuit 6 controls the division ratio N of the N divider 12 to be smaller than the division ratio M of the M divider 11 according to the value n. With this control, the frequency of the read clock signal CLKR, which is the read clock, becomes higher than the frequency of the spare clock signal CLKIS, which is the write clock, and the phase of the read clock advances with time with respect to the phase of the write clock. Read speed becomes faster than the write speed, the amount of delay by the FIFO memory 1 decreases with time, and the data signal D
The delay of the ATAR with respect to the working data signal DATAI decreases. As a result, when the delay is eliminated and the count value n output from the counting circuit 5 becomes zero, the control circuit 6 makes the dividing ratio N of the N divider 12 equal to the dividing ratio M of the M divider 11 and performs switching. The control signal is output to the switching circuit 7.

If the value n is larger than the threshold value in the threshold value determination, the control circuit 6 determines that the data signal DATAR is ahead of the working-side data signal DATAI. In this case, the control circuit 6 calculates the value f−n, and the N frequency divider 12
Is controlled to be greater than the frequency dividing ratio M of the M frequency divider 11 in accordance with the value f−n. By this control, the frequency of the read clock signal CLKR, which is the read clock, becomes lower than the frequency of the spare clock signal CLKIS, which is the write clock, and the phase of the read clock lags behind the phase of the write clock with time.
The reading speed from the O memory 1 becomes slower than the writing speed, the amount of delay by the FIFO memory 1 increases with time, and the working data signal DATA of the data signal DATAR is used.
The advance to I decreases. As a result, when the progress stops and the count value n output by the counting circuit 5 becomes zero,
The control circuit 6 makes the frequency division ratio N of the N frequency divider 12 equal to the frequency division ratio M of the M frequency divider 11, and outputs a switching control signal to the switching circuit 7.

When the switching control signal is input, the switching circuit 7 outputs the working data signal DATAI and the data signal DAT.
Since the relative delay time difference from the AR is within one clock cycle, the output data signal DATAO to be selectively output can be switched from the working data signal DATAI to the data signal DATAR without an instantaneous interruption.

The control circuit 6 sets the frequency division ratio N of the N frequency divider 12 smaller than the frequency division ratio M of the M frequency divider 11 so that the FI
The delay amount due to the FO memory 1 is reduced with time, and the frequency division ratio N is made larger than the frequency division ratio M so that the delay amount is increased with time to adjust the relative delay time difference between the working data signal DATAI and the data signal DATAR. However, instead of fixing the division ratio N of the N divider 12 and decreasing the division ratio N, the division ratio M of the M divider 11 is increased and the division ratio N is increased. Alternatively, the frequency division ratio M of the M frequency divider 11 may be controlled so that the frequency division ratio M is reduced.

[0022]

As described above, according to the present invention, the spare side data signal is temporarily written into the FIFO memory using the spare side clock signal as a write clock, and the output obtained by dividing the output of the variable frequency oscillator by the first divider is used as the output. A read-out clock generated by a phase-locked loop for comparing a phase of an output obtained by dividing a spare clock signal by a second frequency divider delays the spare data signal by reading the read clock generated by a phase locked loop, and a frame pulse of the delayed data signal And a leading / lag of the frame pulse of the working data signal are detected, and based on the detection result, the ratio between the dividing ratio of the first divider and the dividing ratio of the second divider is controlled.
Provided is a specific configuration of a synchronous switching device capable of performing line switching without instantaneous interruption, in which switching is performed after eliminating the relative delay time difference between a delayed data signal and a working data signal by increasing or decreasing the delay amount of the FO memory. There is an effect that can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 read control unit 2 FIFO memory 3, 4 frame synchronization circuit 5 counting circuit 6 control circuit 7 switching circuit 11 M frequency divider 12 N frequency divider 13 phase comparator 15 VCO

Claims (2)

(57) [Claims] 1. The method according to claim 1, further comprising adjusting a relative delay time difference between a working data signal transmitted through a working radio line and a protection data signal transmitted through a protection radio line to switch the working radio line. What is claimed is: 1. A synchronous switching device for switching a signal to a spare data signal without an instantaneous interruption, comprising: a first frequency divider for dividing an input clock signal by a dividing ratio M (M is an integer of 2 or more) and outputting the divided signal; And a division ratio N (N
Is an integer greater than or equal to 2) and outputs a second frequency divider;
A phase comparator for detecting a phase difference between signals output from the first and second frequency dividers, and an output phase controlled to reduce the phase difference detected by the phase comparator. A variable frequency oscillator that generates the clock signal and outputs the clock signal to the first frequency divider; a read control unit that reads the clock signal and outputs the clock signal as a read clock signal; A FIFO memory for sequentially writing a signal as a write clock and sequentially reading and outputting the read clock signal supplied from the read control unit as a read clock;
A spare-side frame synchronization circuit that outputs a spare-side frame pulse in frame synchronization with the data signal read by the memory;
A working-side frame synchronization circuit for outputting a working-side frame pulse in frame synchronization with the working-side data signal; and detecting the advance / delay of the backup-side frame pulse with respect to the working-side frame pulse and detecting the division ratio when the advancement is in progress. The value N / M, which is the ratio of the frequency division ratio N to M, is set to a value greater than 1 and smaller than 1 when the value is delayed.
Control means for controlling the frequency division ratio of at least one of the second frequency divider and the second frequency divider, and outputting a switching control signal when the timings of the working frame pulse and the protection frame pulse coincide with each other; And the working clock signal, which is a clock of the working data signal, the data signal read by the FIFO memory, and the read clock signal. The working data is input until the switching control signal is input from the control means. And a switching circuit for selecting and outputting a signal and the working clock signal and receiving the switching control signal and selecting and outputting the data signal read by the FIFO memory and the read clock signal when the switching control signal is input. Synchronous switching device. 2. A control circuit, comprising: a counting circuit that counts the read clock signal input during a period from the input of the working frame pulse to the input of the standby frame pulse and outputs a count value. , Based on the information on the frame length of the working-side data signal and the protection-side data signal and the count value output by the counting circuit, detects the advance / delay of the protection-side frame pulse with respect to the working-side frame pulse and proceeds. When the frequency division ratio N is larger than the frequency division ratio M and delayed, the frequency division ratio is smaller than the frequency division ratio M, and when there is no advance / delay, the frequency division ratio N is equal to the frequency division ratio M. 2. The synchronous switching device according to claim 1, further comprising a control circuit for controlling a frequency dividing ratio N of the frequency divider.