JP2713250B2 - CPU maintenance system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU maintenance system having a CPU and a service processor for performing a maintenance operation of the CPU, and more particularly to a CPU maintenance system for measuring and recording operating time and information on troubles occurring in the CPU. is there.

[0002]

2. Description of the Related Art CPUs used in computer systems
It is effective to know the next time as a measure for measuring the reliability of the (Central Processing Unit).

[0003] Mean time between failures, which is the average of the time during which a CPU has failed and has been operating without failure until the next failure occurs. Mean Time Between System Down, which is the average of the no-down time from when the system goes down until the next system down occurs.

In the conventional system, there is no method for directly measuring and monitoring the operating state / non-operating state of the CPU. Therefore, the service processor attached to the CPU measures the operating time of the service processor itself. The average failure interval and the average system down interval are calculated on the assumption that the measurement time matches the operation time of the CPU.

[0005]

However, since the operating state / non-operating state of the service processor and the operating state / non-operating state of the CPU do not always coincide with each other, the actual average failure interval and average system down interval of the CPU can be accurately determined. Had the disadvantage of not being able to know.

Accordingly, an object of the present invention is to provide a CPU maintenance system capable of accurately measuring the operating time of a CPU and calculating an accurate average failure interval and an average system down interval.

[0007]

According to the present invention, there is provided a CPU a and a service processor b for performing a maintenance operation thereof,
The CPUa is provided with a notifying means 1 for decoding a start instruction issued when the CPUa is started and a stop instruction issued when the CPUa is stopped, and outputting the same as a start signal and a stop signal to the service processor b. ing.

[0008] The service processor b has a counter 5 for accumulating and counting the operating time of the CPU a;
Counter control means 4 is provided for starting the counting of the counter 5 when a start signal is input and stopping the counting of the counter 5 when a stop signal is input.

The notifying means 1 comprises an instruction register 2 storing a start instruction or a stop instruction, and a decoder 3 for decoding the instruction output from the instruction register 2.

Further, when a failure occurs in the log recording unit 7 storing the log file and the CPUa, the failure information is read out, the counting of the counter 5 is stopped, and the failure information and the stopped counter 5 are stopped. It is preferable to provide a failure processing unit 6 that associates a count value and records the count value in a log file.

[0011]

The operation of the present invention is as follows. When the CPU is activated, the CPU issues a start instruction and outputs a start signal obtained by decoding the start instruction to the service processor. When the start signal is input to the service processor, the counter control means starts counting by the counter.

When the CPU is stopped, a stop instruction is issued from the CPU and a stop signal obtained by decoding the stop instruction is output to the service processor. When the stop signal is input to the service processor, the counter control means stops counting by the counter.

When a fault occurs in the CPU, the fault information is read from the CPU by the fault processing means, and the counting by the counter is stopped. The failure information is associated with the count value of the counter and recorded in a log file stored in the log recording unit.

[0014]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a CPU maintenance system as one embodiment of the present invention, and FIGS. 2 and 3 are operation diagrams showing the operation state.

The present system comprises a CPUa and this CPUa
And a service processor (SVP) b connected via a plurality of required interfaces. The service processor b performs a system operation and a maintenance operation on the CPU a.

A notifying means 1 for notifying the service processor b of a change in the operating state of the CPU a is provided in the CPU a. The notification means 1 includes an instruction register 2 for storing instructions to be sequentially executed by the CPUa, and a decoder 3 for decoding the instructions output from the instruction register 2.

The service processor b includes a control circuit 4,
A counter 5, a failure processing function unit 6, and a log recording unit 7 are provided.

As the instruction from the instruction register 2, a dedicated instruction for starting or stopping counting by the counter 5 in the service processor b is prepared.

The start instruction for starting the counting is executed by the CPU.
a is issued in the software processing for activating a. The start signal corresponding to the start command output from the decoder 3 is input to the control circuit 4 in the service processor b via the interface.

That is, by outputting this start signal to the service processor b, it is notified that the CPUa has transitioned from the operation stop state to the operation state, that is, that the CPUa has started operation.

The stop command for stopping the counting is as follows:
It is issued in software processing for stopping the CPUa. A stop signal corresponding to the stop instruction output from the decoder 3 is input to the control circuit 4 via the interface.

That is, by outputting this stop signal to the service processor b, it is notified that the CPUa has transitioned from the operating state to the operation stopped state, that is, that the operation of the CPUa has been stopped.

The control circuit 4 in the service processor b
It has a function as counter control means for starting and stopping the count of the counter 5 in response to the notification of the change in the operating state. Specifically, when a start signal from the CPUa is input, a count start signal is output to the counter 5, and when a stop signal is input from the CPUa, a count stop signal is output to the counter 5. I do.

The counter 5 accumulates and counts the operating time of the CPUa, for example, on an hourly basis. The counter 5 starts counting in response to a count start signal output from the control circuit 4. The counting is stopped by the stop signal.

When a failure occurs in the CPUa, the failure processing function unit 6 reads out the failure information,
Log file 8 in which the failure information and the count value at the time of the stop are stored in the log recording unit 7.
Has a function as a failure processing means for recording in

The log file 8 is mainly used to leave information on the occurrence of an abnormality in the CPUa as a history. The log file 8 is associated with all the failure information generated in the CPUa and the count value. It is to be recorded. Therefore, by analyzing the record information of the log file 8, it is possible to identify a failure location of the CPUa.

The operation of the present system having the above-described configuration will be described separately for a case where a change in the operating state is notified to the service processor b (FIG. 2) and a case where a failure occurs in the CPU a (FIG. 3).

<When there is a change in the operating state of the CPUa> When the software for activating the CPUa is executed, the instruction register 2 of the CPUa stores the CPUa during this processing.
A start command indicating that the operation has started is stored.

After this start instruction is decoded by the decoder 3, it is output as a start signal to the service processor b via the interface. In response to the input of the start signal, the control circuit 4 causes the counter 5 to start counting the accumulated time of the operating state of the CPUa.

When the software for stopping the CPUa is executed, the instruction register 2 of the CPUa is executed during this processing.
A stop command indicating that the operation of the CPUa has been stopped is stored in the storage area.

After the stop instruction is decoded by the decoder 3, it is output as a start signal to the service processor b via the interface. The control circuit 4 stops counting by the counter 5 in response to the input of the stop signal.

<When a Fault Occurs in CPUa> When a fault occurs in CPUa, fault information of CPUa is notified to fault processing function unit 6 in service processor b via an interface.

The failure processing function unit 6 reads the failure information from the CPUa as the CPU failure processing, and stops counting the accumulated time of the operating state by the counter 5. Then, the failure information and the count value of the counter are recorded in the log file 8 in the log recording unit 7.

The present invention is not limited to the above-described embodiment, but can be variously modified within the scope of the invention.

[0035]

According to the first to third aspects of the present invention, the CP
According to the start command output when U starts and the stop command output when the CPU stops, the counter starts and stops counting by the counter, so that the CPU itself is actually operating. Time can be measured accurately. This makes it possible to calculate an accurate average failure interval and an average system down interval.

According to the third aspect of the present invention, the failure information when the abnormality occurs in the CPU and the count value are recorded in the log file in association with each other, so that the location of the failure occurring in the CPU can be accurately specified. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a CPU maintenance system of the present invention.

FIG. 2 illustrates the operation, and is an operation diagram when a CPU notifies a service processor of a change in an operation state.

FIG. 3 is a diagram illustrating the operation, and is an operation diagram when a failure occurs in a CPU.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 notification means 2 instruction register 3 decoder 4 counter control means (control circuit) 5 counter 6 fault processing means (fault processing function unit) 7 log recording unit a CPU b service processor

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-14645 (JP, A) JP-A-63-280346 (JP, A) JP-A-63-253957 (JP, A) 109061 (JP, A) JP-A-63-313261 (JP, A) JP-A-2-7136 (JP, A) JP-A-2-231165 (JP, A) JP-A-2-245835 (JP, A) JP-A-4-105136 (JP, A) JP-A-5-225210 (JP, A) JP-A-6-214835 (JP, A) JP-A-56-27745 (JP, U) JP-A-3-17838 (JP, U)

Claims (3)

(57) [Claims] 1. A CPU maintenance system having a CPU and a service processor for performing a maintenance operation of the CPU, a start command issued when the CPU is started, and a CPU
The CPU is provided with a notifying means for decoding a stop instruction issued when the CPU is stopped, and outputting the same as a start signal and a stop signal to the service processor, and a counter for accumulating and counting the operating time of the CPU. And a counter control means for starting counting of the counter when the start signal is input and stopping the counting of the counter when the stop signal is input is provided in the service processor. Maintenance system. 2. The CPU maintenance system according to claim 1, wherein said notifying means comprises an instruction register storing a start instruction and a stop instruction, and a decoder for decoding an instruction output from said instruction register. 3. A log recording unit storing a log file,
When a fault occurs in the CPU, the service processor reads fault information and stops counting of the counter, and associates the fault information with the count value of the stopped counter and records it in a log file in a log file. The CPU maintenance system according to claim 1, wherein the CPU maintenance system is provided.