JP2712938B2 - Current source inverter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current source inverter used as a high frequency power supply for an induction heating device.

[0002]

2. Description of the Related Art FIG. 4 is a main circuit configuration diagram of a conventional current-type inverter disclosed in, for example, Japanese Patent Application Laid-Open No. 60-148338. In the figure, 1 is a transformer for a converter, 2 is a forward conversion circuit, 3 is a DC reactor, 4 is a reverse conversion circuit connected in a bridge, and each arm has a transistor 41a to 41d as a switching element and diodes 42a to 42b. It is composed of a series body. 5 is a capacitor 51 and a coil 52
And their constants are set so that they are in a parallel resonance state at the output frequency from the inverse conversion circuit 4.

Next, the operation will be described. Forward conversion circuit 2
Operates with a firing pulse from a forward conversion control circuit (not shown), receives a three-phase AC power supply from the converter transformer 1, and generates a DC voltage having a commanded value of six-phase full-wave rectification. The DC reactor 3 suppresses and smoothes the pulsation of the current so as to supply a constant current to the inverse conversion circuit 4. The inverse conversion circuit 4 receives the transistors 41a and 41d according to a timing signal from a not-shown inverse conversion timing control circuit.
And 41b and 41c perform an on / off switching operation, and output a single-phase alternating current having a frequency corresponding to the resonance frequency of the single-phase load 5. Then, the detected value is fed back to the forward conversion control circuit so that the firing pulse of the forward conversion circuit 2 is controlled so that the average value of the AC output voltage Va matches the predetermined command value.

FIG. 5 shows the DC mode of each arm and the waveforms of the output voltage Va and the output current Ia in order to particularly explain the switching operation of the inverter circuit 4. FIG. 5A shows a conduction mode in a period (a) of FIG. 5D showing a waveform, and a current flows through the transistors 41a and 41d and the diodes 42a and 42d. FIG. 5B shows a conduction mode in a period (b) of FIG. 5D, in which a current flows through all the transistors 41a to 41d and the diodes 42a to 42d. This period is from period (a) to period (c) described later.
During the commutation operation. FIG. 5C shows a conduction mode in a period (c) of FIG.
A current flows through 41c and diodes 42b and 42c. FIG.
The period (b ') of (D) is a period of the commutation operation from the period (c) to the period (a).

Therefore, the transistors 41a and 41d are energized for the period (b ') + (a) + (b),
b and 41c are controlled so as to be energized for a period (b) + (c) + (b '). Then, since the reverse voltage time is determined at the timing of commutation start, commutation is performed by timing control based on the zero point of the voltage, the reverse voltage time of the transistor is detected, and control is performed so that the value becomes a constant value. Is done. As a result, the output voltage Va applied to the single-phase load 5 is a sine wave,
The output current Ia is a trapezoidal wave, and is controlled so that the output current is advanced in phase with respect to the output voltage by an amount corresponding to the commutation margin angle.

[0006]

Since the conventional current-source inverter is configured as described above, for example, when this current-source inverter is used as a power source of an induction heating device for forging, a heating coil is not used. In some cases, an accident such as a short circuit may occur between the output terminals due to aging or the like. In this case, since the frequency of the parallel resonance changes abruptly, the control response in the reverse conversion timing control circuit with a constant reverse voltage time cannot follow, and when the transistor reaches a state in which the transistor performs an off operation with a delayed power factor, the transistor becomes very high. There is a problem that a reverse voltage is applied to cause a voltage breakdown.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a signal of an off operation is transmitted to a transistor at a timing different from a normal state due to a current phase due to a load accident or the like. It is an object of the present invention to obtain a current-source inverter that can safely stop the device without destroying the transistor.

[0008]

Means for Solving the Problems] current source inverter according to claim 1 of the present invention, the output current detecting means for detecting a current of the AC output, energization to detect the conduction period of the switching element from the output current has detected period detection hand stage, and if the upper <br/> Symbol timing signal for turning off the switching element during the conduction period of the switching element is output, the timing signal input to block the input of the timing signal to the switching element It has blocking means .

According to another aspect of the present invention, the load is a single-phase load which is in parallel resonance at a predetermined frequency of the output of the inverter circuit, and the timing signal is an output current with respect to an output voltage of the inverter circuit. Is set to have a predetermined advance phase.

[0010] In the current source inverter according to the third aspect of the present invention, the energization period detecting means may detect a steady state of the detected output current.
Storage unit for storing a predetermined amount subtracted value a value for each half-wave, and determines the period which the value of the output current is greater than the value of the upper <br/> Symbol storage device stored in the half-wave before the point And a discriminator that calculates an energization period from the period and outputs it as an energization signal.

[0011] Also <br/> a current type inverter according to claim 4, the timing signal input blocking means, operates the energization signal from the timing signal and the discriminator from the inverse conversion timing control circuit as an input signal it is <br/> made from the OR circuit.

According to a fifth aspect of the present invention, the current source inverter determines an energizing period for each polarity of the output current from an energizing signal of a discriminator, determines a period in which these energizing periods overlap with each other, and determines the period as a commutation period. A commutation abnormality detection and protection circuit that performs a protection operation by determining that an abnormality has occurred when this period exceeds a predetermined set value.

[0013] A current source inverter according to a sixth aspect of the present invention comprises the drive circuit having an off signal dead time element that does not operate for a predetermined period in response to the input of an off timing signal.

[0014]

In the current source inverter according to the present invention, the AC output current is detected, and the conduction period of the switching element is detected from the output current. Then, even if a timing signal of the OFF operation is output during this energization period, the signal is invalidated and the DC input is stopped. Further, a single-phase load in a parallel resonance state at the output frequency is connected to the inverse conversion circuit, and the inverter is operated at a predetermined advance phase. Moreover, the constant output current
A value obtained by subtracting the normal value by a predetermined amount is stored for each half-wave, an energization period is obtained from the half-wave and an output current, and is output as an energization signal. Then, as long as this energization signal is at the “H” level,
Even if the signal of the OFF operation is output, that is, even if the timing signal becomes the “L” level, the switching element continues the previous ON operation. Further, a period in which the energization periods of the respective polarities overlap is detected, and this period is regarded as a commutation period. When this period exceeds a set value, a protection operation is performed. Further, even if the timing signal to the drive circuit becomes the “L” level of the off operation for a short time due to noise penetration or the like, the switching element continues the on operation due to the off signal dead time element.

[0015]

[Embodiment 1] FIG. 1 is a circuit diagram showing a current source inverter according to one embodiment of the present invention. In the drawing, reference numerals 1 to 3 and 5 are exactly the same as those in the related art, and a description thereof will be omitted. The main circuit configuration of the inverse conversion circuit 4 is also the same as that shown in FIG. 4, so that the parts added in the present invention will be described in detail focusing on the transistor drive circuit system.

Reference numeral 43 denotes an inverse conversion timing control circuit for outputting a timing signal for turning on / off each of the transistors 41a to 41d, which is the same as a conventional one. 44 is a CT for detecting the output current Ia of the inverse conversion circuit;
Reference numerals a and 45b denote storages for storing the value of the output current Ia for each half-wave, the details of which will be described later. 46a and 46b are storage devices 45a and 45
A discriminator that detects the energization period of each transistor from the output of b and outputs it as an energization signal, the details of which will be described later. 47
Reference numerals a to 47d denote OR circuits, and reference numerals 48a to 48d denote base drive circuits for sending a base drive current to each transistor based on a timing signal.

Next, details of the configuration of the storage unit 45 and the discriminator 46 and their operations will be described with reference to FIG. FIG. 2 (1) shows the circuit configuration, and FIGS. 2 (2) to (5) show time charts. Fixed resistors 44a and 44b are connected to the control circuit zero potential point and the k and l terminals of CT44, respectively. As a result, with respect to the output current Ia shown in FIG. (2), the both terminals k, the l detection voltage indicated by v ₁ and v ₂ respectively in FIG. 2 (3) is obtained.

[0018] The storage unit 45a, as shown in FIG. 2 (1), the diode 81a, the fixed resistors 82a, 83a, and is composed of a capacitor 84a, the charge-discharge waveform of the detection voltage v ₂ is the capacitor 84a voltage v ₂₁ to be obtained.
Here, the discharge time constant of the CR elements 83a and 84a is set to several times the period of the oscillation frequency of the inverse conversion circuit 4. Therefore, the voltage v ₂₁ is the detected voltage v ₂ from the diode 81a of the forward drop further a value obtained by subtracting a fixed resistor 82a, 83a
, And has a waveform shown in FIG. 2 (4). Therefore, the stored voltage v ₂₁ is equal to the detected voltage v ₂
(Corresponding to the steady value of the output current Ia) slightly (a predetermined amount)
It is the value that was subtracted. Storage device 45b in the same configuration, the voltage v ₁₁ as a detection voltage v ₁ charge and discharge waveform to the capacitor 84b
Is obtained.

Next, the discriminator 46a detects the detection voltage v ₁ and the half-wave before.
Operating the voltage v ₂₁ stored by the voltage v ₂ as an input to the comparator 61a and the comparator 61a
And an inverter 62a connected to the output side of. Similarly, the discriminator 46b includes a comparator 61b and an inverter 62b. Comparator 61a outputs a signal the detection voltage v ₁ becomes "H" level only when the voltage v ₂₁ large. Voltage v ₂₁ is slightly lower than the detection voltage v ₁
Output value of the comparator 61a
The period during which the signal is at the “H” level is, as can be seen from FIG.
The period when only the transistors 41a and 41d are energized,
The remaining period in one cycle is the transit period including the commutation period.
The energization period of the stars 41b and 41c is reached. Therefore, the comparison
The signal A obtained by inverting the signal from the inverter 61a by the inverter 62a is as shown in FIG.
It can be regarded as a signal which becomes "H" level only during the energization period of b and 41c. Therefore, this signal A is applied to the transistor 41b,
It is sent to the subsequent OR circuit 47b (47c) as an energization signal of 41c. Similarly, the signal B obtained from the comparator 61b and the inverter 62b is regarded as a signal which is at "H" level only during the energizing period of the transistors 41a and 41d, as shown in FIG. 41
It is sent to the subsequent OR circuit 47a (47d) as an energization signal of d.

Thus, in this embodiment, the energizing signals A,
B, and an OR circuit 47a or the like operating these as one input thereof is provided. As described above, the transistor 41 has a transient delay power factor due to a short circuit or the like occurring in the single-phase load 5. Is turned off, that is, even if the signal from the inverse conversion timing control circuit 43 to the OR circuit 47 becomes "L" level, as long as the energizing signal is at "H" level, the OR circuit 47 The output signal from the device continues at "H" level. Therefore, since the transistor 41 does not perform an unreasonable off operation, there is no fear of destruction as in the related art. In this case, a state similar to the commutation failure of the inverse conversion circuit 4 is detected. This is detected by a protection circuit (not shown), the forward conversion circuit 2 is shut off by an overcurrent gate, and the DC input to the inverse conversion circuit 4 is cut off. The device can be safely stopped.

It should be noted that even during normal operation, the above-described OR circuit 47 is used.
And the like operate similarly, so that at the start of commutation, the off-timing signal sent to the transistor 41 that is currently energized is also blocked by the OR circuit 47, but this does not cause any problem. That is, the commutation operation is started by the ON timing signal sent to the transistor 41 which has been turned off, and the current of the transistor 41 which has been energized by the current from the single-phase load 5 decreases before long. It becomes zero and commutation is completed. Therefore, when the commutation is completed, the energization signal becomes “L”.
Since the level becomes the level, the above-mentioned blocking state by the OR circuit 47 is released, and the original OFF timing signal is sent to the transistor.

Embodiment 2 FIG. Reference numeral 6 in FIG. 2A denotes a commutation abnormality detection protection circuit to which a new function is added. In the figure, both outputs of the comparator 61a of the discriminator 46a and the comparator 61b of the discriminator 46b are sent to the OR circuit 47e, and the output is further inverted by the inverter 62c to become the signal C. As shown in FIG. 2 (5), the signal C is a signal which becomes "H" level only during a period that can be regarded as a commutation period. Therefore, when this period becomes abnormally long and the voltage of the set terminal S of the latch circuit 65 rises at a time constant determined by the variable resistor 63 and the capacitor 64 and reaches the threshold voltage, the latch circuit 65 is set, The output gives a commutation abnormality alarm, and commands an emergency stop of inverter operation.
Perform a series of protective actions to prevent accidents from spreading. This commutation abnormality detection is always performed when the delay power factor mode is set. Further, by adjusting the variable resistor 63 so that the time is set within the margin of the reverse voltage time, it becomes possible to detect, for example, the occurrence of an abnormality in the parallel resonance load at the preceding stage.

Embodiment 3 FIG. FIG. 3 shows still another embodiment of the present invention, and is an internal configuration diagram of a base driving circuit 48 corresponding to FIGS. 1 and 2 (1). In the figure,
11, 12 are terminals to which a timing signal passed through the OR circuit 47 is input, 71 is a photocoupler, 72 is a signal amplifier, 73 is a fixed resistor, 74 is a capacitor, 75 is an OR circuit, 76 is a base drive amplifier, 13, 14 Is a terminal for sending a base drive current to the transistor 41. The drive power supply for the signal amplifier 72 and the base drive amplifier 76 is supplied from a DC power supply circuit 78 that receives AC power through terminals 15 and 16 and a transformer 77.

Next, the operation will be described. The timing signals input from the terminals 11 and 12 are insulated by the photocoupler 71 and further amplified by the signal amplifier 72. The following circuit composed of the fixed resistor 73, the capacitor 74 and the OR circuit 75 delays only the tail of the input signal waveform for a fixed time, that is, functions as the OFF signal dead time element 7. The specific delay time is set to about several μsec.
Then, the signal subjected to this processing is amplified by the base drive amplifier 76 and becomes a base drive current, which is transmitted from the terminals 13 and 14 to the transistor 41. As described above, by providing the off signal dead time element 7, even if the input signal momentarily falls to the “L” level due to noise or the like, that is, the input signal goes to the off level, the error is turned off. Since no signal is sent to the transistor 41, destruction of the transistor due to noise or the like is reliably prevented. By appropriately setting the dead time, the detection voltages v ₁ and v ₂₁ , v ₂ and v ₁₁ in the storage device 45 and the discriminator 46 described above are obtained.
And stable transient operation can be ensured by compensating for a signal level instability based on a slight stationary time difference occurring between the two and a slight transient time difference occurring when the output current is increasing.

In each of the above embodiments, a bipolar transistor is used as a switching element of the inverse conversion circuit 4. However, the same effects as described above can be obtained even when GTO, IGBT, or the like is used. Further, the method of detecting the energization period of each transistor is not necessarily the same as that of the storage device 45 described above.
The method is not limited to the method using the discriminator 46, but may be a method in which a signal is digitized and obtained as a logical circuit.

[0026]

Since the present invention is configured as described above, even if an off-operation signal is sent to the switching element at a timing different from the normal state in relation to the current phase, the switching element is not affected. The device can be safely stopped without destroying the device. Further, the energization period of the element can be detected with a simple configuration, and furthermore, an abnormality in the commutation period can be detected to perform a necessary protection operation. Furthermore, since the off-signal dead time element is provided, even if the timing signal goes to the off-operation level for a short time due to noise or the like, the switching element is not affected by it.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a current source inverter according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing details of a storage unit 45 and a discriminator 46 in FIG. 1 and a time chart showing operation waveforms.

FIG. 3 is a circuit diagram showing an internal configuration of another embodiment of the base driving circuit 48 of FIG. 1;

FIG. 4 is a circuit diagram showing a conventional current source inverter.

FIG. 5 is a diagram for explaining a switching operation of the inverse conversion circuit 4;

[Description of Signs] 4 Inverting circuit 41 Transistor as switching element 43 Inverting timing control circuit 44 CT as output current detecting means 45 Memory 46 Classifier 47 OR circuit 48 Base drive circuit 5 Single-phase load 6 Commutation abnormality Detection protection circuit 61 Comparator 62 Inverter 7 Off signal dead time element

Claims (6)

(57) [Claims] 1. An inverting circuit comprising a plurality of self-extinguishing type switching elements for converting a DC input into an AC output having a predetermined frequency and supplying the AC output to a load, and an inverter for outputting a timing signal for turning on and off the switching elements. converting the timing control circuit, and the current source inverter including a driving circuit for sending a drive current to the switching element based on the timing signal, the output current detecting means for detecting the current of the AC output from the output current has detected energization period detection means to detect the conducting period of the switching element, and when the timing signal for turning off the switching element during the conduction period of the switching elements is output, the input of the timing signal to the switching element Taimin blocking
A current source inverter comprising a signal input blocking means . 2. The load is a single-phase load which is in parallel resonance at a predetermined frequency of the output of the inverter circuit, and the timing signal is set so that the output current has a predetermined advance phase with respect to the output voltage of the inverter circuit. 2. The current source inverter according to claim 1, wherein: 3. A storage unit for storing, for each half-wave, a value obtained by reducing a steady value of the detected output current by a predetermined amount ,
And the output current value is stored half a wave before the current time.
Current source inverter according to claim 2, characterized in that it consists of classifiers to be output as calculated energization signal energization time period from the storage device of the determined from larger period value the period that. 4. A timing signal input blocking means, the OR circuit operates an energizing signal from the timing signal from the inverse conversion timing control circuit and the discriminator as the input signal Tona
Current source inverter according to claim 3, wherein the that. 5. An energizing period for each polarity of an output current is determined from an energizing signal of a discriminator, and a period in which these energizing periods overlap with each other is determined. 5. The current-source inverter according to claim 3, further comprising a commutation abnormality detection protection circuit that performs a protection operation by determining an abnormality when the current value is exceeded. 6. The current source according to claim 3, wherein the drive circuit includes an off signal dead time element that does not operate for a predetermined period in response to the input of the off timing signal. Inverter.