JP2711389B2 - Integrated circuit manufacturing method - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to novel methods used in the manufacture of integrated circuits and semiconductor materials, and more particularly to novel conditioning methods intended to provide higher yields. BACKGROUND OF THE INVENTION In the manufacture of integrated circuits such as VLSI circuits, it is essential that the materials and the circuits to be fabricated be free of contamination. The large number of steps required for silicon wafer fabrication and circuit fabrication make contamination unavoidable unless significant care and manipulation is used. In silicon wafer manufacturing techniques, a silicon crystal is first grown. The crystals are harvested according to specifications and polished into cylindrical shapes. The cylinder is sliced into thin slices (ie, wafers), and the thickness of the slice depends on the diameter of the cylinder. The slices are then polished flat, etch polished and contoured, and then first cleaned. They are then etched, smoothed and cleaned again to remove any damage, polished, and then etched and cleaned. In a subsequent cleaning operation, the aqueous hydrogen peroxide solution is used to form a thin oxide coating (eg, about 25-30 Angstroms), and the article is cleaned with a pure aqueous solution. Thereafter, the wafer is packaged in an aseptic manner and shipped for circuit fabrication. Circuit fabrication is a complex operation requiring multiple steps in which a thin film material is overlaid on a silicon wafer. During the fabrication operation, the bare portions of the silicone wafer are exposed. These bare areas are an important functional part of the circuit, and if the bare silicon is contaminated in any way, it can result in circuit failure after undetected until the circuit is tested. For example, there is not only an important interface between bare silicon and a later silicon oxide layer on it,
There are also important interfaces during the silicon oxide polysilicon coating, between the polysilicon coating and the silicide or metal coating, and at many other interfaces. It is important that the bare silicon and the interface are uncontaminated. Certain types of contamination have a more negative effect on the function of the circuit element than others. In general, impact can be distinguished as either lithographic inhibition or chemical contamination. Particles that are about 10 to 30% of the minimum feature size and optically opaque can significantly alter the functional performance of circuit elements as they significantly alter the plate replication operation. Even smaller particles reduce yield if they chemically alter the film composition that is to be deposited on silicon or silicon wafers near the front surface. The biggest problems include degradation of the quality of the oxide used for the gate element or the polysilicon deposition used as the gate plate or contact. Even though these contamination problems do not immediately cause functional failure and loss of die yield, they can manifest themselves as oxide or contact reliability problems after the die is shipped to the customer. Typically, deionized water is used to clean the wafer during circuit fabrication, including cleaning of bare silicon and cleaning of material interfaces during device fabrication. Silicon wafers and the entire integrated circuit process are oxide tolerant. It is, therefore, an object of the present invention to provide a method for fabricating an integrated circuit in which a silicon wafer has an oxide layer as clean as possible over bare silicon and is most receptive to the next layer applied. Conditioning the wafer. It is another object of the present invention to provide a method of fabricating an integrated circuit in which the wafer is conditioned during critical interfaces to minimize problems at the interface and yield higher yields. Other objects of the present invention will become apparent as the description proceeds. SUMMARY OF THE INVENTION In producing an integrated circuit on a wafer,
Wafers should be exposed to at least 0.01 pp ozone to clean between bare silicon surfaces and various interfaces of circuit fabrication.
It has been found that conditioning by washing with pure water containing m is beneficial. We have found that such conditioning minimizes contamination by minimizing the attachment of organic matter and minimizes attachment of particles, including bacterial particles. According to the present invention, there is provided a method of making an integrated circuit having a number of patterned layers of thin film material on a semiconductor wafer, the method comprising the steps of: forming a material layer overlying the semiconductor wafer surface; Forming a photoresist layer thereon, exposing the photoresist to change its properties, removing a portion of the photoresist to form an uncovered portion of the material; The method is provided, comprising removing uncovered portions of the material, and then conditioning the article by washing with a pure aqueous solution containing at least 0.01 ppm of ozone. In an illustrative embodiment, between removing the portion of the photoresist and removing the uncovered portion of the material, the article contains at least 0.01 ppm of ozone.
It is conditioned with the contained pure aqueous solution. In the illustrated embodiment, the pure aqueous solution preferably contains 0.02 to 0.09 ppm ozone. Although the semiconductor wafer material is silicon, the method can be applied to fabricating integrated circuits on gallium arsenide. A more detailed description of the invention is provided in the following description and claims, and is illustrated in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a water treatment method constructed in accordance with the present invention for use in providing ozonated water for fabricating integrated circuits on silicon wafers. 2A to 2N are schematic sectional views of a silicon wafer during circuit fabrication. Detailed Description of Illustrative Embodiments In accordance with the present invention, ozonated and deionized pure water conditions a wafer during circuit fabrication to clean between the bare silicon surface and the various interfaces of the circuit fabrication. Used to FIG. 1 illustrates a system for providing ozonated deionized pure water. Referring to FIG. 1, raw water is pretreated in a pretreatment stage 10 using a multi-media filter and drug injection, and sent to a reverse osmosis module 14 via a pump 12 from which a degassing device, if necessary. Degassed by 16 and consist of cations, anions and mixed bed by re-pressure pump 18;
Alternatively, it is sent to the demineralization stage 20 consisting only of a mixed bed. Instead of a reverse osmosis module 14, a degassing stage 16, a repressurization pump 18, and a demineralization stage 20 consisting of a cation, anion and a mixed bed or consisting of a mixed bed alone, disclosed in U.S. Pat.No. 4,574,049 to Pitner. Such a double pass reverse osmosis system can be used. The demineralized water is sent to a deionized water storage tank 22, repressurized by a pump 24, and supplied to a mixed bed (typically composed of a mixture of cationic and anionic resin) polishing deionized exchange bottle 26. The deionized water from the mixed bed 26 is filtered by a post-filter 26, then passed through an ultraviolet lamp 30 for bacterial control and processed through a submicron filter 32. The post filter is used as a resin trap. The deionized pure water is supplied to a static gas injector 36 via a conduit 34. The deionized pure water is ozonated as follows. Pure oxygen gas is supplied through a conventional ozone generator 38 to manufacture an oxygen plus ozone at about 10psi (0.703kg / cm ^2).
Oxygen and ozone approximately 10psi is supplied to the compressor 40, where the gas is compressed to 85psi (5.976kg / cm ^2), and fed to a static gas injector 36. The compressed oxygen and ozone mix with the pure water in a static gas injector 36 to form ozonated water and provide the ozonated water on conduit 42. A bleed line 44 is provided to remove air bubbles from the ozonated water line. The deionized and ozonized pure water in conduit 42 is PVDF
It is supplied to the circuit fabrication area via piping. A dissolved ozone meter 46 is provided to monitor the ozone concentration.
We have determined that the concentration of ozone in deionized pure water should not be less than 0.1% to properly condition the wafer during circuit fabrication and prevent significant damage to the system's hard wafers.
It has been found that between 01 and 0.1 ppm is preferred. The deionized, ozonated pure water is recycled, but the ozone must be removed before returning the water to the deionized water storage tank 22. To this end, the ozonated water is treated through an ultraviolet lamp 48 to remove ozone for recirculation. The deionized pure water from which ozone has been removed is supplied to a deionized water storage tank 22 through a pressure control pipe 52 by a conduit 50. 2A-2N illustrate a portion of integrated circuit fabrication after receiving a clean silicon wafer. FIG. 2A illustrates a silicon wafer as delivered from a wafer manufacturer, wherein a silicon wafer 60 has been chemically grown,
Or coated with oxide 62 from a previous hydrogen peroxide treatment, which oxide typically has a thickness of 20 to 30 Å. Often circuit makers will remove this oxide to re-clean the silicon. On the other hand, the oxide layered silicon of FIG. 2A is placed in a furnace where it is oxidized to form a thermally grown oxide having a thickness of 100 to 400 Å (FIG. 2B).
Thereafter, a silicon nitride overlayer 66 (FIG. 2C) is formed in the furnace, and a photoresist layer 68 is formed over the silicon nitride layer 66. Photoresist 68 is irradiated and etched to leave uncovered portions of silicon nitride (see FIG. 2E). The article of FIG. 2E is then conditioned by washing it with deionized pure water containing 0.01 to 0.1 ppm of ozone, preferably 0.02 to 0.09 ppm. After such cleaning, portions of silicon nitride 66 that are no longer covered with photoresist 68 are etched to obtain the article illustrated in FIG. 2F, the photoresist is removed, and a portion of oxide 64 is removed. Exposed. The article is reconditioned by washing it with ozonated water. The article then grows to a thickness of about 2000 angstroms, a thick oxide film 70 that grows where the nitride has been removed.
Into a furnace to form This is illustrated in FIG. 2G. The article is then conditioned by washing with ozonated water and the silicon nitride is removed (see FIG. 2H). The article is rewashed with ozonated water, after which photoresist 68 is added (FIG. 2I),
Irradiated and then etched. As shown in Figure 2J,
This leaves a bare portion of the oxide, and the article is rinsed again by washing with ozonated water. As shown in FIG. 2K, the photoresist is removed and the oxide is etched into the bare silicon at various areas of the silicon surface. Thereafter, a gate oxide 72 is thermally grown, as shown in FIG. 2L, having a tolerance thickness in the range of 150 to 300 Angstroms. This gate oxide is typically the most important oxidation during the entire fabrication of the integrated circuit. Bare silicon is absolutely necessary to be properly conditioned for gate growth. To this end, the ozonated water clean treats, conditions, and provides perhaps several monolithic thin oxide layers to receive the bare oxide. After the gate is grown as shown in FIG. 2L, a layer 74 of polysilicon is deposited with reference to FIG. 2M. After the polysilicon is deposited, another photoresist layer 68 is formed, irradiated, etched, washed with ozonated water, and the uncovered polysilicon layer is etched,
After washing with ozonated water, the article shown in FIG. 2N is obtained. There may be numerous other layering steps during the fabrication of the circuit. In accordance with the present invention, a photoresist layer is typically formed, irradiated, etched, and the remainder washed with ozonated water, and then the non-photoresist covered material is etched, and then Will be washed with ozonated water. It is desirable that ozonated water be used for cleaning when the photoresist is removed, but it is most important that conditioning with ozonated water be done after materials that are no longer covered with photoresist are etched. It is. For this reason, it is most important that before forming the coating of the material, the conditioning step is carried out by washing with deionized pure water containing 0.01 to 0.1 ppm of ozone, preferably 0.02 to 0.09 ppm. We have discovered that conditioning with ozonated water, described immediately above, enhances the circuit fabrication process by allowing controlled oxidation of the interface with ultrapure reagents. Contamination is minimized by minimizing the adhesion of organic matter and particulate matter, including bacterial particles. Since very clean gas is injected into the ultrapure water, there is only minimal particulate matter. The purity of the ozone injected into the water is significantly higher than the purity of the chemicals found on circuit fabrication lines in prior art processing systems. While described and illustrated in the illustrative embodiments, it should be understood that various modifications and substitutions can be made by those skilled in the art without departing from the spirit and scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an ozonized deionized pure water production system, and FIGS. 2A to 2N are schematic sectional views of a silicon wafer during circuit fabrication. Reference numeral 60 denotes a silicon wafer, 64 denotes an oxide layer, 66 denotes a silicon nitride layer, 68 denotes a photoresist layer, 72 denotes a gate oxide, and 74 denotes a polysilicon layer.

Continuation of front page    (72) Inventors Peter, Elle, Tremont               Texas, United States 77379               Pulling, Terauren Lane 17630 (72) Inventor Arthur, Jay, Ackerman               63122, Missouri, United States               Oakwood, Woodside 303                (56) References JP-A-62-198127 (JP, A)                 61-164030 (JP, U)

Claims (1)

(57) [Claims] A method of making an integrated circuit having a number of patterned layers of thin film material on a silicon semiconductor wafer, comprising: forming a material layer overlying the semiconductor woofer surface; and a photoresist layer on the material layer Forming a portion of the material layer that is not covered by the photoresist; and removing a portion of the photoresist layer to form a portion of the material layer that is not covered by the photoresist. Removing the uncovered portion, removing the remaining portion of the photoresist, and then washing with a pure aqueous solution containing at least 0.01 ppm of ozone so that a thin oxide layer is formed on the surface of the wafer. A method of fabricating the integrated circuit. 2. Removing the portion of the photoresist and removing the uncovered portion of the material layer;
The method of claim 1 including the step of conditioning the wafer by washing with a pure aqueous solution containing at least 0.01 ppm of ozone. 3. The method of claim 1 wherein said pure aqueous solution contains 0.02 to 0.09 ppm of ozone. 4. The method of claim 1 wherein said material layer has a thickness of 20 to 400 Angstroms. 5. The method of claim 1 wherein said material layer comprises silicon nitride. 6. The method of claim 1 wherein said material layer comprises a thick film oxide. 7. When the uncovered portion of the material layer is removed, bare silicon is exposed before the conditioning step, and then the pure aqueous solution containing ozone so that a thin oxide layer is formed on the bare silicon. The method of claim 1 conditioned by washing with.