JP2708946B2 - Display power supply circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display power supply circuit for determining a signal level of a display signal applied to, for example, a simple matrix type liquid crystal display device.

2. Description of the Related Art In a simple matrix type liquid crystal display device, a plurality of row direction electrodes and a plurality of column direction electrodes are formed on a pair of transparent substrates so as to be orthogonal to each other. Each row direction electrode is scanned in the column direction by the column direction drive circuit, and the column direction electrode is scanned in the row direction by the row direction drive circuit, and a display signal is output for each column direction electrode. Such a row-direction drive circuit and a column-direction drive circuit perform the above-described operations based on a display signal and a scan signal from a CPU (central processing circuit).

A display voltage based on display data is applied to a liquid crystal layer interposed between the row direction electrodes and the column direction electrodes to realize a display operation. In order to improve the display characteristics of such a liquid crystal display device, a technique of generating a plurality of types of drive voltages in a liquid crystal display device and appropriately selecting a signal level of a display signal from the plurality of types of drive voltages has been used. I have.

FIG. 6 is a circuit diagram of a typical conventional display power supply circuit 101. The display power supply circuit 101 includes a variable resistor VR having one end connected to the display power supply voltage VE and, for example, five resistors R1, R2, R connected to the other end of the variable resistor VR and connected in series with each other.
3, R4, and R5. Variable resistor VR and resistors R1, R2, R3, R
The output from each connection point P1, P2, P3, P4, P5 between 4, R5 is input to the amplifiers A1, A2, A3, A4, A5, respectively, and the drive current is amplified, and each of the amplifiers A1, A2, A plurality of display voltages V1, V5, V3, V4, V6 different from each other are output from A3, A4, A5. The output from the connection point P6 on the ground potential side of the resistor R5 is used as the display voltage V2.

Such voltage dividing resistors R1, R2, R3, R4, R5 are called bleeder resistors, and are selected as resistance values r1, r1, r2, r1, r1. The optimum bias voltage value Vbi based on the resistance values r1, r2 and the resistances R1, R2, R3, R4, R5 is determined by the following first equation based on the drive duty DUTY of the liquid crystal display device.

That is, the liquid crystal display device of the conventional example is, for example, 1 / 146D
If it is UTY, from the first formula, Therefore, R2 = 9 · R1 (3), the voltage division ratio is 1: 1: 9: 1: 1, and the display voltage level is determined.

FIG. 7 is a view for explaining the operation of the conventional example. When the display power supply circuit 101 does not perform the contrast adjustment, the variable resistor VR is set to have a resistance value r = 0, and each of the display voltages V1 to
The maximum display voltage V1 of V6 matches the display power supply voltage VE. FIG. 7 (1) shows a case where the contrast is adjusted using the display power supply circuit 101 and the resistance value r of the variable resistor VR is set to a non-zero value. At this time, the maximum display voltage
V1 is lower than the display power supply voltage VE by the potential difference ΔV, and the remaining display voltages V2 to V6 are maintained at a ratio of the potential difference between the display voltages V1 to V6 of 1: 1: 9: 1: 1 as shown in the figure. The level has been reduced in the state.

On the other hand, if the display power supply circuit 101 does not adjust the contrast, the maximum display voltage V1 should match the display power supply voltage VE. However, based on the characteristics of the amplifier A1 shown in FIG. ~ 3V potential difference δV (however, as apparent from FIGS. 7 (1) and 7 (2), ΔV
It is known that a voltage level lowered by> δV) is output as a maximum value. Maximum display voltage in such a state
V1 is indicated by a broken line in FIG. 7 (2). As described above, when the maximum display voltage V1 undesirably lowers, the display voltage V1
There is a problem that the above-mentioned ratio regarding the potential difference between V6 and V5 does not hold and the display quality is reduced.

Problems to be Solved by the Invention As described above, this conventional example has a problem that the display quality is deteriorated without performing the contrast adjustment.

An object of the present invention is to solve the above-mentioned technical problems and to provide a display power supply circuit with significantly improved display quality.

Means for Solving the Problems The present invention provides (a) a display power supply circuit for determining a level of a display signal applied to a liquid crystal display element having a liquid crystal layer interposed between a pair of transparent substrates; (C) a variable resistor VR and a resistor R16 are connected in series at a connection point P17, and the variable resistor VR is connected to the one end of the DC power source; resistance
R16 is an adjustment signal output means connected to the other end of the DC power supply; (d) a first amplifier A16 to which the voltage at the connection point P17 is input as an input voltage; and (e) a plurality of voltage dividing resistors R11 to R11. R15 is a voltage divider configured in series, one end of the voltage divider is connected to the output of the first amplifier A16, and the other end of the voltage divider is connected to a grounded voltage divider. (F) The same number of second amplifiers A11 to A15 as the voltage dividing resistors R11 to R15
Wherein the second amplifier A11 of one of the second amplifiers A11 to A15
, The output voltage of the first amplifier A16 is input, and the remaining second amplifiers A12 to A15 are connected to the respective voltage dividing resistors R11 to R15.
(G) The first and second amplifiers A11 to A16 have input voltages of the display power supply voltage VE. When the input voltage is lower than the display power supply voltage VE, the output voltage corresponding to the input voltage lower than the display power supply voltage VE is output when the input voltage is lower than the display power supply voltage VE. A display power supply circuit for outputting.

According to the present invention, the level of the display signal applied to the liquid crystal display element is adjusted in the display contrast by the adjustment signal from the adjustment signal output means. The signal level of the adjustment signal from the adjustment signal output means is input to a first amplifier A16, and the output is divided by a voltage dividing means comprising a plurality of voltage dividing resistors R11 to R15 connected in series. . A plurality of signal level potentials different from each other from the first amplifier A16 and the voltage dividing means are supplied to the same number of second amplifiers A1 as the voltage dividing resistors R11 to R15.
These are input to 1 to A15, respectively.

At this time, if the adjustment signal output means does not adjust the contrast, and therefore the display power supply voltage VE, which is the reference potential, is output as it is, the output level of the first amplifier A16 saturates, for example, from the reference potential VE. The voltage drops by a predetermined voltage δV. First amplifier to which adjustment signal is supplied
If the amplification factor of A16 is appropriately selected, the highest signal level potential V11 among a plurality of mutually different signal level potentials from the second amplifiers A11 may be adjusted when the contrast adjustment is not performed in the adjustment signal output unit. It is possible to prevent a situation in which the display quality is undesirably reduced to lower the display quality.

When the input voltage is equal to the display power supply voltage VE as described later, the first and second amplifiers A11 to A16
Output an output voltage lower by a predetermined voltage δV from VE,
When the input voltage is lower than the display power supply voltage VE, an output voltage corresponding to the input voltage lower than the display power supply voltage VE is output. Therefore, when the contrast adjustment is not performed as described above, the output of the first amplifier A16 becomes the display power supply voltage V
An output voltage that is lower than E by a predetermined voltage δV is output, and this output voltage is input to the one second amplifier A11 of the plurality of second amplifiers A11 to A15, and the one second amplifier A11 Outputs an output voltage corresponding to an input voltage lower than the display power supply voltage VE, and outputs the remaining second amplifier.
The output voltages of the first amplifier A16 are divided and supplied to A12 to A15, and thus the remaining second amplifiers A12 to A15
Is lower than the display power supply voltage VE and outputs an output voltage corresponding to the input voltage. Thus the first
And the input voltage of the second amplifiers A11 to A16 is equal to the display power supply voltage VE.
In the configuration having a characteristic of outputting an output voltage lower than the display power supply voltage VE by a predetermined voltage δV, the output voltages of the second amplifiers A11 to A15 are accurately divided at a desired voltage division ratio. Pressed values can be obtained.

Embodiment FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a block diagram of a data processing device 2 using a common drive circuit 1, and FIG. FIG. The data processing device 2 has a so-called notebook size, and the first operation unit 3 and the second operation unit 4 are configured to be freely opened and closed by a coupling unit 5. The second operation unit 4 includes a cursor key 6, a function setting key 7, a character input key 8, a numeric key 9, and the like. On the other hand, on the first operation unit 3, a so-called transparent touch key 10 and a liquid crystal display device 11 are arranged.

Such a data processing device 2 includes, for example, a CPU (central processing circuit) 12 including a microprocessor or the like.
The CPU 12 has the transparent touch key 10 and the second
A RAM (random access memory) 13 to which each key input means of the operation unit 4 is connected and which is used as a storage area for various input data and a working area for data during operation, and a CPU
A ROM (read only memory) 14 in which programs for defining the control operations of 12, font data for display, calendar data, and the like are stored is connected.

Further, the CPU 12 has a timing circuit 15 for timing, a common drive circuit 1 for controlling the display operation of the liquid crystal display device 11 as described later, and a common drive circuit 1 based on a contrast signal from the common drive circuit 1. The liquid crystal power supply circuit 16 is connected to a liquid crystal power supply circuit 16 that changes the operating state / stop state according to a control signal from the CPU 12. The common drive circuit 1 has a plurality (8 in this embodiment).
), And controls the display state of the liquid crystal display device 11 together with the common drive circuit 1. The liquid crystal display device 11 has a common electrode 1 on a pair of transparent substrates 11a and 11b.
1c, a segment electrode 11d is formed, and a liquid crystal layer 11e is interposed therebetween.

A block diagram of the common drive circuit 1 is shown in FIG. The common drive circuit 1 is supplied with a write / read control signal R / W, a clock signal φ, a busy signal BY, a chip enable signal CE, and the like from the CPU 12, and a control circuit 19 to which address data AD, display data DI, and the like are supplied. Is provided. The display data DI is input through the buffer 20. Further, the common drive circuit 1 outputs a frame signal
FR, a control signal DIS that controls ON / OFF of display by the segment electrode, and a clock signal LCK are used as segment drive circuits.
Output to 17. As described above, such a data processing device 2 is a notebook-sized portable device, and
The various reference voltages necessary for the operation of are generated from the power supply circuit 26 connected to the battery 25.

A data processing circuit 21 is connected to the control circuit 19 and the CPU 12
After performing a predetermined logical operation (such as SET, AND, OR, XOR, etc.) on the address data and display data transferred from the device, the data is transmitted to the segment drive circuit 17. The memory control circuit 22 determines to which of the segment driving circuits 17 the address data sent from the CPU 12 is to be transferred, and generates a relative address in any of the selected segment driving circuits 17. The timing generation circuit 23 generates a clock signal used for various arithmetic processing in the common drive circuit 1 and the like, and receives a reference clock signal from the oscillator 24.

The common signal control circuit 27 and the common-side decoder 28 use the clock signal generated by the timing generation circuit 23 to generate a common signal supplied to the common electrode of the liquid crystal display device 11. The control circuit 19 is connected to a window processing circuit 29 having a configuration and an operation as described later.The contrast adjustment circuit 46 stores the display density on the liquid crystal display device 11, and the density data is set from the CPU 12. . The contrast adjustment of the liquid crystal display device 11 is performed by the liquid crystal power supply circuit 16 shown in FIG. 2 based on the density data in the contrast adjustment circuit 46, and the liquid crystal power supply potential from the liquid crystal power supply circuit 16 is taken into the common drive circuit 1. LCD voltage input section for
17 are provided.

FIG. 4 is a circuit diagram showing a configuration example of the liquid crystal power supply circuit 16. The liquid crystal power supply circuit 16 includes a variable resistor VR having a resistance value r having one end connected to the display power supply voltage VE, and the other end of the variable resistor VR is grounded via a resistor R16 having a resistance value r3. An amplifier A16 is connected to a connection point P17 between the variable resistor VR and the resistor R16, and its output is connected to one end of a series circuit of, for example, five resistors R11 to R15. The other end of this series circuit is grounded. Also resistance
Amplifiers A11, A12, ..., A15 are respectively connected to connection points P11, P12, ..., P16 between both ends of R11 to R15 and each other.

The output of each of these amplifiers A11 to A15 and the connection point P17
Output the display voltages V11, V15, V13, V14, V16, and V12, respectively. Therefore, the magnitude relationship between each of the display voltages V11 to V16 and the display power supply voltage VE is expressed by the following equation (4).

VE ≧ V11>V15>V13>V14>V16> V12 (4) The resistors R11 to R15 are bleeder resistors for voltage division, and the resistance values are r1, r1, r2, r1, r1 as described in the conventional example. Is chosen respectively. These resistance values r1 and r2 and the resistances R11 to R1
The optimum bias value Vbi between 5 is given by the first formula when the common drive circuit 1 of this embodiment has 1/146 DUTY as in the description of the conventional example. Accordingly, the second and third equations are satisfied, and the display voltages V11, V15, V13, V14,
The ratio of the potential difference between V16 and V12 is selected to be 1: 1: 9: 1: 1 as in the conventional example.

FIG. 5 is a diagram for explaining the operation of the present embodiment. When the contrast is adjusted in the liquid crystal power supply circuit 16, the resistance value r of the variable resistor VR is set to a value other than 0, and
The specific power supply voltage VE is divided by the resistance value ratio r: r3 of the resistor R16 and the current is amplified by the amplifier A16, and the output voltage level is divided by the resistors R11 to R15, and the amplifiers A11 to A15 , And is output as the display voltages V11 to V12. This state is shown in FIG. 5 (1). The maximum display voltage V11 is lower than the display reference voltage VE by ΔV (r).

Next, when the liquid crystal power supply circuit 16 does not perform contrast adjustment, the resistance value r of the variable resistor VR is set to 0. At this time, the voltage at the connection point P17 becomes the display power supply voltage VE, this level is output via the amplifier A16, and this output is divided by the resistors R11 to R15. Here, the amplifier A16
, The output has a value lower than the display power supply voltage VE by, for example, a potential difference δV of about 2 to 3 V, but the resistors R11 to R15 divide the voltage based on the output voltage. When the input voltage is equal to the display power supply voltage VE as described above, the amplifiers A11 to A16 output an output voltage lower than the display power supply voltage VE by a predetermined voltage δV. When the input voltage is lower than the display power supply voltage VE, the first and second amplifiers A11 to A16 output an output voltage corresponding to the input voltage lower than the display power supply voltage VE.

Therefore, output from the connection points P11 to P16, the amplifier
The display voltages V11 to V obtained by current amplification in A11 to A15
Among 12, the situation where only the maximum display voltage V11 undesirably lowers the level can be prevented. That is, as shown in FIG. 5 (2), when the maximum display voltage V11 is lower than the display reference voltage VE when the resistance value r of the variable resistor VR is 0, the remaining display voltages V15 to V12 become the potential difference ratio. The level is reduced to the extent corresponding to.

As described above, in the present embodiment, of the display voltages V11 to V12, for example, only the maximum display voltage V11 undesirably fluctuates, and the ratio relationship between the display voltages V11 to V12 is not maintained, and the display quality is reduced. Deterioration is prevented.

As described above, according to the present invention, when the adjustment signal output unit does not perform the contrast adjustment and therefore the display power supply voltage VE which is the reference potential is output as it is, the first amplifier A1
6 is a predetermined voltage δV from the reference potential.
In this case, if the amplification factor of the first amplifier A16 to which the adjustment signal is supplied is appropriately selected, the highest signal level potential V11 among a plurality of mutually different signal level potentials from the respective second amplifiers A11 becomes When the contrast adjustment is not performed in the adjustment signal output unit, it is possible to prevent a situation in which the display quality is undesirably reduced and deteriorated.

Thus, when the input voltages of the first and second amplifiers A11 to A16 are equal to the display power supply voltage VE, the output voltage is lower than the display power supply voltage VE by a predetermined voltage δV, and the input voltage is lower than the display power supply voltage VE. Low, the output voltage corresponding to the input voltage lower than the display power supply voltage VE is output.
When the second amplifiers A11 to A16 are used, as described above, even when the contrast adjustment is not performed, it is possible to accurately obtain an output voltage having a desired voltage division ratio from each of the plurality of second amplifiers A11 to A15. it can.

[Brief description of the drawings]

1 is a block diagram of a common drive circuit 1 according to one embodiment of the present invention, FIG. 2 is a block diagram of a data processing device 2, FIG. 3 is a plan view of the data processing device 2, and FIG. FIG. 5 is a block diagram of a liquid crystal power supply circuit 16 according to one embodiment, FIG. 5 is a diagram for explaining the operation of the present embodiment, FIG. 6 is a block diagram of a typical conventional display power supply circuit 101, and FIG. FIG. 1 common drive circuit, 2 data processing device, 16
Liquid crystal power supply circuit, A11 to A16 …… Amplifier, VR …… Variable resistance

Claims (1)

(57) [Claims] 1. A display power supply circuit for determining a level of a display signal applied to a liquid crystal display element having a liquid crystal layer interposed between a pair of transparent substrates, wherein (b) one end derives a display power supply voltage VE. (C) a variable resistor VR and a resistor R16 are connected in series at a connection point P17, and the variable resistor VR is connected to the one end of the DC power source;
R16 is an adjustment signal output means connected to the other end of the DC power supply; (d) a first amplifier A16 to which the voltage at the connection point P17 is input as an input voltage; and (e) a plurality of voltage dividing resistors R11 to R11. R15 is a voltage divider configured in series, one end of the voltage divider is connected to the output of the first amplifier A16, and the other end of the voltage divider is connected to a grounded voltage divider. (F) The same number of second amplifiers A11 to A15 as the voltage dividing resistors R11 to R15
The output voltage of the first amplifier A16 is input to one of the second amplifiers A11 to A15, and each of the remaining second amplifiers A12 to A15 has a voltage dividing resistor. R11-R15
(G) the first and second amplifiers A11 to A16 receive the divided voltages of the mutual connection points P12 to P15, respectively. When equal, outputs an output voltage lower than the display power supply voltage VE by a predetermined voltage δV, and when the input voltage is lower than the display power supply voltage VE, outputs an output voltage corresponding to the input voltage lower than the display power supply voltage VE. A display power supply circuit.