JP2706352B2 - Photoelectric conversion device using compound semiconductor polycrystalline thin film - Google Patents

Photoelectric conversion device using compound semiconductor polycrystalline thin film

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Publication number
JP2706352B2
JP2706352B2 JP2116810A JP11681090A JP2706352B2 JP 2706352 B2 JP2706352 B2 JP 2706352B2 JP 2116810 A JP2116810 A JP 2116810A JP 11681090 A JP11681090 A JP 11681090A JP 2706352 B2 JP2706352 B2 JP 2706352B2
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Japan
Prior art keywords
semiconductor layer
type semiconductor
transparent electrode
solid solution
photoelectric conversion
Prior art date
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Expired - Fee Related
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JP2116810A
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Japanese (ja)
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JPH0414268A (en
Inventor
章二 森田
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Mitsubishi Heavy Industries Ltd
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Mitsubishi Heavy Industries Ltd
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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/541CuInSe2 material PV cells

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  • Light Receiving Elements (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、化合物半導体多結晶薄膜を用いた光電変換
素子に関する。
Description: TECHNICAL FIELD The present invention relates to a photoelectric conversion element using a compound semiconductor polycrystalline thin film.

〔従来の技術〕 従来のP型化合物半導体CuInSe2を光吸収層とする薄
膜型光電変換素子は、通常、第3図に示す基本構造を有
する。第3図において、6はガラスあるいはセラミック
スなどからなる基板であり、この基板6上にはモリブデ
ンMoあるいはニッケルNiなどからなる電極7が形成され
ている。電極7上には物理的蒸着法(多元蒸着法、スパ
ッタ法など)、スプレー法あるいはメッキ法などの手法
により、P型半導体層8としてCuInSe2が形成されてい
る。さらにP型半導体層8上には、前記手法によりn型
半導体層9が形成されている。n型半導体層9には硫化
カドミウムCdS、あるいは硫化カドミウムCdS−硫化亜鉛
ZnS固溶体が用いられる。固溶体を用いた場合、その組
成は通常n型半導体層9内において均一である。P型半
導体層8およびn型半導体層9の厚さは、製作条件によ
るが、通常、それぞれ2.0〜4.0μmおよび1.0〜2.0μm
である。n型半導体層9上には、真空蒸着法あるいは熱
化学的蒸着法(以下熱CVD法という)などの手法により
インジウムInと錫Snの混合酸化物(以下ITOという)あ
るいは酸化錫SnO2などからな透明電極10が形成されてい
る。さらに、透明電極10上には、アルミニウムAlあるい
は金Auなどからなる集電用のグリッド電極11が形成され
ている。
[Prior Art] A conventional thin film photoelectric conversion element using a P-type compound semiconductor CuInSe 2 as a light absorbing layer usually has a basic structure shown in FIG. In FIG. 3, reference numeral 6 denotes a substrate made of glass, ceramics, or the like, on which an electrode 7 made of molybdenum Mo, nickel Ni, or the like is formed. CuInSe 2 is formed as the P-type semiconductor layer 8 on the electrode 7 by a physical vapor deposition method (multi-source vapor deposition method, sputtering method, or the like), a spray method, a plating method, or the like. Further, an n-type semiconductor layer 9 is formed on the P-type semiconductor layer 8 by the method described above. Cadmium sulfide CdS or cadmium sulfide CdS-zinc sulfide is used for the n-type semiconductor layer 9.
A ZnS solid solution is used. When a solid solution is used, its composition is usually uniform in the n-type semiconductor layer 9. The thicknesses of the P-type semiconductor layer 8 and the n-type semiconductor layer 9 depend on manufacturing conditions, but are generally 2.0 to 4.0 μm and 1.0 to 2.0 μm, respectively.
It is. On the n-type semiconductor layer 9, a mixed oxide of indium In and tin Sn (hereinafter referred to as ITO) or tin oxide SnO 2 is formed by a method such as a vacuum evaporation method or a thermochemical evaporation method (hereinafter referred to as a thermal CVD method). Transparent electrode 10 is formed. Further, on the transparent electrode 10, a current collecting grid electrode 11 made of aluminum Al, gold Au, or the like is formed.

第3図に示した構成の素子において、光は透明電極10
側から入射し、主としてP型半導体層8内で吸収され
る。光を吸収したP型半導体層8内では電子および正孔
が発生するが、これらはPn接合によって形成された内部
電界によって分極され、電子はn型半導体側へ、正孔は
P型半導体側へそれぞれ移動し、電極を通じて外部回路
に取り出される。
In the device having the structure shown in FIG.
The light enters from the side and is mainly absorbed in the P-type semiconductor layer 8. Electrons and holes are generated in the P-type semiconductor layer 8 which has absorbed light, but these are polarized by the internal electric field formed by the Pn junction, and the electrons are directed to the n-type semiconductor and the holes are directed to the P-type semiconductor. Each moves and is taken out to an external circuit through an electrode.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

従来の基本構成を第3図に示した光電変換素子におい
ては、下記の課題があった。
The photoelectric conversion device having the conventional basic configuration shown in FIG. 3 has the following problems.

(1) CuInSe2および硫化カドミウムCdSの薄膜は、通
常、強い配向性を示す。したがって、CuInSe2と硫化カ
ドミニウムCdS多結晶薄膜でPn接合を形成した場合、そ
れぞれの面間隔に差があるため、局所的な歪みが生じ、
Pn接合面付近で欠陥が多数生成される。このため、光発
生した電子および正孔がこれらの欠陥を捕獲され、電流
には寄与しなくなるため、素子特性が低下する。
(1) Thin films of CuInSe 2 and cadmium sulfide CdS usually show strong orientation. Therefore, when a Pn junction is formed of CuInSe 2 and cadmium sulfide CdS polycrystalline thin film, there is a difference between the respective plane distances, so local distortion occurs,
Many defects are generated near the Pn junction surface. Therefore, the light-generated electrons and holes are trapped by these defects and do not contribute to the current, so that the device characteristics are degraded.

(2) n型半導体層は、光入射層であるとともに、光
発生した電子を透明電極へ伝える機能を有する。したが
って、n型半導体層は禁制帯幅および導電率ともに大き
いことが望ましい。n型半導体層として硫化カドミウム
CdSを用いた場合、禁制帯幅を拡げるため、通常、硫化
亜鉛ZnSを固溶する。しかし、この手法の場合、硫化亜
鉛ZnS固溶量の増大とともに禁制帯幅は広がるが、同時
に導電率が低下する。したがって均一組成の膜を形成し
た場合、禁制帯幅と導電率ともに増大させることはでき
ない。
(2) The n-type semiconductor layer is a light incident layer and has a function of transmitting light-generated electrons to the transparent electrode. Therefore, it is desirable that both the forbidden band width and the conductivity of the n-type semiconductor layer be large. Cadmium sulfide as n-type semiconductor layer
When CdS is used, zinc sulfide ZnS is usually dissolved in a solid solution to widen the forbidden band. However, in the case of this method, the forbidden band width increases with an increase in the amount of solid solution of zinc sulfide ZnS, but at the same time, the conductivity decreases. Therefore, when a film having a uniform composition is formed, both the forbidden band width and the conductivity cannot be increased.

本発明は、上記の課題を解決するためになされたもの
であり、良好なPn特性を有する化合物半導体多結晶薄膜
を用いた光電変換素子を提供することを目的としてい
る。
The present invention has been made to solve the above problems, and has as its object to provide a photoelectric conversion element using a compound semiconductor polycrystalline thin film having good Pn characteristics.

〔課題を解決するための手段〕[Means for solving the problem]

本発明に係わる光電変換素子は、光入射側の窓層を形
成し硫化カドミウムCdS−硫化亜鉛ZnS固溶体よりなるn
型半導体層、同半導体層の光が入射する一方の面に接合
された透明電極、および上記n型半導体層の他方の面に
接合されたP型半導体層を備え、上記n型半導体層の硫
化亜鉛ZnSの固溶量をP型半導体層との接合面に近い側
で大きくし透明電極との接合面に近づくにつれて小さく
なるようにその組成を厚さ方向に傾斜させたことを特徴
としている。
The photoelectric conversion element according to the present invention forms a window layer on the light incident side, and is formed of a cadmium sulfide CdS-zinc sulfide ZnS solid solution.
A n-type semiconductor layer, a transparent electrode bonded to one surface of the semiconductor layer on which light is incident, and a p-type semiconductor layer bonded to the other surface of the n-type semiconductor layer. The composition is characterized in that the composition thereof is inclined in the thickness direction so that the amount of solid solution of zinc ZnS is increased on the side close to the joint surface with the P-type semiconductor layer and becomes smaller as the joint surface approaches the joint surface with the transparent electrode.

〔作用〕[Action]

上記において、n型半導体層はP型半導体層との接合
面付近における硫化亜鉛ZnS固溶量が調整され、P型半
導体層とのn型半導体層との面間隔の差が小さくなり格
子の整合性が改善されているため、局所的な歪みが緩和
される。この結果、Pn接合界面付近で生成する欠陥が減
少し、光発生した電子および正孔のうちこれらの欠陥で
捕獲されるものが減少し、外部回路に取り出される電流
が増大する。
In the above, the amount of solid solution of zinc sulfide ZnS in the vicinity of the junction surface between the n-type semiconductor layer and the p-type semiconductor layer is adjusted, so that the difference in plane spacing between the p-type semiconductor layer and the n-type semiconductor layer becomes small, and the lattice matching becomes Due to the improved properties, local distortion is reduced. As a result, the number of defects generated near the Pn junction interface decreases, the number of electrons and holes generated by light, which are captured by these defects, decreases, and the current taken out to an external circuit increases.

また、n型半導体層の形成において透明電極との接合
面に近づくにつれて硫化亜鉛ZnS固溶量を減少させてい
るため、組成の傾斜とともに導電率が増大する。この結
果、素子の内部抵抗が低下し、半導体層の内部で発生し
た電子が効率的に透明電極に流れるようになる。
Further, in forming the n-type semiconductor layer, the amount of solid solution of zinc sulfide ZnS decreases as approaching the bonding surface with the transparent electrode, so that the conductivity increases with the inclination of the composition. As a result, the internal resistance of the element decreases, and electrons generated inside the semiconductor layer efficiently flow to the transparent electrode.

上記により、本発明の変換素子においては良好なPn接
合が形成され、半導体内で光発生した電子および正孔が
効率的に外部回路に取り出されるため、短絡電流および
曲線因子の増大を期待することができる。
As described above, in the conversion element of the present invention, a good Pn junction is formed, and electrons and holes generated by light in the semiconductor are efficiently extracted to an external circuit. Therefore, an increase in short-circuit current and fill factor is expected. Can be.

〔実施例〕〔Example〕

本発明の一実施例を第1図に示す。 One embodiment of the present invention is shown in FIG.

第1図に示す本実施例は、ガラスからなる基板1、同
基板1上に形成され厚さ2000Åの酸化錫SnO2からなる透
明電極2、同透明電極2上に形成され硫化亜鉛ZnSの固
溶量が上記透明電極2との接合面に近づくに従い小さく
なり硫化カドミウムCdSと硫化亜鉛ZnSからなるn型半導
体層3、同n型半導体層3上に形成され銅Cu、インジウ
ムIn及びセレンSe−銅Cu合金からなるP型半導体層4、
および同P型半導体層4上に形成され厚さ0.5μmのモ
リブデンMoからなる金属電極5を備えている。
In this embodiment shown in FIG. 1, a substrate 1 made of glass, a transparent electrode 2 formed on the substrate 1 and made of tin oxide SnO 2 and having a thickness of 2000 °, and a solid solution of zinc sulfide ZnS formed on the transparent electrode 2 are formed. The dissolution amount decreases as approaching the bonding surface with the transparent electrode 2, and the n-type semiconductor layer 3 made of cadmium sulfide CdS and zinc sulfide ZnS is formed on the n-type semiconductor layer 3, and the copper Cu, indium In and selenium Se— A P-type semiconductor layer 4 made of a copper-Cu alloy,
And a metal electrode 5 made of molybdenum M o thickness 0.5μm is formed on the P-type semiconductor layer 4.

上記本実施例の形成手順を以下に説明する。 The forming procedure of the present embodiment will be described below.

まず、ガラスからなる基板1上に熱CVD法により厚さ2
000Åの酸化錫SnO2からなる透明電極2を形成する。透
明電極2が成膜されたガラス基板1は、アセトン、メタ
ノールおよび純水中で順次超音波洗浄した後、乾燥し
た。
First, on a substrate 1 made of glass, a thickness 2
A transparent electrode 2 made of tin oxide SnO 2 of 000 ° is formed. The glass substrate 1 on which the transparent electrode 2 was formed was subjected to ultrasonic cleaning in acetone, methanol and pure water sequentially, and then dried.

上記透明電極2上に形成するn型半導体層3およびP
型半導体層4は、物理的蒸着法の1つである高周波スパ
ッタリング法により形成した。n型半導体層3の形成に
ついては、上記洗浄した透明電極2付きのガラス基板1
に高周波スパッタ装置に設置して5.0×10-7Torrまで排
気し、基板1を所定の温度に加熱した後、チャンバーに
アルゴンAr導入して圧力が5.0×10-3Torrになるように
流量を調整する。続いて、原子を蒸発するターゲットと
基板1、の間を遮断した状態とするためにシャッターを
閉じてプラズマを形成し、約5分間ターゲット表面を洗
浄化した。次に、高周波電力を所定の値に設定した後シ
ャッターを開け、所定時間スパッタリングを行い、n型
半導体層3を形成した。n型半導体層3は、硫化カドミ
ウムCdS焼結体(純度99.99%、直径101.6mm、厚さ5mm)
および硫化亜鉛ZnS焼結体(純度99.99%、直径101.6m
m、厚さ5mm)をターゲットとし、基板1を回転させなが
ら同時にスパッタリングすることにより形成した。この
とき、両ターゲットの電極に負荷する高周波電力を成膜
時間に合わせて制御し、n型半導体層3における厚さ方
向の硫化亜鉛ZnSの固溶量を第2図に示すように、P型
半導体層4との接合面に近い側で大きく、透明電極2と
の接合面に近づくにつれて小さくなるように変化させ
た。P型半導体層4を構成するCuInSe2との面間隔の整
合性を考慮すると、P型半導体層4との接合面(第2図
においてd=0)付近の硫化亜鉛ZnSの固溶量は、5〜1
0%程度が適当であると考えられる。また、素子の内部
抵抗を低下させるため、透明電極2との接合面(第2図
においてd=d1)付近の硫化亜鉛ZnSの固溶量は1〜3
%が適当であると考えられる。
N-type semiconductor layer 3 and P formed on transparent electrode 2
The mold semiconductor layer 4 was formed by a high frequency sputtering method, which is one of the physical vapor deposition methods. Regarding the formation of the n-type semiconductor layer 3, the glass substrate 1 with
The substrate 1 was evacuated to 5.0 × 10 −7 Torr and heated to a predetermined temperature, and argon was introduced into the chamber to adjust the flow rate so that the pressure became 5.0 × 10 −3 Torr. adjust. Subsequently, the shutter was closed to form plasma in order to keep a state between the target from which atoms evaporate and the substrate 1 were cut off, and the target surface was cleaned for about 5 minutes. Next, after setting the high-frequency power to a predetermined value, the shutter was opened and sputtering was performed for a predetermined time to form an n-type semiconductor layer 3. The n-type semiconductor layer 3 is a cadmium sulfide CdS sintered body (purity 99.99%, diameter 101.6 mm, thickness 5 mm)
And sintered zinc sulfide ZnS (purity 99.99%, diameter 101.6m
m, a thickness of 5 mm) as a target and by simultaneously sputtering while rotating the substrate 1. At this time, the high-frequency power applied to the electrodes of both targets was controlled in accordance with the film formation time, and the solid solution amount of zinc sulfide ZnS in the thickness direction in the n-type semiconductor layer 3 was changed to P-type as shown in FIG. It was changed so that it was larger on the side closer to the bonding surface with the semiconductor layer 4 and smaller as it came closer to the bonding surface with the transparent electrode 2. Considering the consistency of the spacing between CuInSe 2 forming the P-type semiconductor layer 4 and the solid solution amount of zinc sulfide ZnS near the bonding surface (d = 0 in FIG. 2) with the P-type semiconductor layer 4 5-1
It is considered that about 0% is appropriate. In order to reduce the internal resistance of the element, the amount of solid solution of zinc sulfide ZnS near the bonding surface (d = d 1 in FIG. 2) with the transparent electrode 2 is 1 to 3.
% Is considered appropriate.

n型半導体層3に引き続いて、同じく高周波スパッタ
リング法によりP型半導体層4を形成した。形成要領
は、n型半導体層3と同様であるが、P型半導体層4の
場合、銅Cu(純度99.99%)、インジウムIn(純度99.99
%)およびセレンSe−銅Cu合金(銅20重量%)をターゲ
ットとし、それぞれの高周波電流を調整することによ
り、組成を制御した。
Subsequent to the n-type semiconductor layer 3, a P-type semiconductor layer 4 was similarly formed by a high frequency sputtering method. The formation procedure is the same as that of the n-type semiconductor layer 3, but in the case of the P-type semiconductor layer 4, copper Cu (purity 99.99%) and indium In (purity 99.99%).
%) And selenium Se-copper Cu alloy (copper 20% by weight) as targets, and the composition was controlled by adjusting the respective high-frequency currents.

本実施例では、n型半導体層3およびP型半導体層4
を形成する際の基板温度および膜厚は、それぞれ下記の
通りとした。
In this embodiment, the n-type semiconductor layer 3 and the p-type semiconductor layer 4
The substrate temperature and the film thickness at the time of forming were respectively as follows.

P型半導体層4に引続き、厚さ0.5μmのモリブデンM
oからなる金属電極5を高周波スパッタリング法により
形成した。
Molybdenum M with a thickness of 0.5 μm following the P-type semiconductor layer 4
The metal electrode 5 made of o was formed by a high frequency sputtering method.

本実施例の素子と比較評価するためn型半導体層3に
おける硫化亜鉛ZnSの固溶量を均一にし、n型半導体層
3以外の成膜条件は本実施例と同一とした従来型の素子
を製作し、透明電極2側から模擬太陽光(スペクトルAM
1.5、照射強度100mW・cm-2)を照射し、素子特性を評価
した。その結果、本実施例のn型半導体層3の組成を傾
斜させた素子は、組成を均一とした従来型の素子に比
べ、短絡電流および曲線因子が10〜20%増大することが
確認された。
For comparative evaluation with the device of the present embodiment, a conventional device in which the solid solution amount of zinc sulfide ZnS in the n-type semiconductor layer 3 was made uniform and the film forming conditions other than the n-type semiconductor layer 3 were the same as in the present embodiment. The simulated sunlight (spectral AM
1.5, irradiation intensity of 100 mW · cm −2 ), and the device characteristics were evaluated. As a result, it was confirmed that the device in which the composition of the n-type semiconductor layer 3 of this example was graded increased the short-circuit current and the fill factor by 10 to 20% as compared with the conventional device in which the composition was uniform. .

上記において、n型半導体層3はP型半導体層4との
接合面付近の組成が調整され、格子の整合性が改善され
ているため、従来の素子に比べ局所的な歪みが緩和され
る。この結果、電子および正孔の捕獲の中心となる欠陥
の発生が抑制される。
In the above description, the composition near the junction surface of the n-type semiconductor layer 3 with the p-type semiconductor layer 4 is adjusted and lattice matching is improved, so that local distortion is reduced as compared with the conventional device. As a result, generation of a defect serving as a center for capturing electrons and holes is suppressed.

また、n型半導体層3はP型半導体層4との接合面か
ら透明電極2との接合面に近づくにつれて徐々に硫化亜
鉛ZnSの固溶量を減少させているため、組成の傾斜とと
もに導電率が増大する。この結果、素子の内部抵抗が減
少する。
In addition, since the n-type semiconductor layer 3 gradually reduces the solid solution amount of zinc sulfide ZnS from the bonding surface with the P-type semiconductor layer 4 toward the bonding surface with the transparent electrode 2, the conductivity of the n-type semiconductor layer 3 increases with the inclination of the composition. Increase. As a result, the internal resistance of the device decreases.

上記により、本実施例の光電変換素子では、良好なPn
接合が形成され、半導体内で光発生した電子および正孔
が効率的に外部回路に取り出されるため、短絡電流およ
び曲線因子の増大を期待することができる。
As described above, in the photoelectric conversion element of this embodiment, good Pn
Since a junction is formed and electrons and holes generated by light in the semiconductor are efficiently extracted to an external circuit, an increase in short-circuit current and fill factor can be expected.

〔発明の効果〕〔The invention's effect〕

本発明の光電変換素子は、一方の面にP型半導体層が
接合され、他方の面に透明電極が接合されたn型半導体
層について、その硫化亜鉛ZnSの固溶量をP型半導体層
の近くで大きくし透明電極の近くで小さくなるようにそ
の組成を厚さ方向に傾斜させることによって、Pn接合面
付近の欠陥の発生を抑制し、透明電極付近の導電率を増
大させ、半導体内で光発生した電子および正孔が効率的
に外部回路に取り出せるものとし、短絡電流および曲線
因子の増大を可能とする。
In the photoelectric conversion element of the present invention, for an n-type semiconductor layer in which a P-type semiconductor layer is joined to one surface and a transparent electrode is joined to the other surface, the solid solution amount of zinc sulfide ZnS is determined for the P-type semiconductor layer. By inclining the composition in the thickness direction so that it increases near and decreases near the transparent electrode, the occurrence of defects near the Pn junction surface is suppressed, the conductivity near the transparent electrode is increased, and Electrons and holes generated by light can be efficiently extracted to an external circuit, and a short-circuit current and a fill factor can be increased.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の一実施例の説明図、第2図は上記一実
施例のn型半導体層における硫化亜鉛ZnSの固溶量の変
化の説明図、第3図は従来の装置の説明図である。 1……基板、2……透明電極、 3……n型半導体層、4……P型半導体層、 5……金属電極。
FIG. 1 is an explanatory view of one embodiment of the present invention, FIG. 2 is an explanatory view of a change in the amount of solid solution of zinc sulfide ZnS in the n-type semiconductor layer of the one embodiment, and FIG. FIG. DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Transparent electrode, 3 ... N-type semiconductor layer, 4 ... P-type semiconductor layer, 5 ... Metal electrode.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】光入射側の窓層を形成し硫化カドミウムCd
S−硫化亜鉛ZnS固溶体よりなるn型半導体層、同半導体
層の光が入射する一方の面に接合された透明電極、およ
び上記n型半導体の他方の面に接合されたP型半導体層
を備え、上記n型半導体層の硫化亜鉛ZnSの固溶量をP
型半導体層との接合面に近い側で大きくし透明電極との
接合面に近づくにつれて小さくなるようにその組成を厚
さ方向に傾斜させたことを特徴とする化合物半導体多結
晶薄膜を用いた光電変換素子。
Cadmium sulfide Cd is formed on a light incident side window layer.
An n-type semiconductor layer made of a solid solution of S-zinc sulfide ZnS, a transparent electrode bonded to one surface of the semiconductor layer on which light is incident, and a P-type semiconductor layer bonded to the other surface of the n-type semiconductor The solid solution amount of zinc sulfide ZnS in the n-type semiconductor layer is P
Using a compound semiconductor polycrystalline thin film, characterized in that its composition is inclined in the thickness direction so that it increases on the side close to the junction with the type semiconductor layer and decreases toward the junction with the transparent electrode. Conversion element.
JP2116810A 1990-05-08 1990-05-08 Photoelectric conversion device using compound semiconductor polycrystalline thin film Expired - Fee Related JP2706352B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2116810A JP2706352B2 (en) 1990-05-08 1990-05-08 Photoelectric conversion device using compound semiconductor polycrystalline thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2116810A JP2706352B2 (en) 1990-05-08 1990-05-08 Photoelectric conversion device using compound semiconductor polycrystalline thin film

Publications (2)

Publication Number Publication Date
JPH0414268A JPH0414268A (en) 1992-01-20
JP2706352B2 true JP2706352B2 (en) 1998-01-28

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JP2116810A Expired - Fee Related JP2706352B2 (en) 1990-05-08 1990-05-08 Photoelectric conversion device using compound semiconductor polycrystalline thin film

Country Status (1)

Country Link
JP (1) JP2706352B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009054973A1 (en) * 2009-12-18 2011-06-22 SULFURCELL Solartechnik GmbH, 12487 Chalcopyrite thin film solar cell with CdS / (Zn (S, O) buffer layer and associated manufacturing process

Also Published As

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JPH0414268A (en) 1992-01-20

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