JP2704035B2 - Power circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit, and more particularly, to a power supply circuit having a function of cutting off a bias current of a start-up circuit when a bandgap reference circuit voltage at power-on becomes a normal voltage. .

[Prior art] As shown in FIG.
Transistors Q ₂ , Q ₃ , Q ₄ , resistors R ₂ , R ₃ , R ₄ , PNP transistor Q
₅ band gap reference circuit (hereinafter referred to as V _REF
Circuit), an error amplifier circuit including NPN transistors Q ₇ and Q ₁₀ , PNP transistors Q ₆ and Q ₉ , a resistor R ₅ , and an output NPN transistor Q ₁₁ , and resistors R ₆ and R for determining an output voltage. _{7, a} starting circuit including NPN transistors Q ₁ and Q ₈ and a resistor R ₁ for reliably operating the V _REF circuit when power is turned on, an output (V _OUT ) terminal 3 and a V _CC Terminal 1 and G
And an ND terminal 2.

Next, a start-up circuit at the time of power-on will be briefly described. When power is turned on, the power supply voltage (hereinafter referred to as V _CC )
It becomes larger than the base-emitter forward voltage drop of the transistor Q ₁ (hereinafter referred to as V _BE), NPN transistor Q ₁ operates, thereby biased NPN transistor Q ₈ is a collector current (hereinafter ICQ ₈₎ flows. This current Ic
Q ₈ is represented by the following equation.

This current is biased PNP transistor Q ₆ is, the PNP transistor Q _5, the collector current in Q ₉ (hereinafter ICQ _5, I
cQ ₉ ) flows. Therefore, the output NPN transistor Q
_11, and the V _REF circuit is biased, and V _REF and V _OUT when V _CC is turned on follow the V _CC and rise as shown in FIG. Next, rises until V _CC V ₁ of the Figure 4 shows V _CC is then (2) (hereinafter referred to as V _REF) V _REF circuit of the voltage represented by the formula, the collector saturation of the PNP transistor Q ₅ Voltage (V
_{CE (sat))} , V _REF becomes constant as shown in the following equation.

V _REF = ｛(V _BE Q ₂ −V _BE Q ₃ ) × R ₃ ｝ / R ₄ + V _BE Q ₄ [V] …… (2) At this time, V _BE of the NPN transistor Q ₈ of the starting circuit is It is shown by the formula.

V _BE Q ₈ = V _BE Q ₁ − (V _REF −V _BE Q ₇ ) (3) Here, if V _REF is constant, V _BE Q ₈ becomes smaller,
Operation can not be maintained and cut off. After this, the output NPN
Transistor Q ₁₁ and PNP transistors Q ₅ , Q ₆ , Q ₉ are NPN
Is biased by the transistor Q _7, V _OUT is, V _CC is V
Where becomes larger than the sum of the V _{CE (sat)} of the _OUT output NPN transistor Q _11, a constant value represented by the following formula.

In the conventional power supply circuit described above to [Invention Problems to Solved], in FIG. 4, V _CC
There rises to V _2, even if the constant value V _OUT is represented by the equation (4), the current I _CQ1 flowing through the transistor Q ₁ is not interrupted. Here, when determining the current through the load current of output NPN transistor Q ₁₁ to the transistor Q ₁ when a 10mA becomes as follows. The condition is that the output NPN transistor Q
DC current amplification factor of ₁₁ (hereinafter _{hFE = 100, R 5 = 1KΩ} , the emitter area ratio of transistors Q _1, Q ₈ and 1:10.

IcQ ₈ = 10mA / h _FE …… (6) The equation (5), (6) and (7), current ICQ ₁ flowing through the NPN transistor Q ₁ is, the IcQ ₁ = 500μA. Also, from the equation (5), as the load current of the output NPN transistor becomes large, it is understood that the ICQ ₁ also increases. Originally, the current flowing through the NPN transistor Q ₁ is, V
_Although not necessary when _REF reaches a constant voltage, a certain current always flows in the conventional circuit path method.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a reference voltage V _REF
It is an object of the present invention to provide a power supply circuit which cuts off a current flowing through a start circuit when a constant voltage is reached.

[Means for solving the problem]

The configuration of the present invention includes a reference voltage circuit that generates a reference voltage, an output circuit that drives a load, and a differential voltage between a voltage obtained by multiplying the output voltage of the output circuit by a constant and the reference voltage, and amplifies this signal. An error amplifier circuit that feeds back to the input terminal of the output circuit, and a starter circuit that supplies a bias current or a bias voltage to the error amplifier circuit when the power supply voltage rises, receives the output voltage, and the output voltage is equal to or higher than a predetermined value. Then, control means is provided for cutting off a MOS transistor connected in series to a power supply input terminal of the starting circuit and cutting off all bias current flowing through the starting circuit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a power supply circuit according to one embodiment of the present invention.

In FIG. 1, the power supply circuit of the present embodiment has a V _CC terminal 1
, GND terminal 2, V _OUT terminal 3 and NPN transistors Q ₁ to
Q ₄ , Q ₇ , Q ₈ , Q ₁₀ , Q ₁₁ , Q ₁₂ and PNP transistors Q ₅ , Q ₆ , Q
₉ , P-channel MOS transistors MP1, MP2, MP3 and N
And channel MOS transistors MN1, MN2, MN3, resistors R ₁ to R ₇
And is configured. Here, transistors Q ₂ , Q ₃ ,
V _REF circuit consisting of Q ₄ , Q ₅ , resistors R ₂ , R ₃ , R ₄ , transistor
_{Q 6, Q 7, Q 9} , Q 10, the error amplifier circuit comprising resistors R _5, the output transistor Q _11, the error amplifier comprising resistors R _6, R _7, transistor Q _1, Q _8, and a resistor R ₁ Start constitute a circuit, the transistor Q _12, resistors R _8, transistors MP1～MP3, in the configuration of MN1 to MN3, constitute a circuit for interrupting the collector current of the transistor Q ₁ when the V _REF circuit was up standing .

That is, in the power supply circuit of this embodiment, the NPN transistor and the base-emitter of the starting circuit are connected in common, the collector is connected to a load resistor, and the collector voltage is high level.
A CMOS inverter circuit that outputs a low level and a CMOS inverter circuit that inverts the output and outputs the inverted signal are provided.
Further, a diode-connected NPN transistor which is a bias circuit of an NPN transistor for driving the aforementioned CMOS inverter circuit, an NPN output transistor, and an NPN transistor for driving a PNP current mirror for operating the V _REC circuit.
A circuit is provided in which a P-channel MOS transistor is inserted between the transistor and its load resistance, and the P-channel MOS transistor is turned on or off by the above-described CMOS inverter circuit.

Next, the operation of the present invention will be described. When power is turned on, V
When _CC exceeds V _BE of the NPN transistors Q _1, NPN transistor Q ₁ is operated, thereby, the NPN transistor Q _8, Q ₁₂
Are biased, the PNP transistors Q ₅ , Q ₆ , Q ₉ and the NPN output transistor Q ₁₁ constituting the PNP current mirror are biased, and the voltage of the V _OUT terminal 3 and V _REF rise according to the power supply voltage. go. At this time, the NPN transistor Q ₁₂ is,
Since a current IcQ ₁₂ expressed by the following equation (8) flows,
The resistor R _8, transistor Q ₁₂ collector voltage (hereinafter V _C Q
₁₂ ) becomes low level as shown in FIG.

_{(Vcc-IcQ 1 × R 1} -V BE Q 12) / R 5 = IcQ 8 + IcQ 12 [A] ... (8) Furthermore, V _C Q ₁₂ is expressed by the following equation.

V _C Q ₁₂ = V _CC −IcQ ₁₂ × R ₈ [V] (9) Accordingly, the input voltage of the CMOS inverter circuit formed by the transistors MP2 and MN2 is low, so that the output is high and the transistors MP3 and MN3 , The output of the CMOS inverter circuit becomes low level.

Therefore, the MOS transistor MP1 is turned on, and the MOS transistor MP1 is turned on.
MN1 is turned off, the collector current of the NPN transistor Q ₁
IcQ ₁ is flowing. Next, when V _CC rises and becomes V ₁ in FIG. 2, V _BE of the NPN transistors Q ₈ and Q ₁₂ becomes the following equation.

V _BE Q ₈ = V _BE Q ₁₂ = V _BE Q ₁ − (V _REF −V _BE Q ₇ ) [V] (10) Therefore, V _CC rises to V _{1 in} FIG. V _REF
Becomes constant, the voltages V _BE Q ₈ and V _BE Q ₁₂ become small, the operation cannot be maintained, and the power is cut off. Accordingly, V _C Q ₁₂ than the equation (9), the ICQ ₁₂ becomes zero, V _C Q ₁₂ = V _CC, and the subsequent follows the V _CC. Therefore, the output of the CMOS inverter constituted by the transistors MP2 and MN2 changes from high level to low level, and the transistors MP3 and MN3
Output from the low level to the high level, the P-channel MOS transistor MP1
Is shut off, the transistor MN1 becomes conductive, current I _C1 flowing through the NPN transistor Q ₁ is, becomes zero.

〔The invention's effect〕

As described above, in the power supply circuit of the present invention, when V _CC rises from power-on and V _REF becomes a constant value,
Since the current of the starting circuit can be made zero, there is an effect that power saving can be achieved when the output voltage becomes constant.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a power supply circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing a change in voltage of each part when power is turned on in FIG. 1, and FIG. 3 shows a conventional power supply circuit. FIG. 4 is a circuit diagram, and FIG. 4 is a timing chart showing a change in voltage of each part when the power is turned on in FIG. 1 V _CC terminal, 2 GND terminal, 3 V _OUT terminal, Q ₁ to
Q ₄ , Q ₇ , Q ₈ , Q ₁₀ , Q ₁₁ …… NPN transistor, Q ₅ , Q ₆ , Q ₉ …… P
NP transistor, R _{1 to} R ₇ ...... Resistance, MP1 to NP3 ... P-channel MOS transistor, MN1 to MN3 ... N-channel MOS
Transistor.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-243714 (JP, A) JP-A-62-29218 (JP, A) JP-A-1-255017 (JP, A) 10025 (JP, U)

Claims (3)

(57) [Claims] 1. A reference voltage circuit for generating a reference voltage, an output circuit for driving a load, and a differential voltage between a voltage obtained by multiplying the output voltage of the output circuit by a constant and the reference voltage, and outputting this signal to the output circuit An error amplifier circuit that feeds back to the input terminal of the circuit,
A starting circuit for supplying a bias current or a bias voltage to the error amplifier circuit when the power supply voltage rises, and when the output voltage is input and the output voltage is equal to or higher than a predetermined value, the starting circuit is connected in series to a power input terminal of the starting circuit. MO connected
A power supply circuit provided with control means for cutting off an S transistor and cutting off all bias currents flowing through the starting circuit. 2. The power supply circuit according to claim 1, wherein said control means comprises a CMOS inverter. 3. The error amplifying circuit includes a first transistor having a base connected to the reference voltage generating circuit, a base connected to an output of the starting circuit, and an emitter and a collector connected to each emitter of the first transistor. And a second transistor connected to the collector, and a third transistor having a base to which a voltage obtained by multiplying the output voltage by a constant is input, and having an emitter connected to each of the emitters of the first and second transistors. The power supply circuit according to claim 1, wherein: