JP2702049B2 - Method and apparatus for decoding superimposed code - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for decoding a superimposed code, and more particularly, to the correction of an error generated when transmitting a superimposed code.

[0002]

2. Description of the Related Art In digital communication, it is required to appropriately correct errors occurring in a communication path during code transmission. The superimposition code shown in FIG. 8 is a code that can be suitably corrected even when transmitted through a communication path having a high error rate, that is, a code that is strong against errors.

A code word of a generalized superposition code can be expressed by the following equation (1).

[0004]

(Equation 4) In this equation the vector _{f i} of the Galois field _{GF (2) f 0 = f} 1 = ... = when placed with _{f N = f ((N +} 1)
n, k + Nk ′) The superposition code C is expressed as follows.

[0005]

(Equation 5) When information is transmitted using the superposition code C,

(Equation 6) The error represented by

(Equation 7) It is assumed that the following codeword is received (hard-decided). Conventionally, the F code and the f code have been decoded from the received code r in accordance with the decoding procedure shown as Algorithm 1. However, this algorithm is represented using convenience f _i.

[0006]

(Equation 8) FIG. 9 shows the configuration of a device that decodes the superposition code C according to the algorithm 1. The device shown in FIG. 1 includes an input terminal 10, a received signal dividing unit 11, an F code decoding unit 12, an adder 13, an f code decoding unit 14, an information bit extracting unit 15, and an output terminal 16.

The hard-decided received code r is input to the input terminal 10.
Is input to the reception signal division unit 11 via The reception signal division unit 11 generates a vector r _i (where i = 0, 1,... N) by dividing the reception code r into blocks of length n.

[0008] vector _{r i} is input to the F code decoding section 12 and the adder 13. F code decoding section 12 are circuits, i.e. the circuit that executes step 1 above to perform algebraic error correction F _i code by extracting further algebraically decode F _i codes using a vector r _i . The F code decoding unit 12 obtains the vector obtained by performing Step 1.

(Equation 9) Is output to the adder 13.

The adder 13 has a vector

(Equation 10) Are provided in correspondence with. i-th adder 13
Is the i-th vector r _i and

[Equation 11] Is input, and both are added on GF (2). As a result, step 2 of algorithm 1 is executed, and the vector that is the received word of the f code is

(Equation 12) Is obtained.

[0010] The f-code decoder 14 outputs a vector from each adder 13.

(Equation 13) And the vector r ₀

[Equation 14] Enter as The f-code decoding unit 14

(Equation 15) Algebraic decoding of step 2, ie, step 4. Thereby, estimation of the transmitted f-code, that is, error correction is realized. Vector indicating error-corrected f-code

(Equation 16) Is a vector indicating the F code obtained by the F code decoding unit 12.

[Equation 17] At the same time, it is input to the information bit extracting unit 15. The information bit extracting unit 15 extracts information bits from the input bit string, and outputs the information bits from the output terminal 16.

[0011]

By the way, r _i (i =
Error e _i (i = 0, 1,... N) appearing at 0, 1,.
Can be classified into TYPE I and II based on their properties. Here, if the j-th bit of e ₀ , e _i (i = 1, 2,... N ⁾ is represented as e ₀ ^(j) , e _i ^(j) , each TY
The error of the PE is expressed as follows.

[0012]

(Equation 18) These errors are

[Equation 19] Is canceled or canceled by the operation of

(Equation 20) Appears as an error. That is, an error of TYPE I appears and an error of TYPE II is canceled.

In the conventional decoding procedure, a vector is defined on GF (2).

(Equation 21) And by adding the vector r _i, it is performed to decode the f code. Therefore,

(Equation 22) Is incorrectly corrected by decoding the _Fi code.
Error YPE I have, will be treated as having occurred in the vector r _i, the cause of a new error. This leads to a deterioration in the decoding error rate.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and suppresses erroneous correction of a received code (vector r _i ) due to a TYPE I error, thereby lowering a decoding error rate. The purpose is to let them.

[0015]

In the present invention, in order to solve the problems] In describing the means employed for solving the problems, firstly, superposition code C by the following equation, f code, the content of F _i code and the received signal r and F _i Defines the operation to be performed on the received word of the code.

[0016]

(Equation 23) In order to achieve the above object, the f-code received word extracting method of the present invention is configured such that when the superimposed code C is received as the received signal r, the received word of each _Fi code (i = 1, 2,... J
It is determined whether or not an error has occurred in the (j = 0, 1,..., N-1) th bit. As a result of the determination, no error has occurred in the jth bit for any of the received words of the _Fi code. that the case where the extracts j th value of the bit vector r ₀ as the j th bit of f code, j-th bit error in the received word of the result either F _i sign determination occurs , It is assumed that the j-th bit of the received word of the f-code has an erasure error, and the bit candidate obtained as a result of the pseudo maximum likelihood decoding is the value of the j-th bit of the f-code. by extracting a vector _{r i (i = 0,1, ...} N) constituting the received signal r and extracting the received word of the f code from.

The method of decoding a superimposed code of the present invention
When receiving as a reception signal r, while decoding extracted further it received word of F _i symbols do the formula (c), the vector r by f code received word extraction method of the present invention
It is characterized in that a received word of the f-code is extracted from _i , and the f-code is decoded based on the extracted received word.

The superposition code decoding apparatus according to the present invention is an apparatus for implementing the superposition code decoding method according to the present invention. When the superposition code C is received as the reception signal r, the reception signal r is converted to a vector r.
_i (i = 0, 1,... N) a received signal dividing unit;
And F code decoding unit for decoding the extracted further it received word of F _i symbols do the formula (c) (i = 1,2, ... N) on the vectors r _i obtained by the reception signal dividing unit, a vector f code extraction means for extracting a received word of the f code from r _i, and an f code decoding unit for decoding the f code based on the extracted received word, wherein the F code decoding unit receives each _Fi code. It is determined whether or not an error has occurred in the j-th bit of the word, and the result is output. The f-code extracting unit determines which _Fi code is received based on the determination result output from the F-code decoding unit. j th bit of f code when also been the j-th and the means for determining whether or not an error occurs in the bits, no errors occur also received word of any F _i symbols for words And extract the value of the j-th bit of the vector r ₀ as , Either F _i handling f code j as erasure error bit position j of the received word of the f code when received word error in is to be occurring in the code has occurred
Means for replacing the value of the bit with a bit candidate obtained by pseudo maximum likelihood decoding.

In the f-code received word extraction method or superposition code decoding method of the present invention, the bit candidates are generated by, for example, the following procedure. That adds for all i the received signal level at the time of receiving the j-th bit of the vector r _i, to generate the value of the bit candidate in response to the comparison to the results the addition result with a predetermined value. In addition, in the superposition code decoding device of the present invention, for example, the superposition code decoding device generates the following configuration. That has a means for generating a bit candidate in response to the comparison with the predetermined value the means and the addition result is added for every i the received signal level of the j th bit of the vector r _i As a result, the bit candidates The f-code is generated by a configuration including a bit candidate generation unit that supplies the j-th bit candidate of the f-code to the f-code extraction unit. Here, the comparison target with the addition result is the zero level.

The superimposition code decoding apparatus according to the present invention may further include an information bit extracting unit for extracting information bits from the _Fi code and the f code decoded by the F code decoding unit and the f code decoding unit.

[0021]

The operation of the present invention will be described by taking the above-described superimposition code decoding apparatus as an example. In addition, in consideration of the fact that the superposition code decoding method is performed by this apparatus and the f-code reception word extraction method is a main part of the superposition code decoding method, the f-code reception word extraction method and the superposition code decoding method will be described. Although omitted, the operation of the f-code received word extraction method and the convolutional code decoding method of the present invention is clear from the following description.

In the present invention, the superposition code C defined by equation (a) is received as a received signal r represented by equation (b). Received signal r is divided into a vector r _i by the reception signal dividing unit. F code decoding unit vector r with decoding this formula (c) Operation was carried out further extracts the received word F _i codes for _i, j of the received word for each F _i code
It is determined whether or not an error has occurred in the ith bit, and the result is output.

The f-code extracting means determines, for each bit, whether or not it can be replaced with a bit candidate obtained as a result of pseudo maximum likelihood decoding, based on the result of the determination output from the F-code decoding unit. That is, first, for any bit j,
_It is determined whether an error has occurred in the received word of the _i code. Next, if it is determined that the bit is necessary, the bit of the f-code is replaced with a bit candidate obtained as a result of pseudo maximum likelihood decoding. Specifically, if an error occurs in the j-th bit for received word of either F _i code, handled as erasure error in the j-th bit of the received word of the f code occurs, This bit is replaced with a bit candidate obtained as a result of pseudo maximum likelihood decoding. In other cases, that is, when no error occurs in the j-th bit in any of the received words of the _Fi code,
The value of the j-th bit of the vector r ₀ is extracted as the j-th bit of the f-code.

When the received word of the f-code is extracted in this way, the f-code decoding unit executes the decoding process of the f-code. An information bit extracting unit is provided, and an F code decoding unit and f
It is also possible to extract information bits from the _Fi code and f code decoded by the code decoding unit.

As means for implementing pseudo maximum likelihood decoding, a bit candidate generator having the following functions is preferable. That is, first adding the received signal level of the j th bit of the vector r _i for all i. Further, the result of the addition is compared with the zero level. Then, a bit candidate is generated according to the result of the comparison. This bit candidate is supplied to the f-code extraction unit as the j-th bit candidate of the f-code.

[0026] Thus, in the present invention, when an error has occurred in the j-th bit of the received word F _i codes, handling as erasure error which occurs in the received word of the f code, f code due to so as to perform a pseudo maximum likelihood decoding of the influence of errors caused due to the error correction F _i code is minimized. Next, the principle on which this action occurs will be described.

[0027]

The following algorithm 2 is an example of an f-code received word extraction algorithm used in the present invention.

[0028]

(Equation 24) The following algorithm 3 is an example of a superposition code decoding algorithm used in the present invention. This algorithm includes the f-code received word extraction method according to Algorithm 2 as Step 4.

[0029]

(Equation 25) Here, E (x) is a received signal level. In A Rugorizu <br/> arm 2 and 3, it is assumed to represent the bit "1" positive signal level, bit "0" as a negative signal level. For example, "1" is the E ^1/2, "0" is assumed constellation corresponding to -E ^1/2.

When the algorithm 3 is performed, first, a received word of the Fi code is extracted and its algebraic decoding process is executed by a method similar to the conventional method (step 1). Step 1
When the decoding process is performed in (1), an error determination is performed for each bit (step 2). That is, when the error in the j-th bit of the received word F i code occurs, erasure flags E i (j) = 1 and then, if not occurring and E i (j) = 0. These steps 1 and 2
Is performed for all i (step 3).

Next, step 4 relating to extraction of the received word of the f code is executed. In step 4, when an error during the decoding of the received word of F _i code for any i in a certain bit position j is not to occur, i.e. erasure flags E according to all i for a bit position j _{If i} ^(j) is 0, the j-th bit of r ₀ is extracted as the j-th bit of the received word of the f-code (step 4 (b)). On the other hand, when the erasure flag E _i ^(j) related to any i at a certain bit position j is 1 and an error occurs in a received word of any _Fi code,
Bit candidates obtained as a result of pseudo maximum likelihood decoding are extracted as the j-th bit of the received word of the f-code (step 4).
(A)). Then, the received word of the f-code obtained by executing step 4

(Equation 26) Is subjected to decryption processing.

The feature of Algorithm 3 is that Step 4
(A), that is, adoption of pseudo maximum likelihood decoding in extraction of a received word of the f code. In this step, unlike step 2 of algorithm 1 which is a conventional algorithm, the condition of f ₀ = f ₁ =... = F _N is used, and the erasure error determination space is converted into N + 1 dimensions to determine the distance to the erroneous determination area. I'm making it big. Thereby, the decoding error rate of the f code is improved.

Now, for the sake of simplicity, if N = 1 and N + 1, ie, two vectors constituting the received signal r are r _L and r _R , the errors of TYPE I and II are as follows:
It is represented as in FIG. This figure shows the operations performed in step 1 in algorithms 1 and 3.
In this figure, an asterisk indicates an error bit generated on the communication path. As mentioned above, TYPE I errors are:
When a plurality of received words (vectors r _L and r _R ) are vector-added on GF (2), this is an error in which the added value of the corresponding bit becomes an error, and the error of TYPE II is the added value of the corresponding bit. Is a kind of error that is not an error. Therefore,
By executing the operation of step 1, an error of TYPE I can be detected. The error of TYPE II is canceled by the operation of step 1.

[0034] Step 4 of the algorithm 3 is performed after the reception word F _i code is further decoded extracted by such error correction operation. In step 4,
Effect That Misao step 1 of the error correction processing of F _i code
The effect of the operation is that the detected TYPE I error is treated as an erasure error, and the bits related to the erasure error are replaced with bit candidates obtained as a result of pseudo maximum likelihood decoding, thereby extracting the received word of the f code. And are excluded from the decryption process.

More specifically, if it is assumed that the erasure flag E _i ^(j) for any i at a certain bit position j is 1, the received signal level is set at the bit position j of the received word of the f code. The bit candidate obtained as a result of the pseudo maximum likelihood decoding determined according to the added value of is substituted. Note that the present invention does not exclude the employment of other maximum likelihood codes. In the example of N = 1 shown in FIG. 1, the processing executed in step 4 (a) is as follows.

[0036]

[Equation 27] This equation indicates that the erasure error determination space for the f-code in Algorithm 3 is a two-dimensional space as shown in FIG. As shown in the above equation (a),
Since the condition f ₀ = f ₁ =... = F _N is satisfied in the superimposed code C to be decoded in the present invention,
Bit pair ^{_{(E (r L (j)}} ), E (r R (j))) is plausible plausible that decode the point if a region above the broken line in FIG. (1,1), the reverse If it is a lower region, it is considered that decoding to point (0, 0) is most likely. Bit pairs (E (r _L ^(j) ), E (r _R
^(J) )) is determined to be a region above or below the broken line in the example of FIG.
Is compared to a zero level. The operation of setting the j-th bit of the received word of the f code in step 4 (a) is performed according to the result of this determination. Therefore, the operation of step 4 (a) is performed when a TYPE I error occurs in the received signal r.
The j-th bit of the received word of the f code is represented by a received signal level E
It can be said that this is an operation of replacing with a bit candidate obtained as a result of performing pseudo maximum likelihood decoding using (x).

It is intuitively apparent from FIG. 2 that the decoding error rate can be improved by such an operation. That is, the extraction of the received word of the f code is performed by i
When executed every time, in other words, f ₀ = f ₁ =... = F _N
When performing the extraction of the received word of the f _i codes without using the conditions determined space f _i code from the one-dimensional space for each i, the distance misjudgment area and received word bit is 1 . On the other hand, in FIG. 2, the bit pair (E (r (r)) formed from the received word of the f-code obtained in step 4 (a).
^{_{L (j)), E (}} r R (j))) and erroneous distance determination area (point (1,1) or (0,0) and dashed distance) 2
It is ^1/2 . Generally, when considering a superimposed code as shown in FIG. 8, the determination space is an N + 1-dimensional space,
The distance between the bit group and the erroneous determination area is (N + 1) ^1/2 . As described above, a large distance between the received word of the f-code and the erroneous determination area indicates an improvement in the decoding error rate. The final decoding is performed in step 5.

The improvement of the decoding error rate is quantitatively studied by comparing algorithms 1 and 3 as follows. Here, a two-dimensional symmetric channel for transmitting bits as an antipodal signal of energy E is considered. It is also assumed that Gaussian noise is added in this communication path. Under this assumption, since the average of the Gaussian noise is zero, to represent the energy density and N _0/2, the bit error rate p of the channel is expressed by the following equation.

[0039]

[Equation 28] At this time, the number of errors T occurring in a code word of length n is

(Equation 29) It is represented by

First, in a case where the number T of errors represented by the above equation occurs in the communication channel, in order to appropriately decode each _Fi code, in each of the algorithms 1 and 3, the _Fi code The number τ _{F of} decoding processes represented by equation (7)
Must be able to correct the error.

[0041]

[Equation 30] Further, the f code, which is a code word having a length n, has N
Since there are +1 errors, the number of errors that occur on the communication channel and are included in the received word of the f code in the received signal r is T (N +
1) It becomes pieces. When separately extracting each f _i code as Algorithm 1, wherein in the decoding process of the f code (8)
Must be able to correct the number τ _f of errors.

[0042]

(Equation 31) In this equation (8), T appears on the right side. T correction required because the bit error rate p in are those given by the aforementioned equation (6) Equation (6) given by equation (4), in the algorithm 1 to the decryption processing of F _i code The ability depends on the value of the Q function appearing on the right side of equation (4).

On the other hand, in order to correctly decode the f code,
When τ _{f, ε} errors caused by TYPE I errors are corrected as erasure errors, both τ _{f, e} errors caused by erroneous correction and TYPE II errors must be corrected. τ _{f, ε} and τ _{f, e}
Is a value as shown in Expression (9) or (10), respectively.

[0044]

(Equation 32) In algorithm 3, error detected by the decoding of F _i codes are treated as erasure error of f symbol F
_This is due to the decoding of the _i code. When correcting the erasure error of the f-code using the algorithm 2, the number of bits τ (ε) erroneously decoded is expressed by the following equation (11).

[0045]

[Equation 33] From the equations (10) to (11), in order to correct the error of the f code correctly, the following number τ _f
= Τ (ε) + τ The ability to correct the error of _{f, e} is required.

[0046]

(Equation 34) The number τ _f shown in the equation (12) depends on the probability P. This probability P is Q as in the case of the bit error rate p described above.
Determined by the function, where the argument is (N + 1) ^1/2 times that of the bit error rate p. this is,
Focusing on the condition of f ₀ = f ₁ =... = f _N , the reason is that the f-code determination space is expanded to an N + 1-dimensional space.
Since the Q function is a monotonically decreasing function, the error correction capability required for the decoding process of the f-code in the algorithm 3 is smaller and sufficient than that in the algorithm 11. Specifically, from the right side of equation (8), equation (12)
Subtracting the right side of

(Equation 35) Becomes

Therefore, in the present invention, the apparent channel error rate is improved when the f-code decoding process is executed, so that the number of errors that must be corrected in the f-code decoding process is reduced. I do. In other words, the effect of errors that may occur newly by error correction F _i code is reduced compared with the prior art. This appears as an improvement in the decoding error rate when the transmission rate is the same, and as an improvement in the coding rate as a result of redundancy reduction when the decoding error rate is the same.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. The same components as those in the conventional example shown in FIGS. 8 and 9 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 3 shows the configuration of the superposition code decoding apparatus according to one embodiment of the present invention. The greatest feature of this embodiment lies in an algorithm for extracting a received word of f-code. Therefore, instead of the adder 13 in the conventional example, the f code extraction unit 2
4 is used for extracting the received word of the f code, and
An analog reception level input terminal 22 and a bit candidate generation unit 23 are newly provided. F code decoding section 21, like the F code decoding section 12 in the conventional example, and supplies the information bits extraction unit 15 decodes the received word F _i symbols. The F code decoding unit 21 has a function of generating an erasure flag E _i ^(j) and supplying the same to the f code extraction unit 24, as a function not provided in the F code decoding unit 12 in the conventional example. The f-code decoding unit 25 is different from the f-code decoding unit 14 in that the received word of the f-code is supplied not from the adder 13 but from the f-code extraction unit 24, and the f-code is decoded and sent to the information bit extracting unit 15. Supply.

The reception signal division unit 11 receives the reception code r via the input terminal 10 and divides the reception code r into blocks of length n to generate vectors r _i (i = 0, 1,... N). I do. F code decoding unit 21, the vector _{r i}

[Equation 36] By performing the operation to extract the received word F _i code, decodes the received word algebraically. The F code decoding unit 21 obtains the vector

(37) Is output. This output is supplied to the information bit extracting unit 15.

On the other hand, the F code decoding unit 21 generates an erasure flag E _i ^(j) . Here, i is the ith vector r _i (i = 1, 2,... N), and j is this vector r i
Respectively indicate the bit positions in. When decoding the _Fi code algebraically, the F code decoding unit 21 sets E _i ^(j) = 1 for bits determined to be erroneous, and E _i ^(j) = 0 for bits determined to be non-error. I do. The F code decoding unit 21 outputs the erasure flag E _i ^(j) to the f code extraction unit 24.

In addition to the above-mentioned received signal vector r _i and erasure flag E _i ^{( j)} , the f-code extraction section 24

(38) Is entered.

The bit candidate generator 23 has an analog adder 31 and a comparator 32, as shown in FIG. Although only one set of the analog addition unit 31 and the comparison unit 32 is illustrated in FIG.
, A total of n sets are provided for each set. The bit candidate generation unit 23

[Equation 39] The following processing is performed when generating the.

[0054] Bit candidate generating unit 23 first signal level _E when the hard decision received signal ^{r (r i (j))} (i
.. N; j = 0, 1,..., N−1) are input via the analog reception level input terminal 22. Where E
(X) is an analog value indicating the reception level when bit x is received. E ^{_(r i _(j))} is added to each i by the analog addition section 31. Resulting

(Equation 40) Is compared with the zero level by the comparing unit 32. The result of the comparison is the j-th bit candidate

[Equation 41] Is output to the f-code extraction unit 24. Therefore, the j-th bit candidate

(Equation 42) Is

[Equation 43] Is set to 1 when is set to zero level or more, and set to 0 otherwise. Therefore, the bit candidate

[Equation 44] Is a bit obtained as a result of pseudo maximum likelihood decoding of the received bit r _i ^{(j) according} to the principle described above (algorithms 2 and 3).

The f-code extraction unit 24 extracts the received word of the f-code using each input. The f-code extraction unit 24 includes an erasure flag check gate 41 and a switch 42 as shown in FIG. Although only one set of the erasure flag check gate 41 and the switch 42 is shown in this figure, n sets are provided in total corresponding to the bit position j.

The erasure flag check gate 41 outputs the erasure flag E _i ^(j) (i =
1, 2,... N) are input, and the logical sum of them is obtained. That is, if the disappearance flag E _i ^(j) is 1 for any i, the output is 1; otherwise, it is 0.

The switch 42 is switched as follows in accordance with the output of the erase flag check gate 41. First,
When the output of the erase flag check gate 41 is 0,
That is, when the erasure flag E _i ^(j) is 0 for any i, the j-th bit of the received word of the f code

[Equation 45] To extract the bit r ₀ ^(j) . That is,

[Equation 46] Execute the processing of

The erasure flag E _i for any _i
^{If (j)} is 1, the output is

[Equation 47] The switch 42 is switched so that That is,
The j-th bit of the received word of the f code is replaced with a bit candidate obtained by pseudo maximum likelihood decoding.

The f-code decoder 25 receives the f-code received word extracted by the f-code extractor 24 in this way.

[Equation 48] Is algebraically decoded. The information bit extracting unit 15
Vector indicating the obtained F _i code by F code decoding section 21

[Equation 49] And a vector indicating the f-code obtained by the f-code extraction unit 24

[Equation 50] , An information bit is taken out and output from an output terminal 16.

FIG. 6 shows the performance when N = 1 to 3 in this embodiment. The horizontal axis in this figure is the error correction capability per symbol, and the vertical axis is the coding rate. In the figure, “Capacity” indicates a channel capacity in information theory, and “Varshamov-Gilbert bound” indicates a type of a limit expression indicating a relationship between an error correction capability and a coding rate. Codes that asymptotically match or exceed this limit equation are generally considered good codes. In this figure, "Co
“De C” indicates the coding rate when the present embodiment is implemented at N = 1, and “Code C2” indicates the coding rate when the present embodiment is implemented at N = 2. , "Code C3" indicate the coding rate when the present embodiment is implemented with N = 3, which indicates that the coding rate is improved in the present embodiment. In a region where the coding rate is relatively small, N = 2 rather than N = 1.
Furthermore, it is recognized that N = 3 is more preferable.

The effect will be described using numerical values as follows.

First, consider a two-dimensional symmetric channel for transmitting bits as an anti-podal signal of energy E.
Assuming that the bit error rate p in this communication channel is 0.1, the SN ratio is (2E / N ₀ ) ^1/2 = 1.28. Considering a superposition code C with N = 1 and a code length n = 8192, the SN ratio after erasure error correction by Algorithm 3 is (4E / N ₀ ) ^1/2 , so the probability P of erasure correction error failure is , P = 0.0351.

Code length 4096, minimum distance 4 as f code
Assuming that a BCH code of 91 is used, the decoding error probability P _f (ε) of the f code is Pf (ε) = 4.6 × 10 ^−14.
Becomes Code length 4096 as F _i code, the minimum distance 20
When using the M-sequence code of 48, since the communication path error rate is equivalent to 2p = 0.20, _{F i} code decoding error probability _{P F} (epsilon) is _{P F (ε)} = 6.2 × 10 ^-14
Becomes The coding rate of this code is R _c = 0.2065.

On the other hand, code length 8192, minimum distance 1
Using the BCH code 033, the decoding error rate P
_BCH (ε) = 3.6 × 10 ⁻¹³ , which is ^{almost the} same as the above example. However, the coding rate R _BCH = 0.033. Accordingly, the effect of improving the coding rate in this embodiment is 6.26 times as compared with other error correction codes having the same error correction capability.

Also, in this embodiment,

(Equation 51) If an error has occurred at bit position j of the received word of the _Fi code obtained by

(Equation 52) Handled as erasure error that occurred, for which is adapted to perform a pseudo maximum likelihood decoding of the f code, it is possible to minimize the influence of errors caused due to the error correction F _i symbols.

FIG. 7 shows an error index in this embodiment (N = 1). The horizontal axis in this figure is the coding rate, and the vertical axis is the error index. In the figure, E _c (r _c ) is the error index of the present embodiment, and E (r) is the error index in the communication path with the error rate p.

First, if the error rate in the communication channel is p = Q
((2E) / N _O) assume that transmitted the codes of encoding rate r using a two-dimensional target communication channel is ^1/2). Assuming that the received code is to be subjected to maximum likelihood decoding, the decoding error rate P (ε) is expressed as P (ε) ≦ exp (−n · E (r)) 0 ≦ r <C (p) according to the random coding theorem. It can be said that there are (n, k) codes that satisfy. However,
C (p) is the channel capacity.

[0068] _{F i} code (n, k') because a sign,
The decoding error rate P _s (ε) is expressed as follows.

P _s (ε) ≦ exp (−n · E (2r _s , p _s )) 0 ≦ r _s <min [C (p _s ), 1/2 · ln 2]) where r _s = 2k ′ / N · ln2 [nats / sy
It is a _{mbol] p s = 2p (1} -p).

Next, since the f code is an (n, k) code, its decoding error rate P _m (ε) is expressed as follows.

[0071] _{P m (ε) ≦ exp (} -n · E (2r, p m)) 0 ≦ r <min [C (p m), 1/2 · ln2]) However, r = 2k / n · ln2 [Nats / symb
ol] is _{p m = 2p (1-p} ) P + p 2.

When N = 1, the superposition code C is (2n, k +
Since k') is a sign, the coding rate becomes _r c = _r + _{r s.} Therefore, the decoding error rate P in this embodiment (epsilon) is, P (ε) ≦ exp ( -2n [E c (r c) -δ (r)]) 0 ≦ r c <C (p), δ ( r) → 0 (n → _{infinity) E c (r c) =} min [E (2r s, p s), E (2r, p m)] becomes. FIG. 7 is based on this, and it can be understood from this figure that the decoding error rate is improved.

The present invention is not limited to the above embodiment.

[0074]

As described above, according to the first aspect of the present invention,
According to the f-code received word extraction method according to the above, it is determined whether an error has occurred in the j-th bit of the received word of each _Fi code, and the j-th bit of the received word of any _Fi code is determined. Are extracted as the j-th bit of the received word of the f-code when the pseudo maximum likelihood decoding is performed when an error occurs in the f-code. will be executed, it is possible to minimize the influence of errors caused due to the error correction F _i symbols. As a result, the decoding error rate can be reduced if the transmission rate is the same as the conventional one, and the transmission rate can be improved if the same decoding error rate is allowed.

[0075] Further, according to the superposition code decoding method according to claim 2 of the present invention, when decoding the superposition code C received as a received signal r, claim while decoding received word F _i code Since the received word of the f-code is extracted by the f-code received word extraction method according to the first aspect, the same effect as the first aspect can be obtained. According to the superposition code decoding apparatus according to claim 4 of the present invention, the method according to claim 2 is realized, and the same effect as that of claim 2 can be obtained.

[0076] Further, according to the method or apparatus according to claim 3 or 5 of the present invention, by adding the received signal level at the time of receiving the j-th bit of the vector r _i for all i, the addition result with a predetermined Since the value of the bit candidate is generated according to the result of comparison with the value, pseudo maximum likelihood decoding which can be suitably used in the method according to claim 1 or 2 and the apparatus according to claim 4 can be realized.

In addition, according to the superimposition code decoding apparatus according to claim 6 of the present invention, since the information bit extracting section is provided, the F code decoded by the F code decoding section and the F code decoded by the f code decoding section are provided.
Information bits can be extracted from the _i code and the f code.

[Brief description of the drawings]

1 is a diagram showing an error correction and detection as well as error classification of the operation performed when extracting the received word F _i symbols.

FIG. 2 is a diagram illustrating a principle of improving a decoding error rate in an example in which a decision space of an f-code is two-dimensionally determined in the present invention.

FIG. 3 is a block diagram illustrating a configuration of a superposition code decoding apparatus according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a bit candidate generation unit according to the embodiment.

FIG. 5 is a block diagram illustrating a configuration of an f-code extraction unit in the embodiment.

FIG. 6 is a diagram illustrating a coding rate when N = 1, 2, 3;

FIG. 7 is a diagram showing an error index.

FIG. 8 is a diagram showing code words of a ((N + 1) n, k + Nk ′) superposition code C when f ₀ = f ₁ =... = F _N = f in a general formula.

FIG. 9 is a block diagram illustrating a configuration of a superposition code decoding device according to a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Input terminal 11 Reception signal division part 15 Information bit extraction part 16 Output terminal 21 F code decoding part 22 Analog reception level input terminal 23 Bit candidate generation part 24 f code extraction part 25 f code decoding part 31 Analog addition part 32 Comparison part 41 Clear flag check gate 42 switcher f GF (2) on the (n, k) linear code F _i GF (2) on the (n, k') linear code (where i
= 1, 2,... N) r _i A vector constituting the received signal r (where i = 0,
1, ... N)

Claims (4)

(57) [Claims] 1. When a superimposition code C defined by equation (a) is received as a received signal r represented by equation (b), a vector r _i (i = 0, 1, ... N)
In a f-code received word extraction method for extracting a f-code received word from It is determined whether or not the j-th (j = 0, 1,..., N-1) bit has an error in the received word of each _Fi code (i = 1, 2,... N). If it is determined that no error has occurred in the j-th bit also in the received word of the _Fi code of ( _{i), the} value of the j-th bit of the vector r ₀ is extracted as the j-th bit of the received word of the f code. , if the error in the j-th bit for the received results either F _i sign of judgment is to be occurring is handled as erasure error in the j-th bit of the received word of the f code occurs , When the j-th bit of the vector r _i is received
The result of adding the received signal level for all i and
By performing comparison with a predetermined value, pseudo maximum likelihood decoding is performed .
A f-code received word extraction method characterized by extracting a bit candidate estimated by pseudo maximum likelihood decoding as a j-th bit of an f-code received word. If wherein receiving the superimposed code C as the received signal r, while extracting the received word F _i code by the operation of the following formula (c) further decodes this, from the vector r _i In a convolutional code decoding method for extracting a received word of an f-code and decoding an f-code based on the extracted received word, A superposition code decoding method, wherein a reception word of f-code is extracted by the f-code reception word extraction method according to claim 1. 3. A reception signal division unit that divides the reception signal r into vectors r _i when the superposition code C defined by the expression (a) is received as the reception signal r represented by the expression (b).
The vector r _i (i = 0,
1,... N), the operation of equation (c) is performed and the _Fi code (i
= 1, 2,... N), an F-code decoder for extracting and decoding the received word, f-code extracting means for extracting a received word of f-code from the vector r _i , and a f-code decoding unit for decoding the f-code. Change the j-th received signal level of the vector r _i to all i
Means for adding and comparing the addition result with a predetermined value.
Means for generating bit candidates in accordance with the result;
Is a candidate for the j-th bit of the received word of f-code.
Candidate generation unit that performs pseudo maximum likelihood decoding by
The F code decoding unit determines whether an error has occurred in the j-th bit of the received word of each _Fi code and outputs the result, and the f code extraction means outputs the F code from the F code decoding unit. Means for determining whether or not an error has occurred in the j-th bit of the received word of any _Fi code based on the output determination result; and an error has occurred in the received word of any _Fi code. If it is a non extracts j th value of the bit vector r ₀ as the j th bit of the received word of the f code for the received word of any F _i code is an error has occurred Means for treating the j-th bit of the received word of the f-code as having an erasure error and replacing the j-th bit of the received word of the f-code with the bit candidate generated by the bit candidate generator. A superimposition code decoding device, comprising: . 4. The superposition code decoding device according to claim 3 , further comprising an information bit extracting unit that extracts information bits from the _Fi code and the f code decoded by the F code decoding unit and the f code decoding unit. Superimposing code decoding device.