JP2701187B2 - Clock loss detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock disconnection detection circuit for detecting a disconnection of a clock signal distributed and supplied to a plurality of packages. A communication control device and various devices are configured by mounting a plurality of packages, and various circuits mounted on each package generally operate in synchronization with the phase of a reference clock signal. Therefore, if the clock signal is interrupted due to the disconnection of the wiring of the backboard or the like, the circuit mounted on the package cannot perform a normal operation, and thus it is necessary to detect the interrupt of the clock signal.

[0002]

2. Description of the Related Art FIG. 9 is an explanatory view of a conventional example, in which 71 is an oscillator, 72 is a frequency divider, 73-1 to 73-n are packages (PKG1 to PKGn), and 74-1 to 74-n are buffers. (BF), 75-1 to 75-n are clock signal disconnection detection circuits (DET1 to DETn), 76-1 to 76-n are clock signal lines, and 77 is an OR circuit (OR).

An output signal of the oscillator 71 having high stability is used as a master clock signal, and a frequency divider 72 generates a clock signal having a predetermined frequency.
-1 to 76-n via buffers 74-1 to 74-n, and a clock signal is supplied to the mounted packages 73-1 to 73-n. Each package 73-1
If the clock signal supplied to each of the packages 73-1 to 73-n is interrupted, the circuits on each of the packages 73-1 to 73-n cannot operate normally.
When the interruption of the clock signal is detected by -n, the OR circuit 7
7, a disconnection detection signal is transmitted, and a clock disconnection alarm signal is transmitted from an alarm circuit (not shown).

The disconnection detection circuits 75-1 to 75-n are constituted by, for example, retrigger-type monostable multivibrators, and are triggered by a clock signal.
For example, “0” having a pulse width of 10 pulses of the clock signal
Output pulse. Therefore, the clock signal line 76-1
1 to 76-n, if the clock signal is interrupted for a period of 10 pulses or more due to a buffer failure, disconnection of the clock signal line, or the like, the output signal of the monostable multivibrator becomes "1" and OR The signal is output from the circuit 77 as a disconnection detection signal.

Also known are disconnection detection circuits 75-1 to 75-n constituted by counters. In this case, high-speed clock signals such as master clock signals are counted, and clock signal lines 76-1 to 76-n are counted. By clearing with the n clock signal, when the clock signal is cut off, the count content of the counter overflows, and this is used as a cutoff detection signal.

[0006]

Problems to be Solved by the Invention In the conventional example,
Clock disconnection detection circuits 75-1 to 75-n are provided for the clock signal lines 76-1 to 76-n, that is, for the packages 73-1 to 73-n to be mounted. In a large number of devices, a large number of clock disconnection detection circuits 75-1 to 75-n are also required, each of which is provided with a monostable multivibrator, a counter, and the like. In the configuration using the monostable multivibrator, the time constant is set to about 10 pulses as described above, and therefore, there is a disadvantage that a pulse missing of 10 pulses or less cannot be detected. Further, in the configuration using the counter, it is necessary to use a configuration for counting the high-speed clock signal, so that there is a disadvantage that the configuration becomes expensive. It is an object of the present invention to economically detect disconnection of a clock signal even for a large number of clock signal lines.

[0007]

A clock disconnection detecting circuit according to the present invention will be described with reference to FIG.
From a plurality of packages 2-1 to 2-n (PKG1 to PK
Gn), a clock signal of the same or different frequency to be supplied and supplied thereto, and a common disconnection detection unit 3 for outputting a detection signal when at least one of the clock signals is disconnected, and detection of the common disconnection detection unit 3 And a latch circuit 4 for latching a signal and outputting a disconnection alarm signal.

The common disconnection detecting section 3 includes a plurality of packages 2
A first AND circuit for directly inputting clock signals of the same frequency distributed to -1 to 2-n, a second AND circuit for inverting and inputting, and a signal obtained by inverting the output signal of the first AND circuit A third AND circuit for inputting an output signal of the second AND circuit; an output signal of the third AND circuit to a data terminal via a delay circuit; and an output signal of the first AND circuit to a clock terminal. Each of the flip-flops includes a flip-flop to be input, and a fourth AND circuit that inputs an output signal of the flip-flop and an output signal of the first AND circuit.

The common disconnection detecting unit 3 includes a plurality of packages 2
A clock signal of the same frequency distributed to -1 to 2-n is used as an address signal, and when the address signal is other than all "1" and all "0", the read-only memory is configured to read a disconnection detection signal of the clock signal. Is done.

The common disconnection detecting section 3 includes a plurality of packages 2
-1 to 2-n, the sum of a clock signal of a different frequency to be supplied to each of the sequence signals and a sequence signal is used as an address signal, and the sequence signal is read out by the address signal. Is formed by a read only memory from which the disconnection detection signal is read.

[0011]

The clock generator 1 comprises a high-stability oscillator 5 such as a crystal oscillator and a frequency divider 6. If the frequency divider 6 is one, each of the packages 2-1 to 2-n Clock signals of the same frequency can be supplied to a plurality of frequency dividers, and when a plurality of frequency dividers of different frequency division ratios are provided, or when frequency dividers of the same frequency division ratio are cascaded, A signal can be provided. Clock generator 1
The clock signals CLK1 to CLKn are distributed and supplied to the clock signal lines via a buffer (BF) 7, and the clock signals CLK1 to CLKn are supplied to the mounted packages 2-1 to 2-n. The common disconnection detecting unit 3 receives the clock signals CLK1 to CLKn of each clock signal line, and when any one of the clock signals is disconnected, adds a disconnection detection signal to the latch circuit 4 and outputs a disconnection alarm from the latch circuit 4. Output a signal.

The clock generation unit 1 sends each package 2-
In the case of distributing and supplying clock signals of the same frequency to 1 to 2-n, the common disconnection detection unit 3 is configured by a logic circuit, and the first AND circuit is configured such that any one of the clock signals CLK1 to CLKn is fixed at a low level. Upon detecting that the disconnection has occurred, the second AND circuit detects that any one of the clock signals CLK1 to CLKn has been fixed at the high level. The third AND circuit is configured to output an output signal of “1” when the first and second AND circuits detect the disconnection of the low-level fixed clock signal or the high-level fixed clock signal, The output signal is applied to the data terminal of the flip-flop via a delay circuit,
The output signal of the AND circuit is applied to the clock terminal, so that the clock signal CLK1 and the clock signal CLK1 are disconnected.
When the mutual phases of ~ CLKn are shifted by more than the allowable value,
The output of the flip-flop becomes low level, so that a break of the clock signal and a phase shift can be detected.

When the common disconnection detecting section 3 is constituted by a read-only memory, a clock signal of the same frequency is used as an address signal, and when all are "1" or all "0",
That is, if the frequency is the same and the phase is the same, a signal determined to be normal is read from the read-only memory, and if the address signal is other than that, a detection signal of a cutoff or phase shift of the clock signal can be read.

When the frequency of each clock signal is different,
The read-only memory stores a sequence signal and a disconnection detection signal, and the sum of each clock signal and the sequence signal is used as an address signal. When each clock signal is normal, the next sequence signal is read. In the case of a clock signal interruption, a disconnection detection signal is read out without reading the next correct sequence signal.

[0015]

FIG. 2 is an explanatory view of one embodiment of the present invention, showing a case where a common disconnection detecting section is constituted by a logic circuit.
Is a first AND circuit (AND), 12 is a second AND circuit (AND), 13 is a third AND circuit (AND), 1
4 is a fourth AND circuit (AND), 15 is a flip-flop, 16 and 17 are inverters, and 18 is a delay circuit (D
L), 19 are mono-multi vibrators (MMV), PK
G1 to PKGn indicate the packages in FIG. 1 and show the case where the clock signals CLK1 to CLKn are respectively distributed via the buffer 7 in FIG.

The clock signals CLK1 to CLKn are the first
Is input to the AND circuit 11 and the inverter 16
And input to the second AND circuit 12.
Therefore, the clock signal CLK1 having the same frequency and the same phase
To CLKn, the clock signals CLK1 to CLKn
Is normal, it becomes all "1" or all "0". Therefore, the output signals of the AND circuits 11 and 12 are alternately inverted, and when the output signal of the AND circuit 11 is "0", The output signal becomes “1”, and the output signal of the AND circuit 11 is supplied via the inverter 17 to the third AND circuit 1.
3, the output signal of the AND circuit 13 repeats “1” and “0” corresponding to the clock signals CLK1 to CLKn, and is output to the data terminal D of the flip-flop 15 via the delay circuit 18. In addition, since the output signal of the AND circuit 11 is applied to the clock terminal C of the flip-flop 15, the output terminal Q of the flip-flop 15 maintains the high level. Therefore, the output signal of the fourth AND circuit 14 is the same as the output signal of the AND circuit 11, and the monomultivibrator 19 is triggered every cycle of the clock signals CLK1 to CLKn. The mono-multivibrator 19 corresponds to the latch circuit 4 of FIG. 1 and has a retrigger type configuration, outputs a predetermined time “0” when triggered, and outputs “1” when it is not triggered even after the predetermined time has elapsed. Is output.

FIG. 3 is a diagram for explaining the operation of one embodiment of the present invention. The clock signals CLK1 and CLK2 are normal.
When the clock signal CLK3 is in a cut-off state fixed to the low level L, the output signal of the AND circuit 11 becomes the low level L as shown in (a), and the output signal of the AND circuit 12 becomes the clock signal as shown in (b). CLK1, CLK2
Are inverted. Therefore, the AND circuit 13
Is the same as the output signal of the AND circuit 12, and is applied to the data terminal D of the flip-flop 15 via the delay circuit 18. However, flip-flop 15
Is applied with the output signal of the AND circuit 11 shown in (a), the output terminal Q of the flip-flop 15 becomes low level L as shown in (c). Accordingly, the output signal of the AND circuit 14 becomes low level L as shown in FIG.
Cannot be triggered, and a "1" clock disconnection detection signal is output.

On the other hand, when the clock signal CLK3 is turned off at the high level fixed to H, contrary to the above case, the output signal of the AND circuit 11 becomes the clock signal CL as shown in FIG.
K1 and CLK2 have the same phase, but the AND circuit 12
Is at a low level L as shown in FIG.
Accordingly, the output signal of the AND circuit 13 also becomes low level, so that the output terminal Q of the flip-flop 15 becomes low level as shown in FIG. As a result, the output signal of the AND circuit 14 also becomes the low level L, and the mono-multivibrator 19 cannot be triggered, so that the clock cutoff detection signal of "1" is output.

When the phase of the clock signal CLK3 is inverted with respect to the clock signals CLK1 and CLK2 as shown by CLK3 ', the output signals of the AND circuits 11 and 12 are as shown in (h) and (i). To a low level L. Therefore, the output signal of the AND circuit 13 is also at the low level L.
Since the output terminal Q of the flip-flop 15 is at the low level L as shown in (j), the trigger of the monomultivibrator 19 cannot be performed as in the case described above. Is output.

In the operation explanatory diagram of one embodiment of the present invention shown in FIG. 4, clock signals CLK1, CLK3, CLK
4, when the phase of the clock signal CLK2 is shifted by 90 °, the output signal of the AND circuit 11 becomes a pulse having half the pulse width of the clock signal as shown in FIG. Also, as shown in (b), the pulse becomes a half of the pulse width of the clock signal. Since the output signal of the AND circuit 11 is inverted by the inverter 17 and added to the AND circuit 13, the AND circuit 13
And the output signal of the AND circuit 12 is output as it is.
Then, a signal shown in (c) is generated via the delay circuit 18 and applied to the data terminal D of the flip-flop 15. The clock terminal C of the flip-flop 15 has (a)
, The output terminal Q of the flip-flop 15 is at the low level L as shown in FIG. Accordingly, the output signal of the AND circuit 14 also becomes the low level L as shown in (e), so that the monomultivibrator 19 cannot be triggered, and the clock cutoff detection signal of "1" is output.

When the phase of the clock signal CLK2 with respect to the clock signals CLK1 and CLK3 is less than the allowable value as shown by CLK2 ', the output signal of the AND circuit 11 becomes (f) and the output of the AND circuit 12 becomes (f). The signal is (g)
Respectively, and the output signal of the AND circuit 12 becomes a signal shown in FIG. 3 (h) via the delay circuit 18 and is applied to the data terminal D of the flip-flop 15. Accordingly, by applying the output signal of the AND circuit 11 to the clock terminal C, the output terminal Q of the flip-flop 15 becomes high level H as shown in FIG.
Since the output signal of No. 4 is as shown in (j), the monomultivibrator 19 is triggered. That is, the clock disconnection detection signal of “1” is not output.

Even if the flip-flop 15 is omitted, it operates as a common break detector, but the pulse width of the output signal of the AND circuit 14 may become very narrow, and the mono-multivibrator 19 may not be triggered. . In such a case, the operation is stabilized by providing the flip-flop 15 as shown in the embodiment of FIG. The mono multivibrator 19 is constituted by a counter reset by an output signal of the AND circuit 14, counts a clock signal (not shown), and outputs the clock signal CLK1.
When any one of .about.CLKn is cut off, an overflow signal is output by not being reset, so that it can be used as a clock cutoff detection signal.

FIG. 5 is an explanatory view of another embodiment of the present invention. Reference numeral 21 denotes a clock generator, 22-1 to 22-n denote packages (PKG1 to PKGn), and 23 denotes a lead constituting a common disconnection detector. Only memory (ROM), 24 is a flip-flop constituting a latch circuit, 25 is an oscillator,
6, 27 are frequency dividers, 28 is a buffer (BF), CLK1
CLKn is a clock signal, MCLK is a master clock signal, and ACLK is a disconnection detection clock signal.

The clock signals CLK1 to CLKn distributed to the respective packages 22-1 to 22-n from the clock generator 21 via the buffer 28 are supplied to the read only memory 2.
3 and the clock signal CL
When K1 to CLKn have the same frequency and the same phase, their address signals are all "1" or "0". The read-only memory 23 stores, for example, “0” for all “1” or all “0” address signals, and “1” for other pattern address signals. A disconnection detection clock signal ACLK applied to the clock terminal C of the flip-flop 24
Is twice the frequency of the clock signals CLK1 to CLKn. For example, when the flip-flop 24 sets the read signal of the read-only memory 23 applied to the data terminal D at the falling edge, the clock signals CLK1 to CLKn
When CLKn is normal, the output terminal Q of the flip-flop 24 is always "0". However, the clock signal CL
If any one of K1 to CLKn is disconnected or a phase shift of 以上 cycle or more occurs, “1” is read from the read-only memory 24, so that the output terminal Q of the flip-flop 24 becomes “1”. Become. That is, the disconnection of the clock signal is detected.

FIG. 6 is an explanatory view of still another embodiment of the present invention, in which 31 is a clock generator, 32 is an oscillator, and 33, 3
4, 35 and 36 are frequency dividers and 37 is a rising differentiating circuit (D
F), 38 to 41 are buffers (BF), 42 is a read only memory (ROM), 43 is a 1-bit shift latch circuit, 44 is a flip-flop, CLKA and CLK
B, CLKC and CLKD are clock signals having different frequencies.

In this embodiment, a plurality of packages (not shown) are provided from the clock generator 31 to the buffers 38 to 41.
Clock signals CLKA having different frequencies through
To supply the clock signals CLKB to CLKD.
This shows the case where the disconnection of CLKD is detected.
Assuming that each of 3 to 36 has the same configuration that divides by two,
Frequency FA to FD of clock signals CLKA to CLKD
Has a relationship of FA = 2 · FB = 4 · FC = 8 · FD.

A sequence signal from the read only memory 42 is input to the data terminal D of the latch circuit 43,
The clock signal CLKA is input to the clock terminal C, and the output signal of the rising differentiating circuit 37 is input to the reset terminal R. Also, the clock signal CL is supplied to the read only memory 42.
KB to CLKD and an output signal from the output terminal Q of the latch circuit 43 are applied as an address signal, and a sequence signal and a signal indicating the presence or absence of a clock interruption are read out. This signal is applied to the data terminal D of the flip-flop 44. And
The clock signal CLKA is applied to the clock terminal C, and a signal indicating whether or not the clock is disconnected is output from the output terminal Q.

FIGS. 7A to 7D are diagrams for explaining the operation of still another embodiment of the present invention. FIGS. 7A to 7D show clock signals CLKA to CLKC.
LKD, (e) is an output signal of the rising differentiating circuit 37,
(F) shows an address signal based on the clock signals CLKB to CLKD, and (g) shows a sequence signal. That is, the time t
1, the clock signals CLKB to CLKD are all “1”, and the resulting address signal is “1”.
11 "= 7 and the sequence signal becomes" 001 "= 1. At the next time t2, the clock signal CLKB
The address signal by .about.CLKD is "110" = 6, and the sequence signal is "010" = 2. At this time,
At time t1, the sequence signal “1” read and the address signal “6” by the clock signals CLKB to CLKD are applied to the read-only memory 42.

At the next time t3, the clock signal C
The address signal by LKB to CLKD is “101” =
5 and the sequence signal becomes “011” = 3. At this time, “2” of the sequence signal read at time t2 and an address signal based on clock signals CLKB to CLKD are applied to read-only memory 42. Thereafter, the read-only memory 42 is accessed similarly. That is, if the clock signals CLKB to CLKD are normal, the access address of the read-only memory 42 is "7" which is the sum of the clock signals CLKB to CLKD and the sequence signal read out one time earlier. Means that the read only memory 42 is configured to read "0" indicating that the clock is not cut off. Then, after the time t8, the clock signal C
At the rising timing of LKD, the rising differential circuit 37 outputs the signal shown in (e), and the latch circuit 43 is reset.

FIG. 8 is an explanatory diagram of the address and data as described above. Of the addresses A0 to A5, the lower three bits A0, A1 and A2 of the address are the clock signal CLK.
D, CLKC, CLKB, the upper 3
Bits A3, A4, and A5 are sequence signals of the output of the latch circuit 43 read out one time earlier, and the sequence signal is composed of three bits D1 of data D0 to D3 corresponding to the address of the read-only memory 42. , D2, D3
It is. The least significant bit D0 indicates a disconnection detection signal. In the case of an address other than that shown, the data D0 is "1".
This indicates disconnection detection. It is also possible to use 6 bits A0 to A5 as an access address of the read only memory 42, but (A0 to A2) + (A
It is also possible to use an address signal obtained by adding 3 to A5). In this case, if the clock signal is normal, the same access address (“111”) is always used.

The present invention is not limited to only the above-described embodiments, but includes a plurality of clock signals of the same frequency,
Even in a configuration in which a plurality of clock signals having different frequencies are mixed and distributed to the respective packages, the common disconnection detection unit can detect disconnection of at least one clock signal or a phase shift exceeding an allowable value. it can.

[0032]

As described above, according to the present invention, a clock signal having the same or different frequency is supplied from the clock generation unit 1 and distributed to a plurality of packages, and any one of the clock signals can be disconnected. A common disconnection detection circuit 3 for outputting a detection signal when the common disconnection detection circuit 3
Input, including the clock signal to be distributed and supplied
Logic circuits or flip-flops using circuits or flip-flops, etc.
When the clock signal is cut off and the phase
Outputs a detection signal when the deviation exceeds the allowable value and increases.
In a device equipped with multiple packages,
There is an advantage that it is possible to monitor whether or not the clock signal is normal .

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of one embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of one embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of one embodiment of the present invention.

FIG. 5 is an explanatory diagram of another embodiment of the present invention.

FIG. 6 is an explanatory view of still another embodiment of the present invention.

FIG. 7 is an operation explanatory view of still another embodiment of the present invention.

FIG. 8 is an explanatory diagram of addresses and data.

FIG. 9 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Clock generation part 2-1-2-n Package (PKG1-PKGn) 3 Common disconnection detection part 4 Latch circuit 5 Oscillator 6 Divider 7 Buffer (BF)

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-79122 (JP, A) JP-A-63-79121 (JP, A) JP-A-62-202238 (JP, A) JP-A-61-202 98425 (JP, A)

Claims (3)

(57) [Claims] 1. A clock signal having the same or different frequency to be distributed and supplied to a plurality of packages (2-1 to 2-n) from a clock generation unit (1), and at least one of the clock signals is cut off. And a latch circuit (4) for latching the detection signal of the common disconnection detection unit (3) and outputting a disconnection alarm signal.
With the door, the common loss detection unit (3), said plurality of packages (2
-1 to 2-n) clock signals of the same frequency to be distributed and supplied
The first AND circuit inputs the signal as it is,
A second AND circuit to be activated and an output of the first AND circuit.
And an output signal of the second AND circuit.
And a third AND circuit for inputting a signal
Output signal of the path to a data terminal via a delay circuit,
Input the output signal of the AND circuit of
Flip-flop to output and the output of the flip-flop
A signal and an output signal of the first AND circuit,
A clock disconnection detection circuit comprising: an AND circuit according to (4 ). 2. The method according to claim 1, wherein a plurality of packages are provided from a clock generator.
Same or different to be distributed to the pages (2-1 to 2-n)
Input a clock signal of at least one of
Outputs a detection signal when one clock signal is interrupted.
The detection signals of the disconnection detection unit (3) and the common disconnection detection unit (3) are
Latch circuit for latching and outputting disconnection alarm signal (4)
And the common disconnection detection unit (3) includes the plurality of packages (2
-1 to 2-n) are clock signals of the same frequency to be supplied and supplied as address signals, and the address signals are all "1".
And a signal for detecting a disconnection of the clock signal when the signal is not all "0"
That the read-only memory
Characteristic clock disconnection detection circuit. 3. The method according to claim 1, wherein a plurality of packages are provided from the clock generator.
Same or different to be distributed to the pages (2-1 to 2-n)
Input a clock signal of at least one of
Outputs a detection signal when one clock signal is interrupted.
The detection signals of the disconnection detection unit (3) and the common disconnection detection unit (3) are
Latch circuit for latching and outputting disconnection alarm signal (4)
And the common disconnection detection circuit (3) includes a plurality of packages (2-1 to 2-n) each having a different frequency.
The sum of the number of clock signals and the sequence signal
And the sequence signal is changed by the address signal.
The data is read out and the clock signal is
Read-only memory for reading the disconnection detection signal of the lock signal
A clock disconnection detection circuit characterized by comprising: