JP2699468B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2699468B2
JP2699468B2 JP25847088A JP25847088A JP2699468B2 JP 2699468 B2 JP2699468 B2 JP 2699468B2 JP 25847088 A JP25847088 A JP 25847088A JP 25847088 A JP25847088 A JP 25847088A JP 2699468 B2 JP2699468 B2 JP 2699468B2
Authority
JP
Japan
Prior art keywords
wafer
back surface
ion implantation
grinding
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP25847088A
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Japanese (ja)
Other versions
JPH02105526A (en
Inventor
輝夫 飯野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Publication date
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Publication of JPH02105526A publication Critical patent/JPH02105526A/en
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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はIC,LSI等の半導体装置の製造方法に関し、特
に、イオン注入後の半導体ウェハー裏面の処理方法に関
する。
Description: BACKGROUND OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device such as an IC or an LSI, and more particularly to a method for processing the back surface of a semiconductor wafer after ion implantation.

〔従来の技術〕[Conventional technology]

近年、高密度MOS LSIを構成するMOSトランジスタのソ
ース、ドレイン領域を形成するのに、不純物拡散の半導
体表面および深さ方向の両方に対してより精密な制御が
可能なイオン注入法を用いることが多くなっている。こ
のような高濃度不純物領域を生産性良く形成するには、
当然イオン注入時の電流値は数〜10mA程度と大きくな
る。このようにイオン注入時の電流密度が大きくなる
と、ウェハーが発熱しイオン注入のマスクとなっている
フォトレジスト膜の変質やデバイス特性の劣化の問題が
起るため、この種の高電流イオン注入装置では、イオン
注入時のウェハー温度上昇を防ぐ目的でウェハー冷却機
構を設けているのが普通である。例えばバリアン社製の
高電流イオン注入装置では、イオン注入中に、ウェハー
裏面にシリコンゴムを押し付けてウェハーを冷却してい
る。即ち、通常の冷却用金属板をウェハー裏面に押し付
けても、この金属板がウェハー裏面と均一に密着しない
ため、有機材料のうちで、弾力性,耐熱性および熱伝導
性に優れたシリコンゴムがウェハー冷却用材料として用
いられているものである。
In recent years, in order to form the source and drain regions of MOS transistors that make up high-density MOS LSIs, it has been necessary to use an ion implantation method that can more precisely control both the semiconductor surface and the depth direction of impurity diffusion. More. To form such a high concentration impurity region with high productivity,
Naturally, the current value at the time of ion implantation is as large as about several to 10 mA. If the current density at the time of ion implantation becomes large as described above, the wafer generates heat, causing a problem of deterioration of a photoresist film used as a mask for ion implantation and deterioration of device characteristics. In general, a wafer cooling mechanism is provided for the purpose of preventing a wafer temperature from rising during ion implantation. For example, in a high-current ion implantation apparatus manufactured by Varian, the silicon rubber is pressed against the back surface of the wafer during ion implantation to cool the wafer. That is, even if a normal metal plate for cooling is pressed against the back surface of the wafer, the metal plate does not uniformly adhere to the back surface of the wafer, so that among the organic materials, silicon rubber having excellent elasticity, heat resistance and thermal conductivity is used. It is used as a wafer cooling material.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上述した従来の大電流イオン注入装置のウェハー冷却
方法は、以下の問題点がある。即ち、イオン注入時にウ
ェハー裏面がシリコンゴムに密着しているため、大量の
有機物がウェハー裏面に付着する。例えば、バリアン社
製の大電流イオン注入装置Extrion 80−10において、不
純物として砒素を選択し、イオン注入条件として加速電
圧80KV,ビーム電流8.0mAで不純物濃度が1016/cm2になる
まで注入したシリコンウェハーの裏面を光学顕微鏡を暗
視野にして観察すると、0.3μm以上の粒子が100〜200
ケ/cm2程度付着していることが確認された。このウェハ
ー裏面に付着した粒子を2次イオン質量分析法(Second
ary Ion Mass Spectrometer)で元素成分を分析したと
ころ、炭素,ナトリウム,カリウム,アルミニウム等MO
Sデバイスの特性を劣化させる、汚染物質が検出され
た。そこで、本願発明者は汚染粒子が裏面に付着したウ
ェハーを現行の通常の方法で洗浄してみた。即ち、下記
の2種類の洗浄液にウェハーを所定時間浸漬した後、純
水ですすいで遠心乾燥機で乾燥させた。
The above-described conventional wafer cooling method of the large current ion implanter has the following problems. That is, since the back surface of the wafer is in close contact with the silicon rubber at the time of ion implantation, a large amount of organic substances adhere to the back surface of the wafer. For example, in a high-current ion implantation apparatus Extrin 80-80 manufactured by Varian, arsenic was selected as an impurity, and implantation was performed until the impurity concentration reached 10 16 / cm 2 at an acceleration voltage of 80 KV and a beam current of 8.0 mA as ion implantation conditions. When observing the back surface of the silicon wafer with an optical microscope in the dark field, particles of 0.3 μm or more are 100 to 200
It was confirmed that the particles had adhered to about 10 cm / cm 2 . The particles attached to the back of the wafer are analyzed by secondary ion mass spectrometry (Second
Analysis of elemental components using an ary ion mass spectrometer) revealed that the MO of carbon, sodium, potassium, aluminum, etc.
Contaminants have been detected that degrade the characteristics of the S device. Then, the inventor of the present application tried cleaning the wafer on which the contaminant particles adhered to the back surface by a current usual method. That is, the wafer was immersed in the following two kinds of cleaning liquids for a predetermined time, rinsed with pure water, and dried with a centrifugal dryer.

アンモニア水と過酸化水素水との混合液 (液温90℃) 硫酸と過酸化水素水との混合液 (液温120℃) 上記2種類の方法で洗浄したウェハーの裏面を光学顕
微鏡で観察したところ、ウェハー裏面上の粒径0.3μm
以上の粒子は100〜200ケ/cm2程度と洗浄前とほとんど変
化していないことが確認された。
Mixed solution of ammonia water and hydrogen peroxide solution (solution temperature 90 ° C) Mixed solution of sulfuric acid and hydrogen peroxide solution (solution temperature 120 ° C) The back surface of the wafer cleaned by the above two methods was observed with an optical microscope. However, the particle size on the back of the wafer is 0.3 μm
It was confirmed that the above particles were almost 100 to 200 / cm 2, which was almost the same as before cleaning.

以上より、現行の大電流イオン注入法ではシリコンウ
ェハーの裏面が冷却用のシリコンゴムと接触して大量の
粒子が付着し、その後の洗浄でも除去されないという問
題が見出された。
From the above, it has been found that in the current high-current ion implantation method, a large amount of particles adhere to the back surface of the silicon wafer in contact with the silicon rubber for cooling and cannot be removed by subsequent washing.

イオン注入により不純物を導入されたシリコンウェハ
ーは、その後、熱処理により、電気的に活性な高濃度拡
散領域を形成する必要がある。この時、イオン注入時に
おいてウェハー裏面に付着した有機物が汚染源となり、
そのウェハーおよび熱処理炉をも汚染してしまいMOS LS
Iの特性および歩留りに重大な影響を与えることが、本
願発明者の検討により明らかとなった。
The silicon wafer into which the impurities have been introduced by ion implantation must then be subjected to heat treatment to form electrically active high-concentration diffusion regions. At this time, organic substances attached to the back surface of the wafer during ion implantation become a source of contamination,
MOS LS also contaminates the wafer and heat treatment furnace
It has been clarified by the study of the present inventor that it has a significant effect on the characteristics and yield of I.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の半導体装置の製造方法は、 半導体基板の裏面に該半導体基板の冷却用部材を密着
させた状態で、該半導体基板の主面に選択的に不純物を
導入する工程と、 前記冷却用部材を除去した後、該冷却用部材と接触し
ていた半導体基板裏面を研削する工程とを有している。
The method of manufacturing a semiconductor device according to the present invention includes: a step of selectively introducing an impurity into a main surface of the semiconductor substrate in a state in which a cooling member of the semiconductor substrate is in close contact with a back surface of the semiconductor substrate; And then grinding the back surface of the semiconductor substrate that has been in contact with the cooling member.

〔作用〕[Action]

イオン注入後ウェハー裏面のシリコンを2μm程度研
削することにより、通常の洗浄方法では除去不可能であ
ったイオン注入時にウェハー裏面に付着したゴミを完全
に除去し、熱処理炉やウェハー自体の汚染を格段に低減
できるようになる。
After the ion implantation, the silicon on the back surface of the wafer is ground by about 2 μm to completely remove dust adhering to the back surface of the wafer at the time of ion implantation, which cannot be removed by a normal cleaning method. Can be reduced.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明す
る。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(e)は本発明の半導体装置の製造方
法の一実施例の工程断面図である。
1 (a) to 1 (e) are process cross-sectional views of one embodiment of a method for manufacturing a semiconductor device according to the present invention.

まず、最初に、シリコンウェハー1上の主面10上にイ
オン注入のマスクとなるポジレジストパターン11を形成
する。このレジストパターンは、例えば、東京応化工業
製のポジ型レジストOFPR−800を1.35μmの厚さに塗布
し、日本光学製の縮小投影露光装置NSR−1505Gにより3
a,3bの部分のみ選択的に露光し、その後、水酸化テトラ
メチルアンモニウムの水溶液を主成分とする現像液で現
像処理を行なって3a,3bの部分のレジスト膜を除去する
ことによって行う。その後、シリコンウェハー1に、ホ
ットプレート上で120℃,3分間の加熱処理を施しレジス
ト膜11の主面1に対する密着性を増大させる。(第1図
(a)) 続いて、バリアン社製のイオン注入装置Extrion 80−
10によりウェハー1の主面10上に砒素を注入する。注入
条件は加速電圧80KV,ビーム電流8.0mAで、注入された砒
素の濃度は1016atms・cm-2となり、シリコンウェハー1
の主面2の開口部3a,3bに砒素の高濃度不純物領域2a,2b
が形成される。一方、シリコンウェハー1の裏面20a上
には、注入時にシリコンゴムと密着したため有機物4a,4
b,4cが付着している。(第1図(b)) 次いで、シリコンウェハー1の主面上に、フジハント
エレクトロニクステクノロジー社製の高粘度ポジ型レジ
ストFH−PC 120C.P.を回転塗布法により約5μmの厚さ
に塗布し、その後、ホットプレート上で130℃,5分間の
加熱処理を行い、レジスト中の溶剤成分を蒸発させて、
裏面研削用の厚膜レジスト12を形成する。(第1図
(c)) 次に、シリコンウェハー1の裏面20aを機械的に厚さ
2μm程度研削して、研削裏面20bを形成する(第1図
(d))。このシリコンウェハーの裏面研削方法をより
詳細に説明すると、第2図に示すように、テフロン製の
ウェハーチャック30上に、ウェハー1を主面10を下にし
て置き、空孔部31を700〜750mmHg程度の真空度にする
と、ウェハー1はテフロンチャック30上に固定される。
また、ディスコ社製のシリコン研削用の円盤形CBD砥石
(Ceramic bonded diamond)40を金属性回転軸41に接続
固定させる。このとき、砥石40のサイズはウェハー1と
ほぼ同一のものを使用し、両者の位置関係は、ちょうど
互いにウェハー1の半径の長さだけずれ、かつ円盤砥石
40はウェハー1より若干上に位置している。その後ウェ
ハーチャック30を中心軸31を中心とし、また円盤砥石40
は中心軸41を中心として、回転数1000回転/分で回転さ
せ、ウェハー1裏面20上に純水を適量注ぎながら、回転
している円盤砥石40を回転軸41と共に降下させ、ほぼ、
1.2Kgの荷重でもってウェハー1の裏面20上に同砥石40
を押しつける。この研削方法では、砥石中に含まれてい
るダイヤモンド微粒子が析出して、シリコン表面を0.5
μm/分の速度で研削していく。従ってこの方法で研削を
始めて4分程度経過すると、ウェハー1の表面20は2.0
μ程度研削され、新たに裏面20bが形成され裏面20aに付
着した有機物4a,4b,4cはシリコンとともに完全に除去さ
れる。
First, a positive resist pattern 11 serving as a mask for ion implantation is formed on the main surface 10 on the silicon wafer 1. This resist pattern is applied, for example, by coating a positive resist OFPR-800 manufactured by Tokyo Ohka Kogyo Co., Ltd. to a thickness of 1.35 μm, and applying a reduction projection exposure apparatus NSR-1505G manufactured by Nippon Kogaku.
The exposure is performed by selectively exposing only the portions a and 3b, and thereafter performing a developing process using a developing solution mainly containing an aqueous solution of tetramethylammonium hydroxide to remove the resist film in the portions 3a and 3b. Thereafter, the silicon wafer 1 is subjected to a heat treatment at 120 ° C. for 3 minutes on a hot plate to increase the adhesion of the resist film 11 to the main surface 1. (Fig. 1 (a)) Next, an ion implantation apparatus Extrin 80-
Arsenic is implanted on the main surface 10 of the wafer 1 by 10. The implantation conditions were an acceleration voltage of 80 KV and a beam current of 8.0 mA, and the concentration of the implanted arsenic was 10 16 atms · cm -2 .
Arsenic high concentration impurity regions 2a, 2b are formed in openings 3a, 3b of main surface 2 of
Is formed. On the other hand, on the back surface 20a of the silicon wafer 1, the organic substances 4a and 4
b and 4c are attached. (FIG. 1 (b)) Next, a high-viscosity positive resist FH-PC 120C.P. manufactured by Fuji Hunt Electronics Technology Co., Ltd. is applied on the main surface of the silicon wafer 1 to a thickness of about 5 μm by a spin coating method. After that, heat treatment at 130 ° C for 5 minutes on a hot plate to evaporate the solvent component in the resist,
A thick film resist 12 for backside grinding is formed. (FIG. 1 (c)) Next, the back surface 20a of the silicon wafer 1 is mechanically ground to a thickness of about 2 μm to form a ground back surface 20b (FIG. 1 (d)). The backside grinding method of the silicon wafer will be described in more detail. As shown in FIG. 2, the wafer 1 is placed on a Teflon wafer chuck 30 with the main surface 10 down, and the holes 31 When the degree of vacuum is set to about 750 mmHg, the wafer 1 is fixed on the Teflon chuck 30.
In addition, a disk-shaped CBD grinding wheel (Ceramic bonded diamond) 40 for silicon grinding manufactured by Disco Corporation is connected and fixed to the metallic rotating shaft 41. At this time, the size of the grindstone 40 is almost the same as that of the wafer 1, and the positional relationship between the two is exactly shifted by the radius of the wafer 1, and
40 is located slightly above wafer 1. After that, the wafer chuck 30 is centered on the central axis 31 and the disk grinding wheel 40
Is rotated around the central axis 41 at a rotation speed of 1000 revolutions / minute, and while pouring an appropriate amount of pure water onto the back surface 20 of the wafer 1, the rotating disk grindstone 40 is lowered together with the rotating shaft 41.
The whetstone 40 is placed on the back surface 20 of the wafer 1 with a load of 1.2 kg.
Press. In this grinding method, diamond fine particles contained in the grinding wheel are precipitated, and the silicon surface is reduced by 0.5%.
Grind at a speed of μm / min. Therefore, when about 4 minutes have elapsed after the start of the grinding by this method, the surface 20 of the wafer 1 becomes 2.0
The back surface 20b is newly formed by grinding by about μ, and the organic substances 4a, 4b, and 4c attached to the back surface 20a are completely removed together with the silicon.

続いて120℃に加熱した硫酸と過酸化水素水との混合
液にウェハー1を浸漬して、レジスト膜11および12を除
去し、さらに90℃に加熱したアンモニア水と過酸化水素
水との混合液に浸漬してウェハー1を洗浄する。この段
階で、光学顕微鏡でウェハー1の裏面20を観察した所、
粒径0.3μm以上の付着物は0.1ケ/cm2以下とほぼ裏面研
削程度前の1/1000以下に減少し、ほぼ問題ないレベルで
あることが確認された。最後にウェハー1にN2雰囲気中
で950℃,30分の熱処理を加えると、不純物拡散領域2a,2
bは電気的に活性な高濃度N型拡散領域が完成する(第
1図(e))。
Subsequently, the wafer 1 is immersed in a mixed solution of sulfuric acid and hydrogen peroxide heated to 120 ° C. to remove the resist films 11 and 12, and further mixed with ammonia water and hydrogen peroxide heated to 90 ° C. The wafer 1 is washed by being immersed in the liquid. At this stage, when the back surface 20 of the wafer 1 was observed with an optical microscope,
Deposits having a particle size of 0.3 μm or more were reduced to 0.1 particles / cm 2 or less, almost 1/1000 or less before back grinding, and it was confirmed that the level was almost no problem. Finally, when the wafer 1 is subjected to a heat treatment at 950 ° C. for 30 minutes in an N 2 atmosphere, the impurity diffusion regions 2a, 2
For b, an electrically active high-concentration N-type diffusion region is completed (FIG. 1 (e)).

第3図はウェハー研削方法の他の例を示す装置断面図
である。
FIG. 3 is an apparatus sectional view showing another example of the wafer grinding method.

テフロン製のウェハーチャック30上にウェハー1を主
面10を下にして置き、空孔部分を700〜750mmHg程度の真
空度にすると、ウェハー1はテフロンチャック30上に固
定される。そして、空孔部51を有する円筒状のステンレ
ス製ノズル50を、ウェハー1の裏面上10mmの所にノズル
50の先端52が位置する様に垂直に設置し、かつ平面的に
ノズル50はウェハー1の少なくとも直径部分の長さだけ
移動可能な機構を有している。そして、ウェハーチャッ
ク30を中心軸31を中心にして、回転数4000回転/分で回
転させる。その後ノズル50の空孔部51よりアルミナ(Al
2O3)の微粒子60を空気とともに吹き出し、ウェハー1
の裏面20a上に吹きつける。このとき、微粒子の直径は
0.5〜10μm程度のものを使用し、ノズル50から吹き出
す空気の速度は50m/sec程度に調節する。この状態でノ
ズル50をウェハー1の直径方向に所定の速度でアルミナ
微粒子60がウェハー1の裏面20a上に均一に当たる様に
移動すると、ウェハー1の裏面20aのシリコンウェハー
は研削され、研削の深さが2μ程度になると、裏面20b
が形成され、裏面20に付着していた有機物4a,4b,4cはシ
リコンとともに完全に除去される。なお、この後、120
℃に加熱したアルキルベンゼンスルホン酸とオルト−ジ
クロロベンゼンを主成分とするレジスト剥離剤中にウェ
ハー1を5分間浸漬して、レジスト膜11および12を除去
し、さらに130℃に加熱した硫酸と過酸化水素水との混
合液に10分程度浸漬し、純水によるすすぎ洗いおよび遠
心脱水法によりウェハー1上の水分を除去して、ウェハ
ー1の洗浄を完了する。その後、光学顕微鏡でウェハー
1の裏面20を暗視野で観察した所、粒径0.3μm以上の
付着物は0.1ケ/cm2以下とイオン注入直後のほぼ1/1000
以下に減少しほぼ問題ないレベルであることが確認され
た。
The wafer 1 is fixed on the Teflon chuck 30 when the wafer 1 is placed on the wafer chuck 30 made of Teflon with the main surface 10 down, and the vacant portion is evacuated to a degree of vacuum of about 700 to 750 mmHg. Then, a cylindrical stainless steel nozzle 50 having a hole 51 is placed at a position 10 mm above the back surface of the wafer 1.
The nozzle 50 is installed vertically so that the tip 52 of the wafer 50 is located, and has a mechanism capable of moving the nozzle 50 in a plane by at least the length of the diameter portion of the wafer 1. Then, the wafer chuck 30 is rotated about the central axis 31 at a rotation speed of 4000 revolutions / minute. After that, the alumina (Al
The fine particles 60 of 2 O 3 ) are blown out together with air, and the wafer 1
Spray on the back surface 20a of the. At this time, the diameter of the fine particles is
A nozzle having a diameter of about 0.5 to 10 μm is used, and the speed of the air blown from the nozzle 50 is adjusted to about 50 m / sec. In this state, when the alumina fine particles 60 are moved at a predetermined speed in the diameter direction of the wafer 1 so as to uniformly hit the back surface 20a of the wafer 1, the silicon wafer on the back surface 20a of the wafer 1 is ground, and the grinding depth is reduced. Is about 2μ, the back surface 20b
Are formed, and the organic substances 4a, 4b, 4c attached to the back surface 20 are completely removed together with the silicon. After this, 120
The wafer 1 was immersed for 5 minutes in a resist stripping agent containing alkylbenzenesulfonic acid and ortho-dichlorobenzene as main components heated to 130 ° C. to remove the resist films 11 and 12, and further heated to 130 ° C. with sulfuric acid and peroxide. The wafer 1 is immersed in a mixed solution with hydrogen water for about 10 minutes, rinsed with pure water and centrifugally dehydrated to remove water on the wafer 1, thereby completing the cleaning of the wafer 1. After that, when the back surface 20 of the wafer 1 was observed in a dark field with an optical microscope, the number of deposits having a particle size of 0.3 μm or more was 0.1 particles / cm 2 or less, almost 1/1000 immediately after ion implantation.
It was confirmed that the level decreased to the following level, which was almost no problem.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明はイオン注入後ウェハー裏
面を研削することにより、従来除去不可能であったイオ
ン注入時にウェハー裏面に付着する有機物を完全に除去
できる効果がある。これにより、その後の拡散層形成用
の熱処理炉の汚染が従来に比べて格段に低減されるとと
もに、熱処理により半導体ウェハー中に取り込まれる炭
素,ナトリウム,カリウム,アルミニウム等のMOSデバ
イスの特性を劣化させる汚染物質が極めて低減され、MO
Sデバイスの特性および歩留りの向上が図れる。
As described above, the present invention has the effect of completely removing the organic matter adhering to the back surface of the wafer at the time of ion implantation, which was impossible to remove conventionally, by grinding the back surface of the wafer after ion implantation. As a result, contamination of the subsequent heat treatment furnace for forming the diffusion layer is significantly reduced as compared with the conventional case, and the characteristics of MOS devices such as carbon, sodium, potassium, and aluminum which are taken into the semiconductor wafer by the heat treatment are deteriorated. Pollutants are significantly reduced and MO
The characteristics and yield of the S device can be improved.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(e)は本発明の半導体装置の製造方法
の一実施例の工程断面図、第2図はウェハー裏面の研削
方法を示す装置断面図、第3図はウェハー裏面の研削方
法の他の例を示す装置断面図である。 1……シリコンウェハー、 2a,2b……不純物領域、 3a,3b……露光領域、 10……ウェハー主面、 11……ポジレジストパターン、 12……厚膜レジスト層、 4a,4b,4c……有機物、 20a,20b……裏面研削後のウェハー裏面、 30……ウェハーチャック、 31……ウェハーチャック空孔部、 30c……ウェハーチャック中心線、 40……CBD砥石、 41……砥石回転軸、 40c……砥石回転軸中心線、 50……ノズル、 51……ノズル空孔部、 60……アルミナ微粒子。
1 (a) to 1 (e) are process cross-sectional views of an embodiment of a method of manufacturing a semiconductor device according to the present invention, FIG. 2 is a device cross-sectional view showing a method of grinding the back surface of a wafer, and FIG. It is an apparatus sectional view showing other examples of a grinding method. 1 ... silicon wafer, 2a, 2b ... impurity region, 3a, 3b ... exposure region, 10 ... wafer main surface, 11 ... positive resist pattern, 12 ... thick resist layer, 4a, 4b, 4c ... … Organic matter, 20a, 20b… back side of wafer after grinding back side, 30… wafer chuck, 31… wafer chuck hole, 30c… wafer chuck center line, 40… CBD grinding wheel, 41… grinding wheel rotation axis , 40c: Center line of the grindstone rotation axis, 50: Nozzle, 51: Nozzle hole, 60: Fine alumina particles.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板の裏面に該半導体基板の冷却用
部材を密着させた状態で、該半導体基板の主面に選択的
に不純物を導入する工程と、 前記冷却用部材を除去した後、該冷却用部材と接触して
いた半導体基板裏面を研削する工程とを有する半導体装
置の製造方法。
A step of selectively introducing an impurity into a main surface of the semiconductor substrate in a state in which the cooling member of the semiconductor substrate is in close contact with the back surface of the semiconductor substrate; and after removing the cooling member, Grinding the back surface of the semiconductor substrate in contact with the cooling member.
JP25847088A 1988-10-14 1988-10-14 Method for manufacturing semiconductor device Expired - Lifetime JP2699468B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25847088A JP2699468B2 (en) 1988-10-14 1988-10-14 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25847088A JP2699468B2 (en) 1988-10-14 1988-10-14 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02105526A JPH02105526A (en) 1990-04-18
JP2699468B2 true JP2699468B2 (en) 1998-01-19

Family

ID=17320671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25847088A Expired - Lifetime JP2699468B2 (en) 1988-10-14 1988-10-14 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2699468B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002324773A (en) * 2001-04-25 2002-11-08 Nec Corp Manufacturing method for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002324773A (en) * 2001-04-25 2002-11-08 Nec Corp Manufacturing method for semiconductor device

Also Published As

Publication number Publication date
JPH02105526A (en) 1990-04-18

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